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Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits © Digital Integrated Circuits2nd Sequential Circuits Naming Conventions In our text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edgetriggered elements flip-flops This leads to confusion however © Digital Integrated Circuits2nd Sequential Circuits Latch versus Register Latch stores data when clock is low D Q D Q Clk Clk Clk Clk D D Q Q © Digital Integrated Circuits2nd Register stores data when clock rises Sequential Circuits Latch-Based Design • N latch is transparent when f = 0 • P latch is transparent when f = 1 f N Latch Logic P Latch Logic © Digital Integrated Circuits2nd Sequential Circuits Timing Definitions CLK t tsu D © Digital Integrated Circuits2nd D thold DATA STABLE Q CLK t tc 2 Q Register q DATA STABLE t Sequential Circuits Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states CLK CLK Q CLK D D CLK D CLK Converting into a MUX © Digital Integrated Circuits2nd Forcing the state (can implement as NMOS-only) Sequential Circuits Mux-Based Latches Negative latch Positive latch (transparent when CLK= 0) (transparent when CLK= 1) 1 D 0 Q 0 D Q 1 CLK CLK Q Clk Q Clk In © Digital Integrated Circuits2nd Q Clk Q Clk In Sequential Circuits Edge-Triggered Flip-flop © Digital Integrated Circuits2nd Sequential Circuits Static SR Flip-Flop Clock version? Writing data by pure force No clock needed (Asynchronous) © Digital Integrated Circuits2nd Sequential Circuits Registers for Pipelining + © Digital Integrated Circuits2nd Sequential Circuits Registers for Pipelining ? Pipelined © Digital Integrated Circuits2nd Sequential Circuits Semiconductor Memories © Digital Integrated Circuits2nd Sequential Circuits Memory Memory Classification Memory Architectures The Memory Core Periphery © Digital Integrated Circuits2nd Sequential Circuits Semiconductor Memory Classification Read-Write Memory Random Access Non-Random Access SRAM FIFO DRAM LIFO Non-Volatile Read-Write Memory Read-Only Memory EPROM Mask-Programmed E2PROM Programmable (PROM) FLASH Shift Register CAM © Digital Integrated Circuits2nd Sequential Circuits Memory Timing: Definitions Read Cycle READ Read Access Read Access Write Cycle WRITE Write Access Data Valid DATA Data Written © Digital Integrated Circuits2nd Sequential Circuits Memory Architecture: Decoders M bits S0 S0 Word 0 S1 Word 1 S2 Word 2 SN 2 2 Nwords SN 2 M bits 1 Storage cell Word 0 A0 Word 1 A1 Word 2 A K2 1 Word N 2 2 Word N 2 1 Decoder Word N 2 Storage cell 2 Word N 2 1 K 5 log2N Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals © Digital Integrated Circuits2nd Input-Output (M bits) Decoder reduces the number of select signals K = log2N Sequential Circuits Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH AK AK+1 AL-1 Bit Line Storage Cell Row Decoder 2L-K Word Line M.2K Sense Amplifiers / Drivers A0 Column Decoder AK -1 Amplify swing to rail-to-rail amplitude Selects appropriate word Input-Output (M bits) © Digital Integrated Circuits2nd Sequential Circuits Hierarchical Memory Architecture Row Address Column Address Block Address Global Data Bus Control Circuitry Block Selector Global Amplifier/Driver I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings © Digital Integrated Circuits2nd Sequential Circuits Read-Only Memory Cells (ROM) BL BL BL VDD WL WL WL 1 BL WL BL BL WL WL 0 GND Diode ROM © Digital Integrated Circuits2nd MOS ROM 1 MOS ROM 2 Sequential Circuits MOS OR ROM BL[0] BL[1] BL[2] BL[3] WL[0] V DD WL[1] WL[2] V DD WL[3] V bias Pull-down loads © Digital Integrated Circuits2nd Sequential Circuits MOS NOR ROM V DD Pull-up devices WL[0] GND WL [1] WL [2] GND WL [3] BL [0] © Digital Integrated Circuits2nd BL [1] BL [2] BL [3] Sequential Circuits MOS NOR ROM Layout Cell (9.5l x 7l) Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion © Digital Integrated Circuits2nd Sequential Circuits MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row © Digital Integrated Circuits2nd Sequential Circuits MOS NAND ROM Layout Cell (8l x 7l) Programmming using the Metal-1 Layer Only No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion © Digital Integrated Circuits2nd Sequential Circuits Precharged MOS NOR ROM f V DD pre Precharge devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. © Digital Integrated Circuits2nd Sequential Circuits Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Gate Source D Drain G tox tox n+ p n+_ S Substrate Device cross-section © Digital Integrated Circuits2nd Schematic symbol Sequential Circuits Floating-Gate Transistor Programming 20 V 10 V S 5V 0V 20 V D Avalanche injection © Digital Integrated Circuits2nd 2 5V S 5V 0V D Removing programming voltage leaves charge trapped 2 2.5 V S 5V D Programming results in higher V T . Sequential Circuits FLOTOX EEPROM Gate Floating gate I Drain Source 20–30 nm V GD -10 V 10 V n1 n1 Substrate p 10 nm FLOTOX transistor © Digital Integrated Circuits2nd Fowler-Nordheim I-V characteristic Sequential Circuits EEPROM Cell BL WL VDD © Digital Integrated Circuits2nd Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell Sequential Circuits Flash EEPROM Control gate Floating gate erasure n 1 source Thin tunneling oxide programming n 1 drain p-substrate Many other options … © Digital Integrated Circuits2nd Sequential Circuits Cross-sections of NVM cells Flash © Digital Integrated Circuits2nd EPROM Courtesy Intel Sequential Circuits Characteristics of State-of-the-art NVM © Digital Integrated Circuits2nd Sequential Circuits Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended © Digital Integrated Circuits2nd Sequential Circuits 6-transistor CMOS SRAM Cell WL V DD M2 M5 Q M1 BL © Digital Integrated Circuits2nd M4 Q M6 M3 BL Sequential Circuits CMOS SRAM Analysis (Read) WL V DD M4 BL Q= 0 M5 V DD Cbit © Digital Integrated Circuits2nd M1 Q= 1 V DD BL M6 V DD Cbit Sequential Circuits CMOS SRAM Analysis (Write) WL V DD M4 M5 Q= 1 M1 BL = 1 © Digital Integrated Circuits2nd M6 Q= 0 V DD BL = 0 Sequential Circuits 6T-SRAM — Layout VDD M2 M4 Q Q M1 M3 GND M5 BL © Digital Integrated Circuits2nd M6 WL BL Sequential Circuits Resistance-load SRAM Cell WL V DD RL M3 BL RL Q Q M1 M2 M4 BL Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem © Digital Integrated Circuits2nd Sequential Circuits SRAM Characteristics © Digital Integrated Circuits2nd Sequential Circuits 3-Transistor DRAM Cell BL 1 BL 2 WWL WWL RWL M3 X M1 CS M2 RWL V DD 2 V T X BL 1 BL 2 V DD DV V DD 2 V T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL-VTn © Digital Integrated Circuits2nd Sequential Circuits 3T-DRAM — Layout BL2 BL1 GND RWL M3 M2 WWL M1 © Digital Integrated Circuits2nd Sequential Circuits 1-Transistor DRAM Cell BL WL Write "1" Read "1" WL M1 CS X VDD VT GND VDD BL VDD/2 CBL sensing VDD /2 Write: CS is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance CS ---------------------- V = VBL – V PRE = V BIT – V PRE C S + CBL Voltage swing is small; typically around 250 mV. © Digital Integrated Circuits2nd Sequential Circuits DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD © Digital Integrated Circuits2nd Sequential Circuits Sense Amp Operation V BL V(1) V PRE D V(1) V(0) Sense amp activated Word line activated © Digital Integrated Circuits2nd t Sequential Circuits 1-T DRAM Cell Capacitor M 1 word line Metal word line SiO2 Poly n+ Field Oxide n+ Poly Inversion layer induced by plate bias Cross-section © Digital Integrated Circuits2nd Diffused bit line Polysilicon gate Polysilicon plate Layout Sequential Circuits Periphery Decoders Sense Amplifiers © Digital Integrated Circuits2nd Sequential Circuits Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder © Digital Integrated Circuits2nd Sequential Circuits Hierarchical Decoders Multi-stage implementation improves performance ••• WL 1 WL 0 A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3 ••• NAND decoder using 2-input pre-decoders A1 A0 A0 A1 © Digital Integrated Circuits2nd A3 A2 A2 A3 Sequential Circuits Dynamic Decoders Precharge devices GND VDD GND WL 3 VDD WL 3 WL 2 WL 2 VDD WL 1 WL 1 V DD WL 0 WL 0 VDD f A0 A0 A1 A1 2-input NOR decoder © Digital Integrated Circuits2nd A0 A0 A1 A1 f 2-input NAND decoder Sequential Circuits 4-input pass-transistor based column decoder BL 0 BL 1 BL 2 BL 3 A0 S0 S1 S2 A1 S3 2-input NOR decoder D Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count © Digital Integrated Circuits2nd Sequential Circuits 4-to-1 tree based column decoder BL 0 BL 1 BL 2 BL 3 A0 A0 A1 A1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches © Digital Integrated Circuits2nd Sequential Circuits Sense Amplifiers Idea: Use Sense Amplifer small transition s.a. input © Digital Integrated Circuits2nd output Sequential Circuits Differential Sense Amplifier V DD M3 M4 y M1 bit SE M2 Out bit M5 Directly applicable to SRAMs © Digital Integrated Circuits2nd Sequential Circuits DRAM Timing © Digital Integrated Circuits2nd Sequential Circuits
