Download Chapter # 4

Memories
• Memories store large amounts of digital data
• Each bit represented by a single storage cell
• Major Categories
• Static RAM (SRAM)
• Dynamic RAM (DRAM)
• Mask-programmed ROM
• Erasable, Programmable ROM (EPROM)
• Electrically Erasable ROM (EEROM)
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EE 1210 - Logic System Design
Memory-1
Memory Bit Cells
write
Static RAM
bitIn
D
Q
en
Each bit is stored
in a D latch
bitOut
bitOut
bitIn
write
read
write
Dynamic RAM
bitOut Each bit is stored
in a capacitor
bitIn
bitIn bitOut
wr
rd
GND
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Note: In real implementations,
tri-state inverters are replaced
with single NMOS transistors
EE 1210 - Logic System Design
Memory-2
Multi-bit Registers
• A Register combines several
•
•
•
•
bit cells in one package
Common write signal
• Must write all bits at the
same time
Registers usually come in 4-,
8-, or 16-bit sizes
• Anything bigger takes too
many I/O pins
• A 1K-bit register requires
over 2000 pins
Asynchronous
• Uses D-latches enabled by
the write signal
Synchronous
• Uses D-FF’s
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bitIn[3]
write
Bitcell
bitOut[3]
bitIn bitOut
wr
bitIn[2]
Bitcell
bitOut[2]
bitIn bitOut
wr
bitIn[1]
Bitcell
bitOut[1]
bitIn bitOut
wr
bitIn[0]
Bitcell
bitOut[0]
bitIn bitOut
wr
EE 1210 - Logic System Design
Memory-3
Addressable Memories
•
•
Registers have two
drawbacks
1. In order to write one bit,
10-bit address
you have to write them all
(210 = 1024)
2. Large memories require
millions of pins
Assign a number (address)
to each bit cell
Write signal
• Input the address to
controls whether
reading or writing
read/write
• Access one bit at a time
(for read or write)
1 bit of data
read/written at
a time
1024-bit Memory
Address
[9..0]
DataOut
DataIn
Write
No clock: Data may be
read/written at any time
Clock: Inputs are looked at
on rising edge of clock
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EE 1210 - Logic System Design
Memory-4
Addressing
N=2n Data bits
O0
sel0
n-to-2n
Decoder
write
en
O1
ON
...
Address
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sel1
selN
DataIn
Bitcell
bitIn bitOut
wr
Bitcell
bitIn bitOut
wr
I0
2n-to-1
Mux
I1
Z
Bitcell
bitIn bitOut
wr
DataOut
IN
...
Address
n Address inputs
EE 1210 - Logic System Design
Memory-5
Selectable Bit Cells
To replace the output multiplexor with a bus, we must add
logic to turn on the output of a bit cell only when selected
Add a select input:
Bitcell activated only
when selected
From common
DataIn Line
write
sel
Bitcell

bitIn bitOut
sel wr
From Individual
Select Line
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Bitcell
bitIn bitOut
wr
bitIn
bitOut
To common
DataOut Line
(Tri-state)
From Common
Write Line
EE 1210 - Logic System Design
Memory-6
Memory with Selectable Bit Cells
N=2n Data bits
O0
sel0
n-to-2n
Decoder
memSelect en
Memory
select – if
memory is
not
selected,
DataOut is
tri-stated
O1
sel1
Bitcell

bitIn bitOut
sel wr
Bitcell

bitIn bitOut
sel wr
This is a tri-state  bus
- Only one bit cell is
driving it at any time
2n-bit Memory
Address
[n-1..0]
ON
...
Address
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selN
DataIn
Bitcell

bitIn bitOut
sel wr
DataOut
DataIn
Write
memSelect
DataOut 
write
EE 1210 - Logic System Design
Memory-7
Bi-directional Bit Cells
We’ll never be reading and writing at the same time – why not combine
the bitIn and bitOut lines…
The bitOut line is already
tri-state – it can be an
input or an output!
write
sel
Make sure that the bit line
is not driven when writing
Bitcell
bit 
sel wr
From Individual
Select Line
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Bitcell
bitIn bitOut
wr
bit 
To common
Data In/Out Line
(Tri-state)
From Common
Write Line
EE 1210 - Logic System Design
Memory-8
Memory with Bi-directional Data Line
N=2n Data bits
O0
sel0
n-to-2n
Decoder
memSelect en
O1
ON
...
Address
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sel1
selN
Bitcell
bit 
sel wr
2n-bit Memory
Address
[n-1..0]
Bitcell
bit 
sel wr
Bitcell
bit 
sel wr
write
Data
Write
memSelect
Data 
Write asserted: Input
Otherwise: Output
EE 1210 - Logic System Design
Memory-9
Memory with Multi-bit Words (4-bit word example)
O0
sel0
memSelect
n-to-2n
Decoder
en
O1 sel1
ON
...
Address
selN
Bitcell

bit
sel wr
Bitcell

bit
sel wr
Bitcell

bit
sel wr
write
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Bitcell

bit
sel wr
Bitcell

bit
sel wr
Bitcell

bit
sel wr
Data3 
Bitcell

bit
sel wr
Bitcell

bit
sel wr
Bitcell

bit
sel wr
Data2 
Bitcell

bit
sel wr
2nxW-bit Memory
Address
[n-1..0]
Bitcell

bit
sel wr
Write
memSelect
Repeat bit columns
for wider memories:
- Sel common for
each row
- Write common for
all bits
- Data common for
each column
Bitcell

bit
sel wr
Data1 
Data
[W-1..0]
Data0 
W Bits Wide
EE 1210 - Logic System Design
Memory-10
Static Memories
• Real SRAMs come in a variety of sizes, but are
based on the same basic principles
• Address input specifies where to read/write
• Data input/output contains data to read or write
• WE* (write enable): 1 for reads, 0 for writes
• OE* (output enable): 0 enables the output drivers
• CS* (chip select): 0 to select the chip (enable it)
A0-A10
Bitwide
16K x 1-bit: 20 pins
D0-D7
OE*
6116P-4
CS*
SRAM
WE*
Bytewide
2K x 8-bit: 24 pins
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EE 1210 - Logic System Design
A0-A13
OE*
CS*
WE*
D0
6167
SRAM
Memory-11
Bitwide vs. Bytewide
• Bytewide chips provide a complete byte at a time
• Perfect for microcontroller systems
• Bitwide chips provide only one bit at a time
• We usually need a whole byte (or more)
• Requires putting eight or more chips together
• Common addressing for all chips
• Each chip provides a single bit
• Example: 32-bit wide memory needs 32 chips
• Bitwide chips make sense only when we’re going to
have to use a lot of chips anyway (i.e. large systems)
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EE 1210 - Logic System Design
Memory-12
6264A Read Cycle Timing Diagram
tRC
tAA
Address Valid
A00-A12
tCO1
tLZ1
CS1*
tHZ1
OE*
tOH
tOE
D0D7
If OE* is tied
low, then use
tCO1 and tLZ1
tOLZ
Data Valid
Parameter
tRC
Read Cycle time
tAA
Address Access time
tC01 CS1 to data valid
tLZ1 CS1 to data bus driven
tOLZ Output enable to data bus driven
tOE
Output enable to data valid
tOH Output hold after address change
tHZ1 CS1 unasserted to data Hi-Z
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tOHZ
Min
120ns
Max
120ns
120ns
10ns
5ns
60ns
10ns
0ns
EE 1210 - Logic System Design
40ns
Memory-13
Dynamic RAM Bit Cell
sel
read
write
bitIn
bit
bitOut
GND
GND
bitIn bitOut
wr
rd
sel bit
Replace Tri-state inverter with a
single nMOS transistor.
Use bi-directional bit line.
Reading: Don’t drive bit line; select bit cell.
Writing: Externally drive bit line (hi/lo); select bit cell.
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EE 1210 - Logic System Design
Memory-14
Destructive Read
• A memory cell is read by discharging the capacitor
• Only a small voltage change
• Destroys the value held in the cell!
• A Sense-Amp senses the small voltage changes and
amplifies them
• Once amplified, the value is written back to the memory cell
bit line (connected to all bits in column)
rowsel
sel
bit
write or writeback
GND
bitcell
SA
bit 
write’
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EE 1210 - Logic System Design
Memory-15
16-bit DRAM Organization
• DRAMs are organized as
square arrays
• ½ address bits for row, ½
for column
• In this 16-bit memory: 2
bits for row, 2 for col
• Example: Read location 6
(0110)
• Row = 01, Col = 10
Row Enable 0
Row Enable 1
Row Enable 2
Row Enable 3
• The row is selected first,
reading all columns in row
• All bits in row are written
back
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ColSel 3
ColSel 2
ColSel 1
ColSel 0
Sense Amps
• The column is then
selected at the bottom
EE 1210 - Logic System Design
Memory-16
Refresh
• DRAM loses its charge in a
Row Enable 0
few milliseconds
• Have to re-write every
20ms or so
Row Enable 1
• Reading every bit will do
Row Enable 2
Row Enable 3
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ColSel 3
ColSel 2
ColSel 1
ColSel 0
Sense Amps
(writeback will refresh)
• This means 64M reads
every 20ms for a 64Mb
DRAM
• Solution:
• Reading just one bit in a
row causes all to be
refreshed!
• Only sqrt(64M) = 8K
reads per 20ms
EE 1210 - Logic System Design
Memory-17
DRAM Pinout
• A 64M x 1 DRAM needs:
• 26 Address Pins,1 Data Pin,CS*,R/W*,OE,Vdd,
GND
• 26 out of 32 pins are just for the address!
• Break the address up into two parts
• Row and Column
• Load in the Row first, and latch it
• Load in the Column second
• Use RAS* and CAS* to indicate each half of the
address
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EE 1210 - Logic System Design
Memory-18
DRAM timing
tRC
Address
Row
Col
RAS*
CAS*
Data
Data
tRAC
1. Place Row address on bus, Assert RAS*
2. Place Col address on bus, Assert CAS*
3. Wait for data to become valid (tRAC), Read Data
4. Wait for writeback to complete (tRC), start next cycle
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EE 1210 - Logic System Design
Memory-19
Memory Type Comparisons
SRAM
DRAM
ROM
EEROM
Fastest
Slow (15ns min
Varies
Slow
(3ns min access
time)
access time)
Access modes
speed up (DDR
SDRAM, etc.)
Expensive
Cheapest
Cheap
Cheapest
Volatility Erased on
Power off
Erased on
Power off
Indestructible
Non-volatile
(may have
limits)
Uses
Large
memories for
computers
Program
memory for
specialpurpose
systems
Any data that
needs to
persist after
power off
Speed
Price
1. High-speed
memory
2. Small
memories
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(read – 100ns)
(write – 4700ns)
EE 1210 - Logic System Design
Memory-20