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CS 2204 Fall 2007 Experiment 2 Lab 5 Experiment 2 Lab 5 Outline Presentation General Design Rules General Design Rules Semiconductor technology overview A Brief Look at Semiconductor Technology • Gate Features • Transistor-Transistor Logic (TTL) overview • Complementary Metal Oxide Semiconductor (CMOS) overview Individual work Experiment 2 Develop a 1-bit Adder (Full Adder) of the Ppm term project New handout General Design Rules CS 2204 Fall 2007 Experiment 2 Lab 5 Page 2 Presentation General Design Rules How would you approach Design • System design Pressure-filled tasks ? • If you are in control of the task, you have a chance to complete it successfully on time ► If the task is in control, the chances are slim ! Useful for this course, until graduation and after Use them for exams, projects, homework, etc. CS 2204 Fall 2007 Experiment 2 Lab 5 Page 3 Goal : Be in control of the pressure-filled task Rule 1 : You have enough pressure in the beginning, do not increase it further Do not rush Think Help yourself Prepare a mental/written plan to start and complete the task which uses the remaining rules If it was an exam : you would not rush to solve the first question ! • You would read all the questions and decide solving from the easiest towards the most difficult CS 2204 Fall 2007 Experiment 2 Lab 5 Page 4 Goal : Be in control of the pressure-filled task Rule 2 : Keep your task simple in the beginning Deal with simple concepts in the beginning Give yourself a chance to like the task in case you are not motivated enough Ask yourself : • Am I familiar with the system I will design ? • Am I familiar with the design process ? CS 2204 Fall 2007 Experiment 2 Lab 5 Page 5 Goal : Be in control of the pressure-filled task Rule 2 : Keep your task simple in the beginning If no to either one, do all or some of the following : Investigate similar systems and design processes, i.e. a background search and use it if allowed • If it was an exam, you would look at your notes, homework, handouts and books to have an idea about the question Follow a top-down (block-based) design to deal with simple concepts in the beginning (blocks and their input/output relationship) If possible, design a representative piece of the system you will design • Design a 1-bit 2-to1 MUX and then gradually expand it to the final goal of a 16-bit 2-to-1 MUX • Design a 2-entry digital lock (press two keys) first and then gradually expand it to the final goal of a 6-entry digital lock (press 6 keys) CS 2204 Fall 2007 Experiment 2 Lab 5 Page 6 Goal : Be in control of the pressure-filled task Rule 3 : Base your decisions on design goals : speed, cost, power, reliability, size, weight, etc. Such as selecting among alternative components Be consistent Do not make decisions that look arbitrary Use these even when you partition blocks CS 2204 Fall 2007 Experiment 2 Lab 5 Page 7 Goal : Be in control of the pressure-filled task Rule 4 : When you start the design, do not go for the best design possible Get a system that works first then, optimize it with respect to the design goals. Thus, relax Rule 3 in the beginning • Use this rule especially if you are a new designer CS 2204 Fall 2007 Experiment 2 Lab 5 Page 8 Goal : Be in control of the pressure-filled task Rule 5 : Your design must be such that one can upgrade it in the future Otherwise, to upgrade it would be impossible and so the system has to be redesigned from scratch ! The Ppm project is designed so that one can have different versions of it • Human vs. machine now • Human vs. human later • Machine vs. machine later A computer is designed so that in the future one can upgrade • The memory to large sizes • Place a new version of the microprocessor CS 2204 Fall 2007 Experiment 2 Lab 5 Page 9 Goal : Be in control of the pressure-filled task Rule 6 : Design or at least consider more than one layer at a time after you become familiar with the system you are designing and the design process. This is not top-down design but middle-out ! This is possible if you are an experienced designer CS 2204 Fall 2007 Experiment 2 Lab 5 Page 10 Goal : Be in control of the pressure-filled task Rule 7 : If you are stuck and does not know what to do, especially does not know what to do next, STOP ! Move up to higher layers and see where you are You will see what you have missed You will see which (sub)block is next CS 2204 Fall 2007 Experiment 2 Lab 5 Page 11 Goal : Be in control of the pressure-filled task Rule 8 : If you cannot explain something, cannot explain why it happens as it happens, “zoom in” Move to the lower layers and focus on few (sub)blocks that affect the situation CS 2204 Fall 2007 Experiment 2 Lab 5 Page 12 Xilinx Project Development Steps Today’s work Develop the schematic Design the schematic Place the components and wires Do integrity tests Test the schematic via logic simulations What are these components ? Do a Xilinx IMPLEMENTATION It maps the components to the CLBs of the chip Do timing simulations to test the schematic It generates the bit file Download the bit file to the FPGA and test the design on the board It programs the chip CS 2204 Fall 2007 Experiment 2 Lab 5 Page 13 Developing a digital product A new chip Which gates & FFs and how many is determined by Available components of the technology chosen Besides the major operations and speed, cost, power, etc. product goals of the digital product FPGAs are used to test the new chip A new PCB Which chips and how many is determined by Available chips of the technology chosen Besides the major operations and speed, cost, power, etc. product goals of the digital product CS 2204 Fall 2007 Experiment 2 Lab 5 Page 14 Gate Features Speed, Cost, Power, Size,… Determined by switch features Speed, cost, power, size,… • Depend on the technology chosen ► CMOS, BiCMOS, TTL, ECL They have their own subfamilies CMOS : HC, HCT, AC, ACT, FCT,… TTL : H, L, S, LS, AS,… CS 2204 Fall 2007 Experiment 2 Lab 5 Page 15 Gate Cost How much a gate costs : pennies or less today Determined by The technology The number of inputs The number of gates on the chip Why are Chips Cheap Today ? Silicon is the most common semiconductor • Sea sand has silicon CS 2204 Fall 2007 Experiment 2 Lab 5 Page 16 Gate Power Consumption Amount of electrical power consumed by a single gate Micro Watts or less today Determined by The technology The number of inputs The higher the power consumption, the higher heat generated Indirectly determines the density of the chip The number of transistors on the chip CS 2204 Fall 2007 Experiment 2 Lab 5 Page 17 Gate Size How large a gate is : in terms of microns on a side today Determined by Transistor size • A function of the process : 0.065 micron today • Reason for Moore’s Law • It will be 0.045 micron soon Technology The number of inputs • The more inputs, the larger the gate is CS 2204 Fall 2007 Experiment 2 Lab 5 Page 18 Fan-in The number of inputs a gate has This is purely electrical Determined by the technology a b c y CS 2204 Fall 2007 The fan-in is three Experiment 2 Lab 5 Page 19 Fan-out The number of gate inputs that can be connected to a gate output This is purely electrical Determined by the technology If the fan-out is exceeded The output can be physically damaged The output value may not be electrically “strong” to be interpreted as 1 or 0 CS 2204 Fall 2007 Experiment 2 Lab 5 Page 20 Fan-out In order to increase the fan-out buffers are used Regular buffers (not input nor output buffers) are used to increase the fan-out A buffer is an electronic circuit that is used to electrically “drive” large currents, hence many inputs ► It can also have circuits to filter noise and strengthen the electrical signal CS 2204 Fall 2007 Experiment 2 Lab 5 Page 21 Fan-out Increasing the fan-out a b y c Use a buffer ! But, the input to output delay is increased ..... CS 2204 Fall 2007 ..... Experiment 2 Lab 5 Page 22 Technology of components/chips Transistor-Transistor Logic (TTL) Uses bipolar transistors Consists of two sets of families Commercial : 74xxxx • Cheaper • Widely available Military : 54xxxx • Manufactured for more stringent applications • Expensive CS 2204 Fall 2007 Experiment 2 Lab 5 Page 23 Transistor-Transistor Logic (TTL) Commercial TTL families, each with a different combination of speed, power, cost,.. 74 (Standard) 74L (Low-power) 74S (Schottky) We will use it 74LS (Low-power Schottky) from time to time 74H (High speed) 74AS (Advanced Schottky) 74ALS (Advanced Low-power Schottky) 74F (Fast) CS 2204 Fall 2007 Experiment 2 Lab 5 Page 24 Transistor-Transistor Logic (TTL) Unused gate input 1) It can be left unconnected (floating) a b y Implemented by an available 3input AND gate a b y From documentation point of it is confusing If the designer leaves the company and a new engineer works on it can get confused CS 2204 Fall 2007 Experiment 2 Lab 5 Page 25 Transistor-Transistor Logic (TTL) Unused gate input 2) It can be tied to a used input a y b An available 3-input AND gate used to implement a 2-input AND gate The fan-out of the b signal is increased CS 2204 Fall 2007 Experiment 2 Lab 5 Page 26 Transistor-Transistor Logic (TTL) Unused gate input 3) It can be connected to 1 or 0 depending on the gate type, via a pull-up resistor or pull-down resistor a a b b y y Pull-down resistor Pull-up resistor 0v +5 v CS 2204 Fall 2007 Experiment 2 Lab 5 Page 27 Transistor-Transistor Logic (TTL) Gate outputs Totem-pole outputs Do not short circuit totem-pole gate outputs 2-input NAND gate implementation From ON Semiconductor LS TTL Data Manual CS 2204 Fall 2007 Experiment 2 Lab 5 Page 28 Transistor-Transistor Logic (TTL) Gate outputs Tri-state outputs The output has three values ! • 1, 0 and Hi-Z ≡ High-impedance ≡ Floating ≡ Static voltage • There is an extra control input, Enable, to enable/disable output ► If disabled, the output value is Hi-Z (high-impedance) a y b Enable Enable y 0 Hi-Z 1 ab Operation table Tri-state symbol CS 2204 Fall 2007 Experiment 2 Lab 5 Page 29 Transistor-Transistor Logic (TTL) Gate outputs Tri-state outputs A tri-state gate can be envisioned as a totem-pole gate with a switch at the output y a Output y has three values a y b b Enable Enable Totem-pole gate Switch closed 0 CS 2204 Fall 2007 Experiment 2 Lab 5 Switch open 1 Hi-Z Page 30 Transistor-Transistor Logic (TTL) Gate output Tri-state outputs Outputs can be short circuited if only one gate is enabled at a time Enable1 You can short circuit tri-state gate outputs Tri-state outputs are often used to implement buses A bus line Enable2 CS 2204 Fall 2007 Experiment 2 Lab 5 Page 31 Transistor-Transistor Logic (TTL) Gate output Open-collector An external pull-up resistor is needed a y b Pull-up resistor Open collector symbol Open-collector outputs are often used To drive displays and lights To implement buses +5 v CS 2204 Fall 2007 Experiment 2 Lab 5 Page 32 Transistor-Transistor Logic (TTL) Gate output Open-collector Gate outputs can be short circuited A bus line You can short circuit open-collector gate outputs Open-collector outputs are often short circuited to implement buses +5 v CS 2204 Fall 2007 +5 v Experiment 2 Lab 5 Page 33 Technology of components/chips Complementary Metal Oxide Semiconductor (CMOS) Uses unipolar transistors Slower than Bipolar transistors Consume less power than Bipolar transistors CMOS chips consume very little power Not straightforward to connect to TTL chips Better Fan-out than TTL chips CS 2204 Fall 2007 Experiment 2 Lab 5 Page 34 Complementary Metal Oxide Semiconductor (CMOS) Commercial CMOS families, each with a different combination of speed, power, cost 4000 (Oldest) 74HC (High speed CMOS) 74HCT (High speed CMOS, TTL Compatible) 74AC (Advanced CMOS) 74ACT (Advanced CMOS, TTL Compatible) 74FCT (Fast CMOS, TTL Compatible) 74FCT-T (Fast CMOS, TTL Compatible with TTL VOH) CS 2204 Fall 2007 Experiment 2 Lab 5 Page 35 Complementary Metal Oxide Semiconductor (CMOS) CMOS chips are sensitive to static electricity One should not touch them Unless properly grounded • A wire strapped around the wrist is connected to the ground • The ground has 0v CS 2204 Fall 2007 Experiment 2 Lab 5 Page 36 Complementary Metal Oxide Semiconductor (CMOS) Unused gate input 1) Do not leave it unconnected (floating) a y b ? a y b The gate will not work properly Xilinx does not allow this option ! A No Driver warning is given by the Project Manager CS 2204 Fall 2007 Experiment 2 Lab 5 Page 37 Complementary Metal Oxide Semiconductor (CMOS) Unused gate input 2) It can be tied to a used input a y b An available 3-input AND gate used to implement a 2-input AND gate The fan-out of the b signal is increased CS 2204 Fall 2007 Experiment 2 Lab 5 Page 38 Complementary Metal Oxide Semiconductor (CMOS) Unused gate input 3) It can be connected to 1 or 0 depending on the gate type, via a pull-up resistor or pull-down resistor a a b b y y Pull-down resistor Pull-up resistor 0v +5 v CS 2204 Fall 2007 Experiment 2 Lab 5 Page 39 Complementary Metal Oxide Semiconductor (CMOS) Gate output Regular Do not short circuit regular gate outputs Xilinx warning message from the Project Manager : Multiple drivers on output y y CS 2204 Fall 2007 Experiment 2 Lab 5 Page 40 Complementary Metal Oxide Semiconductor (CMOS) Gate output Tri-state outputs The output has three values ! • 1, 0 and Hi-Z ≡ High-impedance ≡ Floating ≡ Static voltage • There is an extra control input, Enable, to enable/disable output ► If disabled, the output value is Hi-Z (high-impedance) a y b Enable Enable y 0 Hi-Z 1 ab Operation table Tri-state symbol CS 2204 Fall 2007 Experiment 2 Lab 5 Page 41 Complementary Metal Oxide Semiconductor (CMOS) Gate output Tri-state outputs A tri-state gate can be envisioned as a totem-pole gate with a switch at the output y a Output y has three values a y b b Enable Enable Regular gate Switch closed 0 CS 2204 Fall 2007 Experiment 2 Lab 5 Switch open 1 Hi-Z Page 42 Complementary Metal Oxide Semiconductor (CMOS) Gate output : Tri-state gate outputs can be short circuited if only one gate is enabled at a time Enable1 You can short circuit tri-state gate outputs y Tri-state outputs are often used to implement buses A bus line Enable2 CS 2204 Fall 2007 Experiment 2 Lab 5 Page 43 Complementary Metal Oxide Semiconductor (CMOS) Gate output : Open-drain An external pull-up resistor is needed a y b Pull-up resistor Open drain symbol Open-drain outputs are often used To drive displays and lights To implement buses +5 v CS 2204 Fall 2007 Experiment 2 Lab 5 Page 44 Complementary Metal Oxide Semiconductor (CMOS) Gate output : Open-drain Gate outputs can be short circuited A bus line +5 v You can short circuit open-drain gate outputs +5 v CS 2204 Fall 2007 Experiment 2 Lab 5 Page 45 Digital Engineering Terminology U1 U2 Must be U2 has no Load U2 output is not used corrected a Must be corrected U4 input has no driver U4 input is not connected to an output. Its input value is Hi-Z (High-Impedance) as there is infinite impedance (resistance) into the U4 input so no current can flow in U4 b y a c U3 CS 2204 Fall 2007 Must be corrected Multiple drivers on output y U3 and U4 outputs are short circuited Experiment 2 Lab 5 Page 46 Q/A Do not leave the lab before your partners finish ► Help your partners complete today’s project Read slides on the Ppm, Project Manager, Schematic design and other related topics Continue reading the Term Project handout Think about the machine player strategy CS 2204 Fall 2007 Experiment 2 Lab 5 Page 47 Today’s Individual Xilinx Work We will continue to study (analyze) the term project We will use our knowledge of 1-bit ADDers to modify a portion of a term project to develop a 1-bit ADDer in the Points Calculation Block (Block 5) The 1-bit ADDer expression is the same as the one obtained in class • We will replace a 1-bit Xilinx ADDer with our own circuits Help your partners complete today’s project We will continue reading the Term Project handout Relate each term project (sub)block in the Term Project handout to the Ppm schematic Study Ppm (sub)blocks by performing simulations Read slides at the end to learn more about the term project, Project Manager, schematic design and other related topics CS 2204 Fall 2007 Experiment 2 Lab 5 Page 48 Today’s Individual Xilinx Lab Work 1. Copy the termproject folder and paste it in the cs2204 folder as the exp2 folder We will experiment with the Ppm schematics 2. Open the Ppm project in exp2 3. Look at the six Ppm schematics If you copy a project completely as we did and then open its schematics, the schematics will be all Non-Project Therefore, close all these schematics and close the schematics window Then, open the schematics one by one on the Project Manager window, by double clicking on the schematic name on the upper left side 4. Place your team info on the schematics on schematic 1 : ppm1.sch CS 2204 Fall 2007 Experiment 2 Lab 5 Page 49 Today’s Individual Xilinx Lab Work 5. Save schematic 1 6. Switch to schematic 5 7. Zoom into the upper right area, containing the Encoded Adjacency Subsubblock 8. There is a Xilinx macro (a Xilinx Design Block, XDB) A 4-bit ADDer, ADD4, It adds two 4-bit numbers This Xilinx 4-bit ADDer is used as a 1-bit ADDer A Full Adder See ppm5.sch on the next slide CS 2204 Fall 2007 Experiment 2 Lab 5 Page 50 Today’s Individual Xilinx Lab Work Ppm Schematic 5 Xilinx 4-bit ADDer CS 2204 Fall 2007 Experiment 2 Lab 5 Page 51 Today’s Individual Xilinx Lab Work 9. Analyze the ADDer to determine how it is used as a 1-bit ADDer See the correspondence between the Handout 5 circuit inputs and outputs and Xilinx Adder inputs and outputs Determine which input is “a”, which input is “b” and which input is “c” Determine which output is “cout” and which output is the “sum” output ? Do a Hierarchy Push and see that it is implemented by Xilinx differently from the one discussed in class It does not have four cascaded Full Adders ! CS 2204 Fall 2007 Experiment 2 Lab 5 Page 52 Today’s Individual Xilinx Lab Work 9. Analyze the ADDer to determine how it is used as a 1-bit ADDer Observe the internal structure of the Xilinx 4bit ADDer and compare it with the two gate networks in Handout 5 The S0 output is Sum(a, b, c) in Handout 5 The S1 output is cout(a, b, c) in Handout 5 S0 = Sum(a, b, c) = a b c + a b c + a b c + abc = a + b + c S1 = cout(a, b, c) = bc + ab + ac CS 2204 Fall 2007 Experiment 2 Lab 5 Page 53 Today’s Individual Xilinx Lab Work 9. Analyze the ADDer to determine how it is used as a 1-bit ADDer Close the schematic of the internal circuit of the Xilinx 4-bit ADDer by means of a Hierarchy Pop 10. Perform functional simulations on this Xilinx 4-bit ADDer to verify it is a 1-bit ADDer Use the truth table in Handout 5 CS 2204 Fall 2007 Experiment 2 Lab 5 Page 54 Today’s Individual Xilinx Lab Work 11. Search for the inputs and outputs of the ADDer by clicking on the Query window button on top of the schematic sheet In the Signal/Bus mode of the SC Query/Find window that will pop up Determine which components generate the inputs UNENCNSD0, UNENCNSD1, UNENCNSD2 Determine which components use outputs NSD0 and NSD1 12. Delete the Xilinx 4-bit ADDer in schematic 5 Do not delete the wires Save schematic 5, ppm5.sch See modified ppm5.sch on the next slide CS 2204 Fall 2007 Experiment 2 Lab 5 Page 55 Today’s Individual Xilinx Lab Work Ppm Schematic 5 CS 2204 Fall 2007 Xilinx 4-bit ADDer deleted Experiment 2 Lab 5 Page 56 Today’s Individual Xilinx Lab Work 13. Scroll down to the mid area of schematic 5 to have a large working space 14. Draw the schematic of the 1-bit ADDer by using Handout 5 on the left and right side of the mid area in schematic 5 You will implement the sum and cout outputs by using 2-level AND-OR gate networks in Handout 5 You will use the Symbols toolbox button on the leftmost side (or F3) to get the component list You will use the Draw wires button on the leftmost side (or F4) to draw wires To rotate components right press ctrl-r To rotate components left, press ctrl-l Note, wires cannot be rotated But, by pulling from one end of a wire, it can be rotated ! Label the wires (inputs and outputs) based on your analysis in part (9) See modified ppm5.sch on next slide CS 2204 Fall 2007 Experiment 2 Lab 5 Page 57 Today’s Individual Xilinx Lab Work The modified ppm5.sch sum cout 1-bit ADDer CS 2204 Fall 2007 Experiment 2 Lab 5 Page 58 Today’s Individual Xilinx Lab Work 14. Draw the schematic of the 1-bit ADDer by using Handout 5 In the Instance mode of the SC Query/Find window that will pop up Determine that there is no component labeled U267 and above Label the components starting at U267 The last component label is U278 Save schematic 5, ppm5.sch See modified ppm5.sch on next two slides First, the sum circuit Then, cout circuit CS 2204 Fall 2007 Experiment 2 Lab 5 Page 59 Today’s Individual Xilinx Lab Work The sum (NSD0) circuit in ppm5.sch CS 2204 Fall 2007 Experiment 2 Lab 5 Page 60 Today’s Individual Xilinx Lab Work The cout (NSD1) circuit in ppm5.sch CS 2204 Fall 2007 Experiment 2 Lab 5 Page 61 Today’s Individual Xilinx Lab Work 15. Perform an Integrity Test to check for errors Integrity tests do not catch all the errors That is why after the Integrity tests we have to perform • Functional simulations • Xilinx IMPLEMENTATIONs • Timing simulations 16. Perform functional simulations on this 1-bit ADDer in schematic 5 to verify that it is working Use the truth table in Handout 5 Make sure the circuit is beautified and the schematic is saved again CS 2204 Fall 2007 Experiment 2 Lab 5 Page 62 Today’s Individual Xilinx Lab Work 17. Do a Xilinx IMPLEMENTATION Make sure there are no errors Make sure the IMPLEMENTATION options are changed so that a better IMPLEMENTATION is done Read the Implementation Log File to confirm that The number of warnings 25 • These warning are OK, we can continue • Note that there are 25 warnings not 24 as it is the case with the original term project since a wire in Block 5 is not used WARNING:NgdBuild:454 - logical net '$Net00202_' has no load • This wire is the wire that connected the unused data inputs of the Xilinx 4-bit ADDer to GND in Block 5 CS 2204 Fall 2007 Experiment 2 Lab 5 Page 63 Today’s Individual Xilinx Lab Work 17. Do a Xilinx IMPLEMENTATION Read the Implementation Log File to see that The FPGA chip utilization is 97% • The Xilinx IMPLEMENTATION maps the design to 190 to 191 CLBs after an IMPLEMENTATION, a feature peculiar to FPGA testing The conversion of the schematic to the bit file is “randomized” to have a better mapping of the logic to CLBs, but it leads to this situation That is why we fabricate the prototype chip before we mass produce it to test the design one more time to make sure the design is correct CS 2204 Fall 2007 Experiment 2 Lab 5 Page 64 Today’s Individual Xilinx Lab Work 17. Do a Xilinx IMPLEMENTATION The Project Manager window looks like this after the IMPLEMENTATION is completed successfully : Make sure the options for IMPLEMENTATION are “High Effort” “50” and “5” The checkmark for IMPLEMENTATION can be delayed a few minutes sometimes CS 2204 Fall 2007 Experiment 2 Lab 5 Page 65 Today’s Individual Xilinx Lab Work 18. Download the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly If it does not work, inspect your circuit in Block 5 and correct your circuit CS 2204 Fall 2007 Experiment 2 Lab 5 Page 66 Today’s Individual Xilinx Lab Work 19. Help your partners complete today’s project 20. Continue reading the Term Project handout Relate each term project (sub)block in the Term Project handout to the Ppm schematic Study Ppm (sub)blocks by performing simulations Play the other two versions of the term project to refresh your memory • • Ppm human vs. human : ppmhvsh Ppm machine vs. machine : ppmmvsm 21. Read slides at the end to learn more about the term project, Project Manager, schematic design and other related topics CS 2204 Fall 2007 Experiment 2 Lab 5 Page 67 Understand Critical Wires RD : 4 bits The random digit P1RD : 4 bits Next random digit P2RD : 4 bits The random digit after next random digit DISP : 16 bits They represent the four position displays In Hex DISP15-DISP12 : the leftmost position display, PD3 DISP11-DISP8 : position display PD2, etc TDISP : 16 bits Next display bits after the current random digit is played SELTPD : 4 bits Selects between DISP and TDISP to add the current or next random digit If it is 0, it selects DISP, otherwise TDISP TADDDISP : 16 bits The result of selection between DISP and TDISP CS 2204 Fall 2007 Experiment 2 Lab 5 Page 68 Understand Critical Wires NPDISP : 16 bits TADDDISP digits plus RD NDISP : 16 bits New DISP bits In Hex BRWD : 4 bits Basic reward In Hex The digit played and also minimum points earned Brwdeqz : 1 bit BRWD is zero when it is 1 PDPRD : 4 bits Display overflow bits after addition Pdprd : 1 bit The display overflow bit of the position played Selplyr : 1 bit The current player If it is 0, it is the human player, otherwise, it is the machine player CS 2204 Fall 2007 Experiment 2 Lab 5 Page 69 Understand Critical Wires P1SEL : 4 bits The position played by the human player P2SEL : 4 bits The position played by the machine player PSEL : 4 bits Position Select bits of current player ENCPSEL : 2 bits The number of the position played EQ : 4 bits The equality of the four displays to the digit played NSD : 2 bits The number of similar digits, i.e. the adjacency information of the position played RWD : 8 bits The reward points calculated based on adjacencies In Unsigned Binary CS 2204 Fall 2007 Experiment 2 Lab 5 Page 70 Understand Critical Wires P1PT : 8 bits Player 1 points In Hex P2PT : 8 bits Player 2 points In Hex PT : 8 bits The points of the current player In Hex NPT : 8 bits New player points for the current player In Hex Ptovf : 1 bit The points overflow if it is 1, the new player points is above (255)10 CS 2204 Fall 2007 Experiment 2 Lab 5 Page 71 Understand Critical Wires P1add : 1 bit Player 1 adds when it is 1 P2add : 1 bit Player 2 adds when it is 1 Add : 1 bit The current player adds when it is 1 P1skip : 1 bit Player 1 skips when it is 1 P2skip : 1 bit Player 2 skips when it is 1 P1played : 1 bit Player 1 played when it is 1 P2played : 1 bit Player 2 played when it is 1 CS 2204 Fall 2007 Experiment 2 Lab 5 Page 72 Understand Critical Wires Clear : 1 bit Clear FFs, registers, counters, etc. during reset in Block 2 and Block 4 so that it can play again Clearp2ffs : 1 bit Clears Player 2 FFs, counters and registers Shp1rds : 1 bit Shows next two digits to Player 1 in state 1 Add : 1 bit Shows that the current player has selected to add Stp1pt : 1 bit Store Player 1 points Stp2pt : 1 bit Store Player 2 points Grd : 1 bit Signals to generate a new random digit The random digit counter output is stored as P2RD while P2RD and P1RD are shifted to generate the new P1RD and RD Bpds : 1 bit Blink one or all displays slowly Bpdf : 1 bit Blocks a display fast after a display overflow CS 2204 Fall 2007 Experiment 2 Lab 5 Page 73 Understand Critical Wires Clff : 1 bit Clears FFs in Block 2 so that the next player can play if there is no overflow S1 : 1 bit State 1 where when it is 1, the Ppm is in state 1 P2sturn : 1 bit Signals that Player 2 has the turn It is 1 when the Ppm is in state 4 Sysclk : 1 bit System clock of the operation diagram at 6 Hz to the digit played P2clk : 1 bit The clock signal of Player 2 at 48 Hz Rdclk : 1 bit The random digit counter clock at 192 Hz CS 2204 Fall 2007 Experiment 2 Lab 5 Page 74 Project Manager Actions and Reminders Make sure there is a CS2204 folder Make sure there is an experiment folder for the current experiment You can check the folder the current project is in by selecting File -> Project Info Make sure the FPGA chip and its model are correct when a new Xilinx project is created You can check the FPGA chip and its model by selecting File -> Project Type… The selections must be as follows • The chip : Spartan • The model : S10PC84 • Speed : 3 CS 2204 Fall 2007 Experiment 2 Lab 5 Page 75 Project Manager Actions and Reminders If you copy a project completely and paste it as a new project, its schematic files cannot be worked on right away After you open the schematics, they are all Non-Project schematics Close all the schematics Close the schematics window Open the schematics one by one on the Project Manager window Double click on the schematic name on the upper left side for each schematic file CS 2204 Fall 2007 Experiment 2 Lab 5 Page 76 Project Manager Actions and Reminders When you do the first Xilinx IMPLEMENTATION or after clearing the implementation data, you need to change implementation options before clicking on “Run” in the Implement Design Window You can change the options by selecting Options… in the same window and then Increase the Place & Route Level to the Highest Effort on the “Options” window Click on the Edit Options… button for Implementation: in the Program Options area of the “Options” window Click on Place and Route on the “Spartan Implementation Options: Default” window Increase Router Options to 50 and 5 for both Routing Passes and Delay-Based Cleanup Passes CS 2204 Fall 2007 Experiment 2 Lab 5 Page 77 Project Manager Actions and Reminders After a successful IMPLEMENTATION The schematic files have a check mark next to them The Design Entry button will have a check mark The IMPLEMENTATION button has a check mark (after a delay of minutes sometimes) The PROGRAMMING button is highlighted If not, just click in anywhere in the Flow tab area of the Project Manager window, it will be highlighted If the IMPLEMENTATION is not successful due to errors, the IMPLEMENTATION button will have an “X” mark The error can be because of wrong chip selection or schematic design errors Correct them then ! CS 2204 Fall 2007 Experiment 2 Lab 5 Page 78 Project Manager Actions and Reminders After a Xilinx IMPLEMENTATION, read the Implementation Log File for errors, warnings and FPGA chip utilization You can read the Implementation Log File by selecting Reports -> Implementation Log File All No driver warnings must be corrected • No Driver means, the wire is not connected to any component output All Multiple drivers warnings must be corrected • Multiple Drivers means, a wire is connected to multiple component outputs Most No Load warnings can be ignored • Because, the software warns that a component output is not used, because you do not need the output • But, if a component output is needed, and not connected, then it is an error, the output must be connected to the input of a component CS 2204 Fall 2007 Experiment 2 Lab 5 Page 79 Project Manager Actions and Reminders After performing several Xilinx IMPLEMENTATIONs, clear the implementation data, by selecting Project -> Clear Implementation Data Back to back Xilinx IMPLEMENTATIONs use previous implementation data that is unchanged to save time Over time, this implementation data becomes corrupt and the bit file has errors • Correct designs do not perform correctly on the FPGA board Clearing the implementation data changes the implementation options to the default ones The schematic files will keep their check marks The Design Entry button will keep its check mark But, the IMPLEMENTATION button will have a question mark The PROGRAMMING button will not be highlighted The implementation options must be changed to the required ones again CS 2204 Fall 2007 Experiment 2 Lab 5 Page 80 Schematic Design Actions, Shortcuts & Reminders Place team info on schematics You can enter the team info by selecting File -> Table Setup… Place your name & a partner name on Line1: Place names of the other two partners on Line 2: On Line3: place CS2204 – Section A/B/C/D/E/F – Spring 2007 Press F2 to enter the Select & Drag Mode Only, in this mode components can be deleted, rotated, copied and pasted You can press ESC to enter the Select & Drag Mode Press F3 to get component library on screen VCC is logic 1 GND is logic 0 To quickly locate a component, enter the first few letters of the component in the bottom area of the SC Symbols window To locate XOR gates, just enter letter “X” and “O” CS 2204 Fall 2007 Experiment 2 Lab 5 Page 81 Schematic Design Actions, Shortcuts & Reminders Press F4 to draw wires Press F5 to draw buses Press F7 to search for wires and components To search for wires, select the Signal/Bus mode If the wire does not have a name, the software assigns one that starts with a “$” symbol and ends with a “_” symbol • Use the whole name to search for a wire To search for a component, select the Instance mode If a component does not have a name, the software assigns one that starts with “$I” symbols followed by a number • Use the whole name to search for the component Press F8 to start simulation quickly Press F10 to refresh the screen CS 2204 Fall 2007 Experiment 2 Lab 5 Page 82 Schematic Design Actions, Shortcuts & Reminders Press ctrl-c to copy a wire or a component selected When components are copied, their labels are not copied ! You can copy from a schematic that belongs to another project To open the schematic of another project, click on button in the upper left corner, then select the schematic file which will be in another folder Press ctrl-v to paste a wire or a component Press ctrl-r/ctrl-l to rotate components right/left Wires cannot be rotated ! You can see how a Xilinx macro is designed (the internal structure), do a Hierarchy Push, by selecting Hierarchy -> Hierarchy Push You can close the macro internal design screen, by selecting Hierarchy -> Hierarchy Pop CS 2204 Fall 2007 Experiment 2 Lab 5 Page 83 Schematic Design Actions, Shortcuts & Reminders Unless otherwise stated, use Xilinx macros instead of designing them to save time Use buffers to rename wires Do not use unnecessary input/output buffers Do not use unnecessary input/output pads If you copy and paste components, their labels are not copied and pasted by the software You will need to “source” the schematic file to copy and paste component labels as explained in the Advanced Xilinx and Digilent Features handout Xilinx does not have high density ROM memory components 16x1-bit and 32x1-bit They may not be used at all • If needed, its usage is described on page 9 of the Advanced Xilinx and Digilent Features handout CS 2204 Fall 2007 Experiment 2 Lab 5 Page 84 Schematic Design Actions, Shortcuts & Reminders Drawing buses by using Draw Buses button on the left side : Ppm buses are type None Individual wires of a bus must have names the same as the bus name The indices of individual wires start at 0 and are up to the number of bus wires minus 1 • Bus NPT has 8 wires : NPT7, NPT6, NPT5,…, NPT1, NPT0 If a component generates a bus, there is no need to draw the individual wires of the bus, unless a components needs those individual wires CS 2204 Fall 2007 Experiment 2 Lab 5 Page 85 Schematic Design Actions, Shortcuts & Reminders Beautify the schematic for documentation purposes Place components of different sub/blocks separate from each other to recognize them Write Comments, draw lines and rectangles and label sub/blocks to identify them on the schematic for documentation purposes • Use the Graphics Toolbox button on the left : Label components appropriately Wire names follow application and block partitioning naming requirements • Except for wires that are connected IBUFs, OBUFs, IPADs and OPADs Component names start with a U • Except if it is a BUF, IBUF, OBUF, IPAD or OPAD To label a component, right click on the component and select Symbol Properties… • Give the name in the Reference: section of the Symbol Properties window CS 2204 Fall 2007 Experiment 2 Lab 5 Page 86 Schematic Design Actions, Shortcuts & Reminders Beautify the schematic for documentation purposes Do not leave components unused Draw short wires and label them with the same name To label wires double click on the wire and enter the name in the Net Name: area of the pop up window Draw wires without unnecessary turn Draw wires without tangling Draw wires around components/labels/names Do not short circuit input lines Do not short circuit output lines Do not have labels/attributes/components overlap CS 2204 Fall 2007 Experiment 2 Lab 5 Page 87 Schematic Design Actions, Shortcuts & Reminders Perform integrity tests to catch simple errors You can do an integrity test of the current schematic sheet, by selecting Options -> Integrity Test for Current Sheet After the completion, a window may tell you to look at the Project Manager window to read about warnings detected, even if it says the test passed successfully • Look at the Project Manager window, you will see warnings in blue • If the last line has the Schematic Contents OK line, there is no need to correct anything CS 2204 Fall 2007 Experiment 2 Lab 5 Page 88 Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors Press F8 to start simulation quickly You will see the SC Probes window To select the input wires to be simulated, click on the Stimulator tool button of the SC Probes windows Then click on the input wires by precisely clicking on their names to select them • There will be a square gray box shown on the left side of the input wire name • Wires that have no name cannot be simulated, therefore, they must be given names for simulation • When selecting input bus wires, click on the bus wires in the increasing index order : ABUS0, ABUS1, ABUS2,… CS 2204 Fall 2007 Experiment 2 Lab 5 Page 89 Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors Press F8 to start simulation quickly You will see the SC Probes window : To select the output wires to be simulated, click on the Probe tool button of the SC Probes windows : Then click on the output wires by precisely clicking on their names to select them • There will be a square gray box shown on the left side of the output wire name • Wires that have no name cannot be simulated, therefore, they must be given names for simulation • When selecting output bus wires, click on the bus wires in the increasing index order : OBUS0, OBUS1, OBUS2,… CS 2204 Fall 2007 Experiment 2 Lab 5 Page 90 Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors Press F8 to start simulation quickly You will see the SC Probes window : To start the simulation, click on the Simulator button of the SC Probes window : Once you have the simulation window on the screen You will see the input wires listed and then the output wires on the left side of the Logic Simulator window CS 2204 Fall 2007 Experiment 2 Lab 5 Page 91 Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors Separate the input rows from the output rows by placing a blank row between the input and output wires sets Click on the top output wire Make selections Signal -> Empty Rows -> Insert Combine bus bits to reduce the number of rows Click on the top bus wire which has the lowest index (ABUS0) Press shift and simultaneously click on the highest order bus wire (ABUS7) to select all the wires of the bus • A turquoise rectangle covers the bus wires Right click on the turquoise rectangle and make the following selections Bus -> Combine CS 2204 Fall 2007 Experiment 2 Lab 5 Page 92 Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors In order to simulate the circuit, the input wires must be first given new names Click on the Select Stimulators button : • A keypad window will be shown Select an input wire by clicking on it (it will be covered by a turquoise rectangle) and then click on any letter key on the keypad, such as “q” • To the right of the input wire, the new name “q” is shown • To the right of “q”, the current value of the wire is shown ► If it is a single wire, the value is Hi-Z ◊ This has to be changed to have correct simulations ► If it is a bus, the value is shown as capital letter “Z” ◊ This has to be changed as well for correct simulations CS 2204 Fall 2007 Experiment 2 Lab 5 Page 93 Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors To change the values of wires on the simulator window If it is a single wire, the value is Hi-Z : • Just click on the Hi-Z line to make the value 0 ►The value is shown to the right of name “q” as 0 • Click on the 0 value line again to make the value 1 ►The value is shown to the right of name “q” as 1 If it is a bus, the value is shown as capital letter “Z” • Click on Logical States to give a value to the bus : ►The Stimulator State Selection window will be shown • Click on the bus name, such as ABUS • Enter an appropriate Hex value in the Bus State area, such as “FA” ► Appropriate means the Hex value must fit the width of the bus : “FA” implies, the bus has at least eight wires • Click on the Bus button of the Stimulator State Selection window : ►The value assigned is shown to the right of name “q” as “FA” CS 2204 Fall 2007 Experiment 2 Lab 5 Page 94 Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors To change the values of wires on the simulator window To have a clock signal as an input follow the steps below : • Make sure the input signal is not renamed as “q”, “w” etc. • Click on the input signal to select it • Click on the Select Stimulators button : • Click on Formula… • Double click on C1: under Clocks • Enter the following in the Edit Formula area : • 100ns=H 100ns=L ► This means a periodic signal which is 100 ns 1 and 100 ns 0 is generated ► The periodic signal has a period of 200ns or a frequency of 5MHz • Click Accept • Click Close • You will see the C1 button on the Select Stimulators window highlighted • Click on C1 so that the input signal is renamed C1 • Click on the Simulation Step button several times : • You will see the periodic signal automatically generated and the output values in response to that CS 2204 Fall 2007 Experiment 2 Lab 5 Page 95 Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors Start simulating the circuit for different input combinations If the circuit has 4 or less inputs, then simulate the circuit for all input combinations (test vectors) • 16 or less number of input combinations (test vectors) If the circuit has more than 4 inputs, select a number of input combinations (test vectors) then simulate the circuit for these test vectors • Which test vectors to choose is a very important task ! To simulate the circuit, click on the Simulation Step button several times : Observe the outputs If they are correct, try another input combination If wrong, return to the schematic and try to figure out why it is wrong ! If an output value is Hi-Z or Unknown, there is an error, correct it CS 2204 Fall 2007 Experiment 2 Lab 5 Page 96 Schematic Design Actions, Shortcuts & Reminders Printing schematics 1) Double click on the Printer227 icon on your desktop and wait about a minute to allow it to affect the printing option 2) Zoom into an area of the schematic to print the area 3) Select File -> Print on the schematic window 4) Change the option to Current View Only on the Print window 5) Click on Setup on the Print Window 6) Change the printer to HP Printer 8150 in Room 227 7) Click on Options to select Landscape printing if necessary 8) Click OK as many times as needed to print the page 9) Print one copy of each area and then make copies of the printed schematics for your partners CS 2204 Fall 2007 Experiment 2 Lab 5 Page 97 What to do if the testing on the board gives wrong results even thought the design is correct ? If the design is absolutely correct, here are the steps to follow in sequence : 1) 2) 3) 4) 5) 6) 7) 8) The FPGA board is turned on ? SW9 is in the PROG position ? The Bitronics Data Switch selects your PC ? The FPGA type and model are correct ? The implementation options are changed ? There are not too many levels of folders to reach the project on the PC ? Clear the implementation data, close the software, restart the software and do a new Xilinx IMPLEMENTATION Does it work now ? Delete the project, recreate the project, copy the schematic design from the saved schematic file Save the schematic file worked on in a separate folder • Does it work ? • Does it work ? Download the zipped project from the course web site, unzip it, copy the schematic design from the saved schematic file CS 2204 Fall 2007 Experiment 2 Lab 5 Page 98 What to do if the testing on the board gives wrong results even thought the design is correct ? 9) Repeat step 7, by using your partner’s working schematic 10) Login to another PC and try steps 5 - 8 11) Ask from the TA to help you a) The TA will login to your original PC and try steps 5 – 8 by using your schematic design and his/her S drive b) The TA will login to another PC and try steps 5 – 8 by using your schematic design and his/her S drive on the new PC c) The TA will inform the professor 12)If the project works on the second PC, inform the lab supervisor, Mr. Keni Yip that the original PC has a problem CS 2204 Fall 2007 Experiment 2 Lab 5 Page 99