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Lecture 7 and 8
joal 2005 HT:1 Em3
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Custom Designed Integrated Circuits
Extended FSM models
(RT-level)
• FSMs have normally only Boolean inputs as
conditions and Boolean outputs
• Sequential logic has both control path and
data path. How to describe?
• How can we include arithmetic in a FSM?
• One answer is to use a FSMD (FSM with Data
path)
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Custom Designed Integrated Circuits
Extended FSM Models
FSMD
Control path
(FSM)
Status
signals
X<Y
Y=Y-X
Control
signals
X>Y
X=X-Y
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Data path
(ALU etc)
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Custom Designed Integrated Circuits
Extended FSM Models
s1
Control
signals
s2
Condition
signals
=?
s3
s4
Control Path
Data Path
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Custom Designed Integrated Circuits
Extended FSM Models (FSMD)
State name
State box
Decision box
Condition box
Unconditional variable and
output assignments
0
Condition
1
Conditional
variable
assignment
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Custom Designed Integrated Circuits
Extended FSM Models (FSMD)
s0
s0
Block
s1
Block
s1
s2
Cond assign
Moore type
Mealy type
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Custom Designed Integrated Circuits
Extended FSM, UART Project
• We want to model the UART. Alternatives:
– Sequential language model (just VHDL)
– State machine model (FSM) for control and data path.
Control and condition signals between control path and
data path.
– Extended FSM (FSMD with data path)
• Model can be manually synthesized to VHDL code which
is automatically synthesized to logic
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Custom Designed Integrated Circuits
Extended FSM, UART Project
Buss interface
Bit rate
generator
Bit rate * 16
Receiver
Transmitter
FSM
FSM
RX Reg
TX Reg
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Custom Designed Integrated Circuits
Extended FSM, UART Project
Synchronous clock and bit clock
Do not gate the clock but use a condition!
process
begin
if reset=‘1’ then
.........
elsif clk’event and clk=‘1’ then
if bit_clk=‘1’ then -- bit clock= one clk period
.........
end if;
end if;
end process;
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Custom Designed Integrated Circuits
FSMD for UART Receiver
s2
s0
Cnt16=0
BitCnt=0
RX=0
RXRDY=1
RXRDY-set:
Strobe one
system clock!
0
s1
BitCnt=9
Cnt16=Cnt16+1
0
Cnt16=7
0
R=RX & R(9:1)
R=Par & R(9:1)
BitCnt=BitCnt+1
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Custom Designed Integrated Circuits
Design Productivity Gap
Moore’s Law: The capacity of integrated
chips doubles every 18-20 months.
108
Design
Productivity
Gap
106
1
65
75
80
85
90
95
2000 Time
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Custom Designed Integrated Circuits
History of Automation in System Design
Levels of Design Representation
2000
Partially
System Functional Specification

Behavioral Specification (VHDL)

RTL Design, “C-Code”

90s
85
80s
Logic Level Design, “Machine Code”

70’s
Physical Design

Implementation
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Custom Designed Integrated Circuits
Y-Chart
Behavioral
Domain
Structural Domain
Processors, Mem, Buses
Registers, ALUs, MuXs,
.
Gates, Flip-Flops
Transistors
Flowcharts, Algorithms
Register Transfers
Boolean Expressions
Transistor Functions
Transistor Layout
Cells, Modules
Chips, ASICs
Boards, MCM
Physical
Domain
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Custom Designed Integrated Circuits
Y-Chart-AXES
• Behavioral Axis
– Represents functionality: what the system is
supposed to do.
• Structural Axis
– Represents the logical interconnections of
components to build the system: how the system is
built by interconnecting sub-systems(components).
• Physical Axis
– Represents the physical implementation of the
system.
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Custom Designed Integrated Circuits
Design Representation in Y-Chart
Structural Domain
Processors, Mem, Buses
Registers, ALUs, MuXs,
.
Gates, Flip-Flops
Transistors
Behavioral
Domain
Functional
Flowcharts, Algorithms
Design
Register Transfers
Boolean Expressions
Transistor Functions
Transistor Layout
Cells, Modules
Physical Design
of a chip
Chip, ASIC
Boards, MCM
Physical
Domain
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 As we move towards the
center, we add more
details
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Custom Designed Integrated Circuits
Representation of Design Processes
Structural Domain
Processors, Mem, Buses
Registers, ALUs, MuXs,
.
Gates, Flip-Flops
Transistors
Behavioral
Domain
Synthesis
Flowcharts, Algorithms
Register Transfers
Boolean Expressions
Transistor Functions
Transistor Layout
Implementation
Cells, Modules
Chips, ASICs
Boards, MCM
Physical
Domain
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Custom Designed Integrated Circuits
High level design / Simulation
The efficiency of the designer will increase if she/he designs at a higher
abstraction level.
It’s possible to design and simulate VHDL on a Behavioural level. The
data types etc can be more freely chosen.
Special synthesis tools are required to synthesize on behavioural level!
Note the difference between behavioural level and behavioural synthesis!
We will come to Behavioural synthesis later in this lecture
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Custom Designed Integrated Circuits
Synthesis
Synthesis involves the transformation of system description from
behavioral domain to structural domain.
 Behavioral Synthesis
 Algorithmic description => RTL-design
 RTL-design: Design using Registers, adders, muxes etc.
 Logic Synthesis
 Boolean functions, Finite State Machines => Logic Design
 Logic design: Design using gates and flip-flops.
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Custom Designed Integrated Circuits
Synthesizable/Executable Spec.
Executable Specification
It is possible to simulate the specification to determine system
behaviour. Some languages give clock accurate simulation (e.g.
SystemC).
Synthesizable Specification
It is possible to build hardware with equivalent timing and
functional behaviour to the specification.
(A subset of VHDL is synthesizable)
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Custom Designed Integrated Circuits
Synthesizable VHDL: Examples
Simulation
Architecture XYZ of PQR is
Signal S1, S2, S3
Begin
•••••
•••••
S2 <= X and Y;
S3 <= S2 or Y after 3 ns;
••••••
End;
Y
S2
S3
X
Y
S2
&
1
S3
It is not possible to ensure the
delay to be exact 3 ns.
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Custom Designed Integrated Circuits
Behavioral and RTL Synthesis
x
Behavioral
Synthesis
x
x
-
-
+
x
+
4 cycles*15 ns
3 cycles*15 ns
Vary clock period
Vary # of clock periods
HDL Description
Z=a(i)*b(i)-c*d(k)+f
RTL
Synthesis
Vary clock period
1 clock cycle
x
-
+
2 cycles*20 ns
x
Multiple
Architectures
x
-
+
x
1 cycle*55 ns
Single
Architectures
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Custom Designed Integrated Circuits
Behavioral Synthesis: Illustration
ENTITY gcd IS
PORT (x_in,y_in: IN bit8; z_out: OUT bit8; clock,
start: IN BIT; ready: OUT BIT);
MUX
MUX
X-Reg
END gcd;
Y-Reg
ARCHITECTURE beh_gcd IS
BEGIN
MUX
PROCESS
Comparator
Variable x,y,z: bit8;
MUX
-
BEGIN
WAIT UNTIL start = ’1’;
Z-Reg
X= x_in; Y = y_in;
WHILE NOT( X=Y) LOOP
IF X > Y THEN X= X- Y ELSE Y = Y-X;
Controller
WAIT UNTIL clock’event;
END LOOP;
Z_out = X; ready = ’1’;
Control Signals
END Process
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Custom Designed Integrated Circuits
Behavioral Synthesis/High Level Synthesis
Behavioral synthesis translates the behavioral HDL (VHDL) description
to RTL-design (Register Transfer Level). Reuse of resources! Control of
resource usage done by Control Unit ( comapare to RTL-level)
Behavioral Synthesis Steps
 Scheduling
 To decide time for each operation
 Constrains on resources or time
 Allocation
 Resources: Registers, Memories, ALUs, buses etc.
 To decide the type and number of resources required.
 Binding
 Deciding a specific ALU for each operation
 Deciding a specific register for each varible.
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Custom Designed Integrated Circuits
Behavioral Synthesis/High Level Synthesis
 Data path: A number of interconnected components on RTL-level
 Control Unit: FSM that generates control signals for Data path
 Scheduling
To decide time for each operation. Determine in which clock
cycle a resource shall be executed. Different function can use the
same resource but not at the same time. The scheduler is
implemented as a State machine (control unit).
 Allocation
Allocate resources to operators. Decide the type and number of
resources required.
 Binding
Bind a special resource to a special operation
 Latency: Number of clock cycles required to execute a function.
 Throughput: How often new data can be clocked into the system.
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Custom Designed Integrated Circuits
Behavioral Synthesis/High Level Synthesis
1
*
+
*
*
2
2
The resources shall be
scheduled so the
resource with the
longest path to end shall
be scheduled first.
3
*
3
(one method)
+
4
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Custom Designed Integrated Circuits
Behavioral Synthesis/High Level Synthesis
Handshaking / Process synchronization
• VHDL code can be correctly simulated on behavioural level. It’s
clock accurate.
• After Behavioural synthesis the cycle-to-cycle behaviour is
changed (due to scheduling and resource allocation).
• The processes must be synchronized by handshake signals
data
ready
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Custom Designed Integrated Circuits
Behavioural synthesis
For special purposes a HW,
designed by Behavioural
Synthesis, can replace a micro
controller and SW
(SPP=Single Purpose
Processor).
Less over head
Faster
Example:
Scheduler in a Real time kernel in
HW. RealFast in Västerås
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Custom Designed Integrated Circuits
Technology Mapping
Technology mapping process converts a technology independent design
into a netlist of components from a particular technology
 Technology independent design (generic)
 Gates with any number of inputs or outputs.
 Register of any size and with any number of control signals.
 Technology dependent components
 A gate with 2 inputs and a specified fan-out.
 A gate optimized for speed.
 A gate optimized for area.
 Etc.
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Custom Designed Integrated Circuits
System Modelling
C has been used for system modelling and then refined with VHDL.
Newer methods:
SDL, Specification and Description Language (graphical)
SystemC (Class library to C++ for HW modelling)
EFSM = Extended Finite State Machine (data path and control
path). Control path generated by tool.
state A
process
X
wait for
signal
state B
process
Y
state A
signals
channel
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send
signal
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Custom Designed Integrated Circuits
System Modelling
HW and SW co-design and co-simulation.
Tools to partion HW and SW
New tools or extended “old” tools: Examples
1)
C / VHDL
2)
SystemC (C++ with class libraries
for hardware and communication
modelling)
3)
Superlog (extended Verilog)
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Custom Designed Integrated Circuits
IP, Intellectual Property
Virtual components / Cores
The design efficiency can be increased if tested components are reused.
Such virtual components are called IP (Intellectual Property).
Hard IP: Technology mapped for a special process or FPGA.
Soft IP: Synthesible HDL description (VHDL, Verilog, SystemC etc).
Examples of IP blocks :
Cores: Micro controllers, DSP, DES encryption modules etc.
IO-block: DRAM-controller, UART, USB, Firewire etc
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Custom Designed Integrated Circuits
SoC System On Chip
CPU
RAM
USER
LOGIC
Communication
Co
Processor
IO
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Custom Designed Integrated Circuits
SoC / SOPC
System On Programmable Chip
New technology (small scale) has high NRE (Nonrecurring Engineering
Cost). (1.2 => 0.6 => 0.35 => 0.25 => 0.15 => 0.13 =>0,09 ( ?? m)
Today (2003): NRE (0.13 m) $500k-1000k
(Write off for a fab is $2Bn+ over 3 years)
Q: Who can afford this?
A: Big companies with very high volumes.
Q: Why do we then study System Level Design? In Sweden only
Ericsson designs such circuits.
A: FPGAs with built in, hard or soft cores, also require system level
design methods.
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Custom Designed Integrated Circuits
NOC Network on Chip (ING Research)
network (packet swiched)
switch
resource
e.g. CPU
0110
0110
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Custom Designed Integrated Circuits
Seems interesting?
If System level design seems interesting
If Logic synthesis seems interesting
If Advanced HW design seems interesting
Apply for the Master program in Embedded
Systems!
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Custom Designed Integrated Circuits
ASIC
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Custom Designed Integrated Circuits
Customer Integrated Circuits
ASIC
(F)PLD
FPGA
Gate Array
Std Cell
PAL
Full Custom
SoC
ASIC = Application Specific Integrated Circuit
Gate Array = Prefabricated wafer with logic+added
interconnections (metal layers). Vol > 10k
Standard Cell = Library with components (e.g. gates,
multiplexors, flip-flops). Precompiled on
transistor level. Vol >100k
Full Custom = Transistor level design. Used for analog
circuits.
SoC = System on Chip. Processors and logic on chip.
SoPC
CPLD
PLD
FPLD = Field Programmable Logic
Device.
FPGA = Field Programmable Gate Array.
>1 milj gates!
PLD = Programmable Logic Device
CPLD = Complex PLD. <10k gates
SoPC = System on Programmable Chip
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Custom Designed Integrated Circuits
ASIC Design Phases
Design
Fabrication
• From idea to synthesizable model
• From synthesizable model  masks
Wafer fabrication
• To check the fabricated chip
Testing
Packaging
• Slicing of wafer into separate chips
wire bonding  packaging
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Custom Designed Integrated Circuits
ASIC Design Phase
Design
Synthesis and
Optimization
Fabrication
Netlist
Place & Route
Simulations
Testing
Packaging
Validation
GDS-II
tape
Mask set
(Photo masks)
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Custom Designed Integrated Circuits
ASIC Fabrication Phase
Design
Silocon
wafers
Dia= 4”,
6”, 8”.. etc
Thickness
= 0.5 mm
Fabrication
Semiconductors
fabrication
Testing
Packaging
Metal layers
interconnections
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Standard cell
& Full
custom
Only custom
stage in Gate
Array
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Custom Designed Integrated Circuits
ASIC Fabrication Phase
Design
Fabrication
Testing
Test vectors
Wafer tests
(Probing of pads)
Test equipment
Connection
pads
Packaging
Chip
Wafer
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Custom Designed Integrated Circuits
ASIC Fabrication Phase
Design
Scribing
(Cutting wafers
to chips)
Fabrication
Bonding e.g.
wire bonding
to lead frame
Testing
Plastic
moulding or
ceramic
packaging
Packaging
and test
Test of circuits
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chip
Test vectors
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Custom Designed Integrated Circuits
n-MOS transistor basics
Gate
oxide
Source
Gate
Drain
------------------------
n+
Channel (minority
carriers=e-)
n+
p+
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Positive voltage on the
gate will result in a
channel of electrons
below the gate oxide
(inversion => majority
carriers will be replaced
with minority carriers).
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Custom Designed Integrated Circuits
p_MOS transistor basics
Gate
oxide
Source
Gate
Drain
+++++++++++++ + +++++
p+
p+
p+
p+
n-well
n+
p+
joal 2005 HT:1 Em3
Negative voltage
(relative source) on the
gate will result in a
channel of holes below
the gate oxide (inversion
=> majority carriers will
be replaced with
minority carriers).
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Custom Designed Integrated Circuits
ASIC Fabrication
Phases
Si - substrate
Si-oxide
Lithography
Si - substrate
Photo resist:
Organic polymer.
photo resist
Positive photo resist:
soluble after exposure with UVlight (shorter and shorter
wavelengths required)
Si - substrate
UV -light
Glass photo
mask
Si - substrate
etching
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Si - substrate
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Custom Designed Integrated Circuits
n-channel MOSFET
SiO2
SiO2
Si-substrate
Si-substrate
Etching
SiO2
Si-substrate
Poly silicon
Doping
(diffusion / Ion
implantation)
SiO2
Si-substrate
Thin
oxide
n+
Si-substrate
metal
connectors
n+
SiO2
n+
n+
Si-substrate
Si-substrate
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Custom Designed Integrated Circuits
CMOS inverter
in
in
out
VDD
VSS
p+
p+
n+
n+
n+
n-well
p+
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Custom Designed Integrated Circuits
CMOS inverter
Vout
Vin
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Custom Designed Integrated Circuits
CMOS inverter
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Custom Designed Integrated Circuits
NAND gate
CMOS circuits
P
a
b
P
N
z
&
z
a
N
b
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Custom Designed Integrated Circuits
VLSI words
• 0.25 micron process, 0.13 micron process, 0.09 micron process:
smallest dimension in a transistor is 0.25 micro meter etc
• Cu- layers. Copper is used for the metal layers => lower resistance in
the signal wires. 9 metal layers is not unusual!
• 6 inch wafer, 8 inch wafer: Diameter is 6 inches, 8 inches (newest).
• NRE (Non Recurring Engineering costs. Includes e.g. mask set costs.
NRE increases with new (smaller) technology
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Custom Designed Integrated Circuits
NRE cost evaluation
• Typical cost for an ASIC in 0.18 m is $5 millions, in 0.13 m $10
millions. Future 0.45 m will cost more than $15 millions.
• Only Asic’s in very high volumes possible (>100k, >1000k)
• Possible solutions to ASIC cost problem:
• “Structured ASIC”: Modern Gate Array (GA) with more complex
building blocks than traditionally GA’s.
• Converted FPGA to “Hardwired FPGA” => faster, cheaper
http://www.altera.com/products/software/pld/products/q2/qtsindex.html?xy=qts-gif
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Custom Designed Integrated Circuits
VHDL Test bench
problem
- tb_exempel
-- joal 2003-10-07
-- Abstract: To demonstrate how multiple drivers can be
-- generated in a test bench and
-- how to avoid problems with that
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
-***********************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY tb_exempel IS
END tb_exempel ;
ARCHITECTURE behav OF tb_exempel IS
component tt_buffer is
port(rd: in std_logic;
out_buffer: inout std_logic_vector(7 downto 0));
end component;
signal rd: std_logic;
signal out_buffer: std_logic_vector(7 downto 0);
BEGIN
u1: tt_buffer port map (rd,out_buffer);
process
begin
rd<='1';
wait for 500 ns;
rd<='0';
wait;
end process;
process
begin
wait for 1 us;
out_buffer<="10101010";
wait;
end process;
END behav;
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Custom Designed Integrated Circuits
ARCHITECTURE behav OF tb_exempel IS
component tt_buffer is
port(rd: in std_logic;
out_buffer: inout std_logic_vector(7 downto 0));
- tb_exempel
end component;
-- joal 2003-10-07
signal rd: std_logic;
-- Abstract: To demonstrate how multiple drivers can be
signal out_buffer: std_logic_vector(7 downto 0);
-- generated in a test bench and
BEGIN
-- how to avoid problems with that
u1: tt_buffer port map (rd,out_buffer);
process
begin
LIBRARY ieee;
rd<='1';
USE ieee.std_logic_1164.ALL;
wait for 500 ns;
USE ieee.std_logic_arith.ALL;
rd<='0';
wait;
-end process;
***********************************************
process
LIBRARY ieee;
begin
USE ieee.std_logic_1164.ALL;
-- out_buffer driver in this process must have a start value
USE ieee.std_logic_arith.ALL;
– otherwise ’U’ is used and can't be resolved!!!!
out_buffer<="ZZZZZZZZ";
ENTITY tb_exempel IS
wait for 1 us;
END tb_exempel ;
out_buffer<="10101010";
wait;
end process;
END behav;
VHDL Test bench
problem
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Custom Designed Integrated Circuits
VHDL Test bench problem
Before code corrected
rd
out_buffer
UUUUUUUU
10101010
After code corrected
rd
out_buffer
01010101
10101010
1 s
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Custom Designed Integrated Circuits
IEEE 1076.1-1999 /VHDL-AMS, Analog modeling added
http://www.eda.org/vhdl-ams/
----------------------------------------------------------------------- The capacitor definition begins.....
----------------------------------------------------------------------- Schematic of the capacitor component:
--Ta1 o----||----o Tb1
----------------------------------------------------------------------LIBRARY DISCIPLINES;
USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
ENTITY Capacitance IS
GENERIC (val
: REAL);
PORT
(TERMINAL p,m
: ELECTRICAL);
END;
ARCHITECTURE behav OF Capacitance IS
QUANTITY u_c ACROSS i_c THROUGH p TO m;
BEGIN
i_c==val * u_c'dot;
END;
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Custom Designed Integrated Circuits
VHDL-AMS, Analog modeling added
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Custom Designed Integrated Circuits