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Chapter 3 Interconnect: Wire Models Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory June 22, 2005- revised July 1,2006 B.Supmonchai Outlines Interconnects at first glance Wire Capacitances Wire Resistances Wiring Models Wire Inductance 2102-545 Digital ICs Interconnect: Wire Models 2 B.Supmonchai Interconnect: The Wire Transmitters Receivers Schematics 2102-545 Digital ICs Physical Interconnect: Wire Models 3 B.Supmonchai Interconnect (Wire) Models All-inclusive model Capacitance-only (R, L, and C present) 2102-545 Digital ICs Interconnect: Wire Models 4 B.Supmonchai Modern Interconnect 2102-545 Digital ICs State-of-the-art processes offer multiple layers of aluminum or copper, and at least one layer of polysilicon Even the n+ and p+ diffusion layers can be used for wiring purposes. Interconnect: Wire Models 5 B.Supmonchai Interconnect Impact on Chip 2102-545 Digital ICs Interconnect: Wire Models 6 B.Supmonchai Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric 2102-545 Digital ICs Interconnect: Wire Models 7 B.Supmonchai No of nets (Log Scale) Local Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II Global Interconnect SGlobal = SDie SLocal = STechnology 10 100 Source: Intel Nature of Interconnect 1,000 10,000 100,000 Length (u) 2102-545 Digital ICs Interconnect: Wire Models 8 B.Supmonchai Interconnect Parasitics Effects of Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive 2102-545 Digital ICs Interconnect: Wire Models 9 B.Supmonchai Parasitic Simplifications Inductive effects can be ignored if The resistance of the wire is substantial enough (as is the case for long Al wires with small cross section) The rise and fall times of the applied signals are slow enough When the wire is short, or the cross-section is large, or the interconnect material has low resistivity, a capacitance only model can be used 2102-545 Digital ICs Interconnect: Wire Models 10 B.Supmonchai Parasitics Simplifications (Cont.) When the separation between neighboring wires is large, or when the wires run together for only a short distance, interwire capacitance can be ignored and all the parasitic capacitance can be modeled as capacitance to ground 2102-545 Digital ICs Interconnect: Wire Models 11 B.Supmonchai Example: A Simple Wire Model VDD VDD M2 M2 Vin Cdb2 Cg4 Cdb2 Cgd12 Cgd12 Vin Cdb1 M1 VDD VDD Vout Vout Cw Cg3 Cdb1 Cw M1 Interconnect Interconnect M4 Cg4 Vout2 M3 Cg3 M4 Vout2 M3 Fanout Fanout Vin Simplified Simplified Model Model 2102-545 Digital ICs Vin Vout CL Interconnect: Wire Models Fanout Vout CL 12 B.Supmonchai Outlines Interconnects at first glance Wire Capacitances Wire Resistances Wiring Models Wire Inductance 2102-545 Digital ICs Interconnect: Wire Models 13 B.Supmonchai Wiring Capacitance The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates. Wiring capacitance is growing in importance with the scaling of technology. There are 3 components in wiring capacitance Parallel Plate Capacitance Fringing Capacitance Interwire Capacitance 2102-545 Digital ICs Interconnect: Wire Models 14 B.Supmonchai Capacitance: The Parallel Plate Model Current Flow L W H tD Dielectric Electric Field Cint 2102-545 Digital ICs di t di WL Substrate di = Dielectric permittivity constant (SiO2= 3.9) Interconnect: Wire Models 15 B.Supmonchai (Relative) Permittivity of Some Materials 2102-545 Digital ICs Material di Free space 1 Teflon AF 2.1 Aromatic thermosets (SiLK) 2.6 – 2.8 Polyimides (organic) 3.1 – 3.4 Fluorosilicate glass (FSG) 3.2 – 4.0 Silicon dioxide 3.9 – 4.5 Glass epoxy (PCBs) 5 Silicon nitride 7.5 Alumina (package) 9.5 Silicon 11.7 Interconnect: Wire Models 16 B.Supmonchai Fringing Capacitance W W-H/2 L H H First Approximate Model H W-H/2 CW ire CPP C fringe + Second Approximate Model 2102-545 Digital ICs Interconnect: Wire Models cW ire Wdi 2di t di log tdi H (per length Capacitance) 17 B.Supmonchai Fringing versus Parallel Plate For SiO2 with relative permittivity = 3.9 For larger values of W/H (smaller values of H/tdi) the total capacitance approaches the parallel-plate model. Total capacitance levels off to a constant value of approx. 1 pF/cm for line widths smaller than the insulator thickness (i.e., is no longer a function of the width) (from [Bakoglu89]) 2102-545 Digital ICs Interconnect: Wire Models 18 B.Supmonchai Interwire Capacitance fringing fringing parallel parallel CW ire CPP C fringe Ciw Interwire Interwire capacitance is responsible for Cross-Talk CW ire 2102-545 Digital ICs diWL t di 2diL diHLI log tdi H t di Interconnect: Wire Models 19 B.Supmonchai Impact of Interwire Capacitance When W < 1.75H interwire capacitance starts to dominate Interwire capacitance is more pronounced for wires in the higher interconnect layers (further from the substrate) Wire delay nearly proportional to L2 For SiO2 with relative permittivity = 3.9 (from [Bakoglu89]) 2102-545 Digital ICs Interconnect: Wire Models 20 B.Supmonchai Wiring Capacitances (0.25 µm CMOS) Poly Al1 Al2 Al3 Al4 Al5 Field Active Poly 88 54 30 40 13 25 8.9 18 6.5 14 5.2 12 41 47 15 27 9.4 19 6.8 15 5.4 12 57 54 17 29 10 20 7 15 5.4 12 Interwire Cap Al1 Al2 Al3 Al4 PP in aF/m2 fringe in aF/m 36 45 15 27 8.9 18 6.6 14 41 49 15 27 9.1 19 35 45 14 27 38 52 Poly Al1 Al2 Al3 Al4 Al5 40 95 85 85 85 115 per unit wire length in aF/m for minimally-spaced wires 2102-545 Digital ICs Interconnect: Wire Models 21 B.Supmonchai Examples of Wire Capacitances Consider a wire of 10 cm long and 1 micron wide routed in Al1 (e.g., clock line) (over field) then Cpp = (0.1 x 106 micron2) x 30 aF/micron2 = 3 pF Cfringe = 2 x (0.1 x 106 micron) x 40 aF/micron = 8 pF Now, if a second wire is routed alongside the first wire with minimum separation Cinterwire = (0.1 x 106 micron) x 95 aF/micron = 9.5 pF The same wire, if it were routed in Al4 (over field), Cpp = 0.65 pF, Cfringe = 2.8 pF, Cinterwire = 8.5 pF 2102-545 Digital ICs Interconnect: Wire Models 22 B.Supmonchai Dealing with Capacitances Use of Low Capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO2 Family of materials that are low-k dielectrics must be suitable thermally and mechanically Must also be compatible with (copper) interconnect Copper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance 2102-545 Digital ICs Interconnect: Wire Models 23 B.Supmonchai Dealing with Capacitances (Cont.) Use SOI (silicon on insulator) to reduce junction capacitance Rules of thumb! Never run wires in diffusion Use poly only for short runs Shorter wires – lower R and C Thinner wires – lower C but higher R 2102-545 Digital ICs Interconnect: Wire Models 24 B.Supmonchai Outlines Interconnects at first glance Wire Capacitances Wire Resistances Wiring Models Wire Inductance 2102-545 Digital ICs Interconnect: Wire Models 25 B.Supmonchai Wire Resistance R= L H 2102-545 Digital ICs A L = H W Sheet Resistance R W R1 L = R2 Resistance of a square conductor is independent of its absolute size Interconnect: Wire Models 26 B.Supmonchai Interconnect Resistance Sheet Resistance for a typical 0.25 micron CMOS process Resistivity of commonly used conductor (at 20 C) Material (-m) Silver (Ag) 1.6 x 10-8 Copper (Cu) 1.7 x 10-8 Gold (Au) 2.2 x 10-8 Aluminum (Al) Tungsten (W) • • 2.7 x 10-8 5.5 x 10-8 Material Sheet Res. (/) n, p well diffusion 1000 to 1500 n+, p+ diffusion 50 to 150 n+, p+ diffusion with silicide 3 to 5 polysilicon 150 to 200 polysilicon with silicide 4 to 5 Aluminum 0.05 to 0.1 Aluminum used due to low cost and compatibility with fab process Top of the line processes (e.g., IBM) are now increasingly using Copper as the conductor of choice 2102-545 Digital ICs Interconnect: Wire Models 27 B.Supmonchai Skin Effect At high frequency, currents tend to flow primarily on the surface of a conductor with the current density falling off exponentially with depth into the wire W = (/(f)) H where f is frequency = 4 x 10-7 H/m = 2.6 m for Al at 1 GHz so the overall cross section is ~ 2(W+H) Example: H = 10 and W = 20, at 1 GHz effective cross section area is not 200 but 2(10+20)2.6 = 156 2102-545 Digital ICs Interconnect: Wire Models 28 B.Supmonchai Skin Effect (Cont.) The onset of skin effect is at fs where the skin depth is equal to half the largest dimension of the wire. fs = 4 / ( (max(W, H))2) where is the permeability of the surrounding dielectric Below fs, the whole wire is conducting current Skin effect increases resistance of the wire due to the decreased effective cross section area. 2102-545 Digital ICs Interconnect: Wire Models 29 Skin Effect for Different W’s % Increase in Resistance 1000 B.Supmonchai for H = .70 um 100 10 1 0.1 W = 1 um W = 10 um W = 20 um 1E8 1E9 1E10 Frequency (Hz) A 30% increase in resistance is observed for 20 m Al wires at 1 GHz (versus only a 1% increase for 1 m wires) 2102-545 Digital ICs Interconnect: Wire Models 30 B.Supmonchai Dealing with Resistance Selective Technology Scaling Scale W while holding H constant Use Better Interconnect Materials Lower resistivity materials like copper Silicides (WSi2, TiSi2, PtSi2 and TaSi) Conductivity is 8-10 times better than poly alone More Interconnect Layers Reduce average wire-length (but beware of extra contact!) 2102-545 Digital ICs Interconnect: Wire Models 31 B.Supmonchai Polycide Gate MOSFET Silicide PolySilicon SiO2 + + n n p A silicide is a compound material formed using silicon and a refractory metal (W, Ti2, Pt2 and Ta) to create a highly conductive material that can withstand hightemperature process steps without melting. 2102-545 Digital ICs Interconnect: Wire Models 32 B.Supmonchai Outlines Interconnects at first glance Wire Capacitances Wire Resistances Wiring Models Wire Inductance 2102-545 Digital ICs Interconnect: Wire Models 33 B.Supmonchai Electrical Wire Models Parasitics of the interconnect have an impact on the behavior of the circuit: delay, power dissipation, and reliability To study these effects, electrical wire models are introduced to simulate the real behavior of the wire as a function of its parameters. From simple to complex models are: 2102-545 Digital ICs Ideal Wire Model Lumped C Model Lumped RC Model Distributed RC Model Interconnect: Wire Models 34 B.Supmonchai Ideal Wire Model Wires are treated as simple lines with no attached parameters or parasitics Same voltage is present at every segment of the wire at every point in time - at equi-potential Voltage change at one end propagates immediately to the other ends, no matter how far, without delay. Only holds for very short wires, i.e., interconnects between very nearest neighbor gates Small circuit components: gates 2102-545 Digital ICs Interconnect: Wire Models 35 B.Supmonchai Lumped Model Different fractions (distributed parasitics) can be lumped into a single circuit element, if Only a single parasitic component (R, C, or L) is dominant The interaction between the components is small Only one aspect of the circuit behavior is the focus Advantage: Effects of parasitics can be described by an ordinary differential equation Distributed Model requires Partial Differential Eq. 2102-545 Digital ICs Interconnect: Wire Models 36 B.Supmonchai Lumped C Model When the resistive component is small and the switching frequency is low to medium, only capacitive component of the wire can be considered and lumped into a single C Rdriver Vo ut V out cwi re Vin Driver Clumped Still equipotential! Simple yet effective; only introduces the loading effect of the capacitor onto the driving gate 2102-545 Digital ICs Interconnect: Wire Models 37 B.Supmonchai Lumped RC model Total wire resistance is lumped into a single R and total capacitance into a single C driver wire Vin Rdriver Rw Vout Cw Good for short wires; pessimistic and inaccurate for long wires 2102-545 Digital ICs Interconnect: Wire Models 38 B.Supmonchai Distributed RC model Circuit parasitics are distributed along the length, L, of the wire c and r are the capacitance and resistance per unit length Vin rL rL rL rL (r,c,L) rL VN cL cL cL cL Vin VN cL V V rc 2 t x 2 Diffusion Equation 2102-545 Digital ICs Interconnect: Wire Models (N ) 39 B.Supmonchai RC Tree Characteristics What is a RC Tree? A RC Network is a Tree if … A unique resistive path exists between the source node and any node of the network Single input (source) node, s All capacitors are between a node and GND No resistive loops 2102-545 Digital ICs Interconnect: Wire Models 40 B.Supmonchai RC Tree Elmore Delay Solving for Delay time at any points in the tree is intractable. Exact Analyses involve solving differential equations of very high degree. Every Capacitor added raises the degree of the differential equations by one. Elmore Delay Calculation is a reasonable approximation to the exact solution. Beware of the Tree assumption! Once again, good for short wires and give pessimistic results. 2102-545 Digital ICs Interconnect: Wire Models 41 B.Supmonchai RC Tree Elmore Delay (Cont.) Path resistance sum of the resistances on the path from the input node to node i Rii = Rj (Rj [path(s i)]) Shared path resistance resistance shared along the paths from the input node to nodes i and k Rik = Rj (Rj [path(s i) path(s k)]) Elmore Delay at node i in an RC tree is given by N Di Ck Rik first-order time constant of the network k1 2102-545 Digital ICs Interconnect: Wire Models 42 B.Supmonchai Example: Elmore Delay Calculation Find the Delay (after input dropped) at terminal 4. R41 R1, R42 R1, R43 R1 R3 R44 R1 R3 R4 R4 i R1 R3 N D 4 Ck R4 k C1R41 C2 R42 C3 R43 C4 R44 Ci R4 i 2102-545 Digital ICs k1 Interconnect: Wire Models 43 B.Supmonchai RC Chain Elmore Delay 1 = C 1R 1 R1 Vin C1 1 2 = C1R1 + C2(R1+R2) R2 Ri-1 2 C2 i-1 Ci-1 Ri i Ci RN N VN CN i = C1R1+ C2(R1+R2)+…+Ci(R1+R2+…+Ri) Elmore delay equation If all Ri are equal and all Ci are equal then 2102-545 Digital ICs Interconnect: Wire Models i = N(N+1)RC/2 44 B.Supmonchai A Simple Distributed RC Wire Model An RC wire of length L can be modeled by N segments of equal length L/N Given r and c, the wire resistance and wire capacitance per unit length The resistance and capacitance of each segment are given by r L/N and c L/N From the RC chain Elmore delay, 2102-545 Digital ICs Interconnect: Wire Models 45 B.Supmonchai Distributed RC Model Approximation For large number of segments N D lim DN RC lim N rcL2 D 2 N 1 N 2N RC 2 In terms of distributed parameter Observation: Delay of a wire is a quadratic function of its length, L The delay is only half of that predicted by the lumped RC model 2102-545 Digital ICs Interconnect: Wire Models 46 B.Supmonchai Step Responses of RC Wire Models L=1 Vi Needs to solve a set of partial differential equations Vo 1 0 Parameter Voltage Range Lumped RC Distributed RC Prop. Delay - tp 0 50% 0.69 RC 0.38 RC Delay Const. - 0 63% RC 0.5 RC 10% 90% 2.2 RC 0.9 RC 0 90% 2.3 RC 1.0 RC Rise time - tr (Fall time - tf) 2102-545 Digital ICs Interconnect: Wire Models 47 B.Supmonchai Other Distributed Lumped Models Accuracy - + Distributed π Model Distributed T Model 2102-545 Digital ICs Interconnect: Wire Models 48 B.Supmonchai Step Response Examples Consider a Al1 wire 10 cm long and 1 m wide Using a lumped C only model with a source resistance (RDriver) of 10 k and a total lumped capacitance (Clumped) of 11 pF • tp = 0.69 x 10 k x 11pF = 76 ns • tr = 2.2 x 10 k x 11pF = 242 ns Using a distributed RC model with c = 110 aF/m and r = 0.075 /m • tp = 0.38 x (0.075 /m) x (110 aF/m) x (105 m)2 = 31.4 ns • tr = 0.9 x (0.075 /m) x (110 aF/m) x (105 m)2 = 74.25 ns • Poly: tr = 0.38 x (150 /m) x (88+254 aF/m) x (105 m)2 = 112 s • Al5: tr = 0.38 x (0.0375 /m) x (5.2+212 aF/m) x (105m)2 = 4.2 ns 2102-545 Digital ICs Interconnect: Wire Models 49 B.Supmonchai Putting It All Together Rs (r w,cw,L) Vout V in Total Delay Propagation Delay The delay introduced by wire resistance becomes dominant when (RwCw)/2 ≥ RsCw (when L ≥ 2Rs/rw) For an Rs = 1 kΩ driving a 1 µm-wide Al1 wire, Lcrit is 2.67 cm 2102-545 Digital ICs Interconnect: Wire Models 50 B.Supmonchai Design Rules of Thumb rc delays should only be considered when tpRC >> tp,gate of the driving gate Lcrit >> tp,gate/0.38rc Actual Lcrit depends upon the size of the driving gate and the interconnect material rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line trise < RC when not met, the change in the signal is slower than the propagation delay of the wire 2102-545 Digital ICs Interconnect: Wire Models © MJIrwin, PSU, 2000 51 B.Supmonchai Outlines Interconnects at first glance Wire Capacitances Wire Resistances Wiring Models Wire Inductance 2102-545 Digital ICs Interconnect: Wire Models 52 B.Supmonchai Inductance When the rise and fall times of the signal become comparable to the time of flight of the signal waveform across the line, then the inductance of the wire starts to dominate the delay behavior Vin l r g l r c g r c l l g r c Vout g c The condition holds only when the switching speed is sufficiently fast and the quality of the interconnect material is high enough that the resistance of the wire is kept within bounds. 2102-545 Digital ICs Interconnect: Wire Models 53 B.Supmonchai The Transmission Line Effects Signal propagates over the wire as a wave (rather than diffusing as in rc only models) Signal propagates by alternately transferring energy from capacitive to inductive modes It causes ringing – when wave is reflected back on itself reduces speed To avoid wave reflection of signal we must terminate the wire correctly (a matched termination, avoid open and short circuit terminations) 2102-545 Digital ICs Interconnect: Wire Models 54 B.Supmonchai More Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight) tr (tf) < 2.5 tflight = 2.5 L/v where v is the velocity (speed) of propagation within the medium (Al) For on-chip wires with a max. length of 1 cm, we only worry about transmission line effects when tr < 150 ps 2102-545 Digital ICs Interconnect: Wire Models 55 B.Supmonchai More Design Rules of Thumb (Cont.) Transmission line effects should be considered only when the total resistance of the wire is limited R < 5 Z0 = 5 (V/I) where Z0 is the characteristic impedance of the wire Z0 is a function of the dielectric medium and the geometry of the conducting wire and isolator (it is independent of the length of the wire and the frequency of its signal). Typical values of characteristic impedances of wires in semiconductor circuits is from 10 to 200 ohms 2102-545 Digital ICs Interconnect: Wire Models 56 B.Supmonchai Wire Spacing Comparisons Intel P858 Al, 0.18m Intel P856.5 Al, 0.25m - 0.07 - 0.05 - 0.12 - 0.33 - 0.33 - 1.11 Scale: 2,160 nm 2102-545 Digital ICs IBM CMOS-8S CU, 0.18m M6 M5 - 0.10 M7 - 0.08 M5 - 0.10 M6 - 0.17 M4 - 0.50 M5 - 0.50 M4 - 0.50 M3 M4 M3 - 0.49 M3 M2 - 0.49 M2 - 0.70 M2 - 1.00 M1 - 0.97 M1 M1 Closer, C increased Interconnect: Wire Models Copper, C ~ CP858 From MPR, 2000 57 B.Supmonchai Comparison of Wire Delays 1 Normalized Wire Delay 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Al/SiO2 Cu/SiO2 Cu/FSG Cu/SiLK Relative speed of a 200-micron M3 wire for four metal/dielectric systems. All three copper wires were the same thickness and the aluminum wire was scaled to the same sheet resistance. From MPR, 2000 2102-545 Digital ICs Interconnect: Wire Models 58