Download Audio Visual Hints

Analysis and Reduction Soft
Delay Errors in CMOS Circuits
Balkaran Gill, Chris Papachristou,
and Francis Wolff
Department of Electrical Engineering
and Computer Science.
Case Western Reserve University
Cleveland Ohio USA
Gill
1
MAPLD 2005/234
Outline
•
•
•
•
•
Gill
Introduction.
Soft delay phenomenon.
Soft delay modeling.
Soft delay error analysis and reduction
technique in combinational circuits.
Future work and conclusion.
2
MAPLD 2005/234
Introduction
•
•
•
Gill
Single Event Upsets (SEUs) are due to high
energy particle strikes at sensitive nodes in
CMOS circuits.
These upsets originate from cosmic rays in
outer space and α-particles within the chip.
Soft Error Rate (SER) in CMOS circuits is
projected to increase as the process
technology scales down.
3
MAPLD 2005/234
Introduction (cont’d)
•
•
•
•
Gill
A particle strike at the sensitive nodes of
combinational circuits results in a glitch
(pulse) which can propagate to the circuit
output and captured by output flip-flops.
A particle strike at the sensitive node during
the signal transition can result in temporary
delay (soft delay) which can violate the
circuit timing.
SEUs in memory cause temporary cell flip.
Semiconductor memories are more
vulnerable than logic.
4
MAPLD 2005/234
Soft Delay Phenomenon
•
Gill
When a particle strike occurs during the
transition at a node, it can introduce
additional temporary delay.
5
MAPLD 2005/234
Soft Delay Propagation
•
Gill
Propagation of the soft delay.
6
MAPLD 2005/234
Soft Delay Propagation
•
The pulse
generated due
to the particle
strike during
the transition
attenuates
resulting in
soft delay.
Soft Delay Error
Gill
7
MAPLD 2005/234
Soft Delay Modeling
•
Gill
Mixed-mode simulations: Circuit and Device
Simulations.
8
MAPLD 2005/234
Device simulations for Soft Delay
•
Gill
Particle strike simulations using photogeneration models in DAVINCI.
9
MAPLD 2005/234
Current Pulse Extraction
•
Gill
Extracted current pulses for various
energies of the hitting particle.
10
MAPLD 2005/234
Soft Delay in ISCAS85 Benchmark
Circuits
•
Gill
Soft delay at the critical path of ISCAS85
circuits for various hitting particle energies.
11
MAPLD 2005/234
Soft Delay Error Analysis and Mitigation
Flow
Gill
12
MAPLD 2005/234
Reducing SDE - Example
Gill
13
MAPLD 2005/234
Conclusion
•
•
•
•
Gill
Found Soft Delay problem and developed
models to analyze its effects.
Verification of the soft delay using mixedmode simulations.
Characterization of the soft delay in
ISCAS85 circuits.
Soft delay error analysis and mitigation
technique.
14
MAPLD 2005/234
Current and Future Work
•
Current work
• Soft delay error analysis approach for large
circuits.
• Soft errors analysis in reconfigurable system
(FPGA).
•
Future work
• System level node sensitivity analysis
approach.
• Mitigation techniques for soft errors in VLSI
circuits.
• Mitigation techniques for soft errors in SRAM.
Gill
15
MAPLD 2005/234