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MODERN WP5 June
Meetings
Test structures and demonstrators
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
1
Contact List
WP5 Manager
T5.1
Task leader
Task participants
T5.2
Task leader
Task participants
(timing analysis)
(substrate noise)
T5.3
Task leader
Task participants
Loris Vendrame
NMX
[email protected]
+39 039 603 6818
Ehrenfried Seebacher
Alexander Steinmair
Peter Söser
Aurelie Bajolet
Loris Vendrame
AMS
AMS
TUGI
ST-F2
NMX
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
+43 3136 500 5487
+43 3136 500 5617
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
+43 5 1777 6779
Edit BEIGNE
Francesc Moll
Marc Renaudin
Boris Ljevar
Sergei Kapora
Philippe Bonnot
Arnaud Grasset
Peter Söser
IFXA
LETI
UPC
TMPO
NXP
NXP
THL
THL
TUGI
Ronald Gull
Jan ter Maten
Philippe Bonnot
Arnaud Grasset
Angelo Ciccazzo
SNPS
NXP
THL
THL
ST-I
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
+41 44 567 1512
Project Review Meeting
Crolles, June 22-23, 2009
+33 4 38 92 23 60
+39 039 603 6818
+34 934016846
+33 4 76 61 10 00
+33 1 69 41 60 59
+33 1 69 41 60 55
+33 1 69 41 60 59
+33 1 69 41 60 55
+39 0957 403179
23/05/2017
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WP2 Task Leaders
WP5
NMX
[email protected]
T5.1
AMS
[email protected]
T5.2
IFXA
[email protected]
T5.3
SNPS
[email protected]
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
3
WP5 T5.1 Purpose and links
• Test structures for PV analysis: design,
implementation and characterization
• Links:
– AMS and TUGI is working in close relationship in WP5 T5.1 and
T5.2.
– In T5.1 PV will be analyzed with PCM test structures
concentrating on analog/HV design requirements.
– Tools which are developed in WP2 concerning PV and reliability
for HV LDMOS transistors will be benchmarked in WP5 T5.2.
This work will be done in cooperation of AMS,TUGI and TUW.
– NMX and STF are in touch for matching test structures for
possible cooperation
– NMX is working together UNET sharing the results within T2.3
• .
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
4
WP5 T5.1 Review
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Company/Contributor: AMS/TUGI
Status/plan
– # review of the present test structures and split in categories like reliability parameter, design
parameter etc.
– # check the requirements for analog design
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Specifications:
– Process Control Monitor structures including additional analog parameter test structures
– Technology: HV CMOS: concentrating on MOS and LDMOS transistors
-o-o-oCompany/Contributor: STF
Status/plan
– the review of the matching structures is ongoing among them
Kelvin structures versus traditional structures, impact of WPE...
– It should be ready for M12 delivery
Specifications:
– Technology: mainly 45nm
-o–o–oCompany/Contributor: NMX
Status/plan:
– available test structures (focus on logic devices for analogue NVM circuits) are under
investigation; results are bring back into T2.3 and analized in cooperation with UNET
Specifications:
– Technology: different NVM technologies nodes (for logic devices gate oxide in 30 to 300A
range)
Issues
Interaction need with other:
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
5
WP5 T5.2 Purpose and links
• Demonstrator: design, implementation and
characterization
• Links:
– TUGI: Tools which are developed in WP2 concerning PV and reliability for HV
LDMOS transistors will be benchmarked in WP5 T5.2. This work will be done in
cooperation of AMS,TUGI and TUW.
– IFAT is working on demonstrators and test structures to verify developed monitor
and control concepts to compensate for degradation/aging effects and
degradation/aging induced process variations in analog, mixed-signal and RF
circuits. The work is closely linked to Task 3.3. Demonstrators will be fabricated
at foundries.
– TIEMPO link with WP4 results. 65 or 45nm silicon (TBD)
– LETI with WP3 and T4.1 and T4.2 ; 32nm silicon
– NXP link within WP3
– UPC involved in WP3 and WP4
– THALES involved in T4.3 and ISD
• .
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
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•
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WP5 T5.2 Review
Company/Contributor: TUGI (AMS)
AMS, TUGI and TUW is working in close relationship. Demonstrator design is related
to the developed tools in WP2 where AMS and TUW work on variability and reliability
simulation of LDMOS transistors. The demonstrator will verify the developed Silicon
and TCAD based SPICE parameter sets which describe degradation effects and
variability. Demonstrator production will be done at AMS fabrication.
Specifications:
– demonstrator test structures for PV aware and lifetime-critical circuits
– Technology: HV CMOS
o-o-o-
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Company/Contributor: IFAT
General target for IFAT: development and verification of monitor and control
strategies to compensate for degradation/aging effects and degradation/aging
induced process variations in analog, mixed-signal and RF circuits. Concept and
design aspects are covered in Task 3.3 whereas implementation
•
Specifications:
– Technology: 65nm and/or 32nm and/or 28nm low-power CMOS at foundries l
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
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WP5 T5.2 Review
Company/Contributor: TIEMPO
Tiempo work in WP5 starts in the second year of the project. However, all the work
planned during this first year in WP4 and which is a prerequisite for the second year
WP5 work is on schedule. TIEMPO will be using its innovative asynchronous design
technology to fabricate a prototype test vehicle of a significant complexity, for
example a microcontroller based system, in order to demonstrate the variability
tolerance and low noise/electromagnetic emission level that can be achieved
Specifications
– The targeted technology so far is 65nm or 45 nm.
•
Company/Contributor: LETI
•
From a « power aware » scheme to an « adaptive variation aware »
proposal for optimal PPY trade-off.:
•
Specification:
Technology is 32nm
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
8
WP5 T5.2 Review
• Company/Contributor: NXP
• Status/Plans:
– timing analysis (T3.2 to be confirmed)
– substrate noise (T3.4 to be confirmed)
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– -o–o–oCompany/Contributor: UPC
Status/plan: adaptive voltage scaling / regular design
– -o–o–o-
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
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•
WP5 T5.2 Review
Company/Contributor: THALES
– a) The specific work to be done in WP5 for our side is to check by simulation the
multiprocessing execution models in order to demonstrate the solutions developed in
WP4. Programming tools are also considered.
– b) The list of tools and models concerning the architecture level that we address
includes mainly the model of a fault-tolerant multiprocessing architecture. Models of
faults will be required to permit to take into consideration the technology. Technology
characteristics are therefore expected to build these models.
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
10
WP5 T5.3 Purpose and links
• Software demonstrator and tool prototype
• Links:
– THALES activities related to T4.3 and T4.5,
cooperation mainly within T4.3 (ISD)
Platform to be choose within WP4
– SYNOPSYS links to T2.2 activities
– STI links to WP2 activities
– NXP links to WP3 activities (T3.1)
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
11
•
WP5 T5.3 Review
Company/Contributor: THALES
– a) The specific work to be done in WP5 for our side is to check by simulation the
multiprocessing execution models in order to demonstrate the solutions developed in
WP4, including programming tools.
– b) Tools will be developed to take into account reliability requirements in the design
space exploration on the multiprocessing platform.
– c) The objective of the demonstration platform is to enhance the reliability of
processing solution used for critical systems. These systems indeed require
predictable behaviors and performance guarantees. The process variations will
cause some malfunctions (degraded performances, out-of-service element, etc) in
processing nodes and in communication network. The platform definition aims at
improving the reliability in spite of these malfunctions.
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
12
WP5 T5.3 Review
• Company/Contributor: NXP
• Status/Plans:
– MOR [parameterized Model Order Reduction (MOR) methods that
preserve accuracy and stability (passivity) for large linear R, RC, RCL
systems and the effectiveness to reduce problem sizes of large Multiple
Input Multiple Output (MIMO) systems]
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– -o–o–oCompany/Contributor: STI
Status/plan: prototype PDK
– -o–o–oCompany/Contributor: SYNOPSYS
Status/plan: will provide prototype implementation of the new methods to
the partners focusing on the physical modeling of PV effects in the device
modeling tool (geometrical variation model) M24
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
13
WP5 ISSUES
• WP5 is strictly related to WP2/3/4
strengthening links with WPs possible deliverable
overlapping, proposal:
– in WP5 just description and result ‘list’
– spec in WP1, major results and analysis within related WPs
• Some Silicon issues: UPC, IMEP, LIRM founded for
45nm CMP silicon but IMEP/LIRM not in WP5
 need of coordination among WPs
(no change request [possible different funding for
demonstrators], some national reviewers pointed out that
that major companies should have demonstrators)
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
14
WP5 analysis
• Silicon con’t:
-some cluster of ‘self-consistent’
cooperative work and silicon also from
companies:
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AMS / TUG / TUW
NMX / UNET
STF / NMX
IFXA (foundries)
• First deliverables on M12
Project Review Meeting
Crolles, June 22-23, 2009
23/05/2017
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