Download ENGG 3640: Microcomputer Interfacing

ENG3640
Microcomputer Interfacing
Week #1
Review of Transistors
Topics






Semiconductors
PN Junction (Diodes)
Bi-Polar Junction Transistors (BJTs)
MOS Transistors (nMOS/pMOS)
CMOS Technology
Interfacing TTL with CMOS
ENG3640 Fall 2012
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Semiconductor Materials
Electronic materials generally can be divided
into three categories:




The primary parameter used to distinguish
among these materials is the resistivity (rho)





Insulators
Semiconductors
Conductors
Insulator
105 < rho
Semiconductors 10-3 < rho < 105
Conductors
rho < 10-3
Silicon and germanium are the most important
semiconductor materials
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P-type and N-type
The real advantage of semiconductors emerge
when impurities are added to the material in minute
amounts (Doping)
Impurity doping enables us to change the
resistivity over a very wide range and determine
whether the electron or hole population controls
the resistivity of the material.



Donor Impurities: have five valence electrons in the outer
shell (phosphorus and arsenic). Semiconductors doped
with donor impurities are called n-type.

Acceptor Impurities: have one less electron than silicon in
the outer shell (boron). Semiconductors doped with
acceptor impurities are called p-type.
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Diodes: PN Junction
The diode is the simplest
and most fundamental
nonlinear circuit element.
Diffusion of majority
carriers into the opposite
sides causes a depletion
region to appear at the
junction.
The diode essentially allows
an electric current to flow in
one direction and locks it in
the other direction
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Diodes
i = IS(e (v/nVT) - 1)
i = -IS
IS = Saturation Current
VT = Thermal Voltage
v = Terminal voltage
n = Constant (1)
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Diodes: Applications
Half-wave Rectifier with resistive load.
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Transistors: MOSFET vs. BJT
drain
collector
NPN bipolar transistor
N-channel MOSFET
body
base
gate
emitter
source
Uni-Polar Junction Transistor
Bi-Polar Junction Transistor
Voltage Controlled Switch
Current Controlled Switch
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History of Transistors



1940: Ohl develops the PN Junction
1945: Shockley's laboratory established
1947: Bardeen and Brattain create point
contact transistor (U.S. Patent 2,524,035)
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BJT Symbols
collector
base
collector
base
emitter
NPN Bipolar Transistor
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emitter
PNP Bipolar Transistor
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Bipolar Junction Transistor
1. Acts like a current
controlled switch.
2. If we put a small
current into the base
then the switch is on
(i.e. current may flow
between collector and
emitter)
3. If no current is put into
the base, switch is off.
4. Regions of operations
• Cutoff
• Active
• Saturation
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BJT Modes of Operation
Mode
EBJ
CBJ
cutoff
Reverse
Reverse
Active
Forward
Reverse
Saturation
Forward
Forward
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BJT: Bipolar Junction
Transistor
 A current controlled device
Two types: NPN and PNP
 Handles more current than MOSFETs (Faster)
 More difficult to manufacture
 Dissipates more power
 Achieves less density on an IC
 Does not have full swing voltage
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The MOS Transistor
Metal Oxide Semiconductor
Polysilicon
Aluminum
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MOS: Operation
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
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nMOS vs. pMOS Devices
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MOSFET: Metal Oxide
Semiconductor
Field Effect Transistor
 A voltage controlled device
Two types: NMOS and PMOS
 Handles less current than a BJT (Slower)
 Easier to manufacture
 Dissipates less power
 Achieves higher density on an IC
 Has full swing voltage 0  5V
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VLSI Trends: Moore’s Law

In 1965, Gordon Moore predicted that
transistors would continue to shrink, allowing:




Doubled transistor density every 18-24 months
Doubled performance every 18-24 months
History has proven Moore right
But, is the end is in sight?


Physical limitations
Economic limitations
Gordon Moore
Intel Co-Founder and Chairmain Emeritus
Image source: Intel Corporation www.intel.com
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Technology Evolution
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NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
Transistors
pass aa “strong”
0 but0abut
“weak”
1
NMOSNMOS
Transistors
pass
``strong”
a ``weak”
1
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PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
Transistors
passaa ``strong”
“strong” 1 but
a “weak”
0
PMOSPMOS
Transistors
pass
1 but
a ``weak”
0
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Complementary MOS (CMOS)
 NMOS Transistors pass a ``strong” 0 but a ``weak” 1
 PMOS Transistors pass a ``strong” 1 but a ``weak” 0
 Combining both would lead to circuits that can pass
strong 0’s and strong 1’s
C
Y
X
C
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Static Complementary CMOS
VDD
In1
In2
PUN and PDN are dual logic networks
PMOS only
PUN
InN
In1
In2
InN
F(In1,In2,…InN)
PDN
NMOS only
VSS
 At every point in time (except during the switching transients)
each gate output is connected to either VDD or VSS via a low
resistive path
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CMOS Inverter
Pull-up
Network
A
0
1
VDD
Y
A
A
Y
Y
GND
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Pull-down
Network
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CMOS Inverter
A
0
1
VDD
Y
OFF
0
A=1
Y=0
ON
A
Y
GND
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CMOS Inverter
A
0
1
VDD
Y
1
0
ON
A=0
Y=1
OFF
A
Y
GND
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Types of Outputs

1.
2.
3.
There are different types of outputs associated with
digital circuits
Totem Pole (normal output)
Tri-state (High, Low, High Impedance)
Open Collector or Open Drain
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1. Totem Pole (normal output)





Simply refers to the vertical
alignment of components
Q1, Q2 act as switches
controlled by Input A
When One transistor is on
the other is off
Q1 is pull-up, Q2 is pull-down
Not possible to join totem
pole outputs together.
A
Pull-up
Network
VDD
A
Y
Y
GND
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Pull-down
Network
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2. Tri-State Output

Tri-state gates enable a device to electrically
disconnect its output when it is not driving the bus.
E
0
1
1
A
X
0
1
Y
Z
1
0
A
A
E
Y
Y
E
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3. Open Collector



As with tri-state output, open collector outputs allow multiple
logic devices to drive the same line.
Since the pull-up transistor is missing, the circuit has the
capability of pulling the signal down.
To pull a signal up we need an EXTERNAL RESISTOR (passive
pull-up to high level)
Low to high transitions
are much slower for
open drain gate than for
standard gate with
active pull-up
*
Pull-down
Network
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Open Collector: IRQ

Most common use of open collector is to connect several
devices to a common interrupt line.
+5V
I/O Device A
*
I/O Device B
*
IRQ
MCU
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Logic Families


RTL, DTL earliest
TTL was used 70s, 80s



CMOS



Still available and used occasionally
7400 series logic, refined over generations
Was low speed, low noise
Now fast and is most common
BiCMOS and GaAs

Speed
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Resistor-Transistor Logic (RTL)
Vcc
Vou t
RC
Vo ut
RB
Vin
VCC
Q1
VTC of nonsaturating gate
VC E(sa t)
V B E(o n)
V i n(e o s)
Cutoff
Vin
Saturation
Forward-active
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TTL (Transistor-Transistor)
Q1
In
Q2
In
Q1
Q2
Out
0
ON
OFF
1
1
Off
ON
0
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CMOS/TTL Interfacing
Several factors to consider
1. Noise Margin
CMOS (VOL = 0, VOH = 5V)
TTL (VIL = 0.4 V, VIH = 2.4V)
CMOS
TTL
No problem for CMOS to drive TTL since
CMOS has full swing output
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CMOS/TTL Interfacing
TTL (VOL = 0.7 V, VOH = 3.3V)
CMOS (VIL = 2.3, VIH = 3.3V)
TTL
CMOS
1. We do have a problem when TTL drives CMOS.
2. TTL driving HC (high speed CMOS) doesn’t work unless the TTL high
output happens to be higher and the CMOS high input threshold
happens to be lower by a total of 1V.
3. To drive CMOS inputs properly from TTL outputs, the CMOS
device should be TTL compatible (i.e. use HCT, VHCT, FCT)
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CMOS/TTL Interfacing
Other factors to consider
(2) Fan-out: defined as Min( IOH/IIH, IOL/IIL)
We would encounter problems when CMOS drives
TTL since CMOS has limited driving current.
CMOS
TTL
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CMOS/TTL Interfacing
 CMOS has very high input impedance so almost
no current is required in either state!
 So TTL can drive CMOS with no problems if we
are considering fan-out (up to 15 gates)
TTL
CMOS
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History of MOS Transistors


1961: TI and Fairchild introduce the first logic ICs ($50 in
quantity)
1962: RCA develops the first MOS transistor
Fairchild bipolar RTL Flip-Flop
ENG3640 Fall 2012
RCA 16-transistor MOSFET IC
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Bell Labs

1951: Shockley develops a junction
transistor manufacturable in quantity (U.S.
Patent 2,623,105)
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BJT Operating Regions
For different
values of VBE
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BJT in Cutoff Region
VBB is smaller than 0.5V
Under this condition iB= 0
As a result iC becomes negligibly
small
Both base-emitter as well basecollector junctions may be reverse
biased
Under this condition the BJT can be
treated as an off switch
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BJT in Active Region
VBB is above 0.5V around 0.7V
Under this condition
iB= (VBB – VBE)/RBB
As a result iC =  IB
 EBJ is forward
 CBJ is reverse
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BJT in Saturation Region
 Both base emitter as well as base collector junctions
are forward biased.
 VCE  0.2 V
 Under this condition the BJT can be treated as an on
switch
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BJT in Saturation Region
 A BJT can enter saturation in the following ways:
1. For a particular value of iB, if we keep on increasing RCC
2. For a particular value of RCC, if we keep on increasing iB
3. For a particular value of iB, if we replace the transistor
with one with higher 
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BJT: Active Region Bias
Current flow in an NPN transistor biased to operate in the active mode.
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NPN BJT Current flow
IE = IC +IB
?
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BJT ( and )
 From the previous figure iE = iB + iC
 Define  = iC / iE = 0.99
 Define  = iC / iB = 100
 Then  = iC / (iE –iC) =  /(1- )
 Then iC =  iE ; iB = (1-) iE
 Typically   100 for small signal BJTs (BJTs that
handle low power) operating in active region (region
where BJTs work as amplifiers)
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(1) Totem Pole, BJT
Simply refers to the vertical alignment of components
Q1, Q2 act as switches controlled by In
When One transistor is on the other is off
Q1 is pull-up, Q2 is pull-down
Not possible to join totem pole outputs together.





In
In
Q1
Q2
Out
0
ON
OFF
1
1
Off
ON
0
Q1
Q2
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(2) Tri-State Output



When interfacing to a bus we need to connect logic gates
together.
Tri-state gates enable a device to electrically disconnect its
output when it is not driving the bus.
By adding diodes to the previous totem-pole configuration we
can disable both Q1,Q2 and achieve high impedance
In
E
In
Q1
Q2
1 0
ON
OFF
1
1 1
OFF
ON
0
0 X
OFF OFF
Z
Q1
Out
Q2
E
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(3) Open Collector



As with tri-state output, open collector outputs allow multiple
logic devices to drive the same line.
Since the pull-up transistor is missing, the circuit has the
capability of pulling the signal down.
To pull a signal up we need an EXTERNAL RESISTOR (passive
pull-up to high level)
Low to high transitions
are much slower for
open drain gate than for
standard gate with
active pull-up
*
Symbols
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MOSFET Symbols
A circle is sometimes
used on the gate terminal
to show active low input
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MOSFET Operating Regions

Strong Inversion VGS > VT



Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS  VDSAT
Weak Inversion (Sub-Threshold) VGS  VT

Exponential in VGS with linear VDS dependence
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Threshold Voltage: Concept
+
S
VGS
D
G
-
n+
n+
Depletion
Region
n-channel
p-substrate
B
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Transistor in Saturation
VGS
VDS > VGS - VT
G
D
S
n+
-
VGS - VT
+
n+
Pinch-off
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Complementary CMOS Logic Style
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CMOS NAND Gate
A
0
0
1
1
B
0
1
0
1
Y = A.B
Y
Y
A
B
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CMOS NAND Gate
A
0
0
1
1
B
0
1
0
1
Y
1
Y = A.B
ON
ON
Y=1
A=0
B=0
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OFF
OFF
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CMOS NAND Gate
A
0
0
1
1
B
0
1
0
1
Y
1
1
Y = A.B
OFF
ON
Y=1
A=0
B=1
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OFF
ON
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CMOS NAND Gate
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
Y = A.B
ON
OFF
Y=1
A=1
B=0
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ON
OFF
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CMOS NAND Gate
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
OFF
A=1
B=1
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OFF
Y=0
ON
ON
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Example Gate: NOR
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Complex CMOS Gate
B
A
C
D
OUT = D + (A • (B + C))
A
D
B
C
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Open Collector: Driving a Bus

Open-drain outputs can be tied together to allow several
devices (one at a time) to put information on a common bus.
+5V
Data Out
D1
D3
D5
D7
E1
E3
E5
E7
D2
D4
D6
D8
E2
E4
E6
E8
At most one ``Enable Bit” is high at any time enabling the
corresponding data bit to be passed through the bus
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