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Impact of Interconnect
 Interconnection
 Fundamental limitation of Digital
Technology at all scales
 Classes of parasitics:
– Capacitive
– Resistive
– Inductive (Impact usually package/board level)
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Interconnect Impact on Chip
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Nature of Interconnect
No of nets
(Log Scale)
Local Interconnect
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Global Interconnect
SGlobal = SDie
Source: Intel
SLocal = STechnology
10
100
1,000
10,000
100,000
Length (u)
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INTERCONNECT
Capacitance
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Capacitance of Wire Interconnect
VDD
VDD
M2
Vin
Cg4
Cdb2
Cgd12
M4
Vout
Cdb1
Cw
M1
Vout2
Cg3
M3
Interconnect
Fanout
Simplified
Model
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Vin
Vout
CL
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Capacitance: The Parallel Plate Model
Current flow
L
Electrical-field lines
W
H
tdi
Dielectric
Substrate
cint 
 di
t di
WL
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S Cwire 
S
1

S  SL SL
Inverter
Permittivity
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Fringing Capacitance
(a)
H
W - H/2
+
(b)
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Fringing versus Parallel Plate
(from [Bakoglu89])
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Interwire Capacitance
fringing
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parallel
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Impact of Interwire Capacitance
(from [Bakoglu89])
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Wiring Capacitances (0.5 mm CMOS)
Layer
N+
P+
Poly
Poly2
M1
M2
M3
Sub
420
730
87
--
32
16
10
aF/mm2
Ndif
2450
aF/mm2
Pdif
2360
aF/mm2
Poly
860
Poly2
57
16
31
M2
310
250
Poly(fr)
M1(fr)
M2(fr)
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aF/mm2
aF/mm2
52
M1
Sub(fr)
9
13
aF/mm2
32
aF/mm2
76
59
39
aF/mm
61
38
28
aF/mm
51
33
aF/mm
52
aF/mm
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INTERCONNECT
Resistance
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Wire Resistance
R= L
HW
Sheet Resistance
Ro
L
H
R1
W
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R2
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Interconnect Resistance
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Polycide Gate MOSFET
Silicide
PolySilicon
SiO2
n+
n+
p
Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi
Conductivity: 8-10 times better than Poly
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Sheet Resistance
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Example: Intel 0.25 micron Process
5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric
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Interconnect
Modeling
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The Lumped Model
Vo ut
cwi re
Driver
Rdriver
V
out
Vin
Clumped
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The Lumped RC-Model
The Elmore Delay
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The Ellmore Delay
RC Chain
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Wire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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The Distributed RC-line
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Step-response of RC wire as a
function of time and space
2.5
x= L/10
2
voltage (V)
x = L/4
1.5
x = L/2
1
x= L
0.5
0
0
0.5
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1
1.5
2
2.5
3
time (nsec)
3.5
4
4.5
5
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RC-Models
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Driving an RC-line
Rs
(r w,cw,L)
Vout
V
in
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Design Rules of Thumb
rc delays should only be considered when
tpRC >> tpgate of the driving gate
Lcrit >>  tpgate/0.38rc
 rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
trise < RC

 when not met, the change in the signal is slower
than the propagation delay of the wire
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© MJIrwin, PSU, 2000
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Homework 4
1.
2.
For the AMIS 0.5um technology, create an equivalent RC/Elmore SUE model
using the Mosis parametric test results (amis05.txt from web site). This model
should include the effective gate capacitance, source and drain parasitic
junction capacitances and equivalent resistance for NMOS and PMOS,
L=0.5um as a function of W in um. Use this model to estimate the sizes of the
transistors in the ring oscillator test for the standard and wide case from the
given performance data. (Do this carefully, this is a useful model!!)
Rabaey Chap. 4 on-line problems: 1, 4, 7, 12
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