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COPING WITH INTERCONNECT Digital Integrated Circuits Interconnect © Prentice Hall 1995 Impact of Interconnect Parasitics • Reduce Reliability • Affect Performance Classes of Parasitics • Capacitive • Resistive • Inductive Digital Integrated Circuits Interconnect © Prentice Hall 1995 Nature of Interconnect Local Interconnect Global Interconnect SLocal = STechnology SGlobal = SDie Digital Integrated Circuits Interconnect © Prentice Hall 1995 INTERCONNECT Dealing with Capacitance Digital Integrated Circuits Interconnect © Prentice Hall 1995 Capacitance: The Parallel Plate Model L W H tox SiO2 Substrate Digital Integrated Circuits Interconnect © Prentice Hall 1995 Typical Wiring Capacitance Values Digital Integrated Circuits Interconnect © Prentice Hall 1995 Fringing Capacitance (a) H W - H/2 + (b) Digital Integrated Circuits Interconnect © Prentice Hall 1995 Fringing Capacitance: Values Digital Integrated Circuits Interconnect © Prentice Hall 1995 How to counter Clock Skew? (from [Bakoglu89]) Digital Integrated Circuits Interconnect © Prentice Hall 1995 Interwire Capacitance Level2 Insulator Level1 SiO2 Substrate Creates Cross-talk Digital Integrated Circuits Interconnect © Prentice Hall 1995 Interwire Capacitance Digital Integrated Circuits Interconnect © Prentice Hall 1995 Impact of Interwire Capacitance (from [Bakoglu89]) Digital Integrated Circuits Interconnect © Prentice Hall 1995 Capacitance Crosstalk VDD CXY X CX In1 Y PDN In2 5V In3 OV 5x5 m Overlap: 0.35 V Interference Digital Integrated Circuits Interconnect © Prentice Hall 1995 How to Battle Capacitive Crosstalk • Avoid parallel wires • Shielding Shielding wire GND VDD Shielding layer GND Substrate (GND) Digital Integrated Circuits Interconnect © Prentice Hall 1995 Driving Large Capacitances tpHL = CL Vswing/2 Iav VDD Vin Vout CL Digital Integrated Circuits Interconnect Transistor Sizing © Prentice Hall 1995 Using Cascaded Buffers In Out Ci u2 u 1 C1 u N-1 C2 CL uopt = e Digital Integrated Circuits Interconnect © Prentice Hall 1995 tp in function of u and x u/ln(u) 60.0 40.0 x=10,000 x=1000 20.0 x=100 x=10 0.0 1.0 3.0 5.0 7.0 u Digital Integrated Circuits Interconnect © Prentice Hall 1995 Impact of Cascading Buffers Digital Integrated Circuits Interconnect © Prentice Hall 1995 Output Driver Design Digital Integrated Circuits Interconnect © Prentice Hall 1995 How to Design Large Transistors D(rain) S Multiple Contacts D G S(ource) S G(ate) (a) small transistors in parallel Digital Integrated Circuits Interconnect (b) circular transistors © Prentice Hall 1995 Bonding Pad Design Bonding Pad GND 100 m Out VDD Digital Integrated Circuits In GND Interconnect Out © Prentice Hall 1995 Reducing the swing tpHL = CL Vswing/2 Iav • Reducing the swing potentially yields linear reduction in delay • Also results in reduction in power dissipation • Requires use of “sense amplifier” to restore signal level Digital Integrated Circuits Interconnect © Prentice Hall 1995 Charge Redistribution Amplifier 5.0 VA VB M1 M2 M3 CA CB 4.0 2.0 (a) 1.0 0.0 0.0 Digital Integrated Circuits VB Vin 3.0 V Vref Interconnect VA Vref = 3V 1.00 2.00 time (nsec) 3.00 © Prentice Hall 1995 Precharged Bus VDD f In1.f VDD M2 M1 M4 Bus In2.f Cbus Out M3 Cout f 5.0 Vsym V 3.0 Vasym Vbus 1.0 Cbus =1pF -1.0 Digital Integrated Circuits 0 5 t (nsec) Interconnect 10 © Prentice Hall 1995 Tristate Buffers VDD VD D En En Out Out In En Digital Integrated Circuits In Interconnect En © Prentice Hall 1995 Using Bipolar Versus MOS But: Bipolar does not scale well with voltage! Digital Integrated Circuits Interconnect © Prentice Hall 1995 Bipolar Versus MOS (cont.) 5.0 Vin Vout (bipolar) Vout 4.0 3.0 2.0 Vout (mos) 1.0 0.0 0 5 10 t (nsec) 15 20 Driving a 10 pF Capacitance using Emitter(Source)-Followers Digital Integrated Circuits Interconnect © Prentice Hall 1995 INTERCONNECT Dealing with Resistance Digital Integrated Circuits Interconnect © Prentice Hall 1995 Wire Resistance R= L HW Sheet Resistance Ro L H R1 W Digital Integrated Circuits Interconnect R2 © Prentice Hall 1995 Interconnect Resistance Digital Integrated Circuits Interconnect © Prentice Hall 1995 Dealing with Resistance • Selective Technology Scaling • Use Better Interconnect Materials e.g. silicides, bypasses • More Interconnect Layers reduce average wire-length Digital Integrated Circuits Interconnect © Prentice Hall 1995 Polycide Gate Mosfet Silicide PolySilicon SiO 2 n+ n+ p Silicides: WSi2, TiSi 2, PtSi2 and TaSi Conductivity: 8-10 times better than Poly Digital Integrated Circuits Interconnect © Prentice Hall 1995 Modern Interconnect Digital Integrated Circuits Interconnect © Prentice Hall 1995 RI Introduced Noise I VDD R’ pre VDD - V’ X I V V R Digital Integrated Circuits Interconnect © Prentice Hall 1995 Power and Ground Distribution GND VDD Logic Logic VDD VDD GND GND (a) Finger-shaped network Digital Integrated Circuits (b) Network with multiple supply pins Interconnect © Prentice Hall 1995 Electromigration (1) Limits dc-current to 1 mA/m Digital Integrated Circuits Interconnect © Prentice Hall 1995 Electromigration (2) Digital Integrated Circuits Interconnect © Prentice Hall 1995 RC-Delay Digital Integrated Circuits Interconnect © Prentice Hall 1995 RC-Models Digital Integrated Circuits Interconnect © Prentice Hall 1995 Reducing RC-delay Repeater Digital Integrated Circuits Interconnect © Prentice Hall 1995 The Ellmore Delay Digital Integrated Circuits Interconnect © Prentice Hall 1995 Penfield-Rubinstein-Horowitz Digital Integrated Circuits Interconnect © Prentice Hall 1995 INTERCONNECT Dealing with Inductance Digital Integrated Circuits Interconnect © Prentice Hall 1995 Inductive Effects in Integrated Circuits Coaxial Cable Digital Integrated Circuits Triplate Strip Line MicroStrip Interconnect Wire above Ground Plane © Prentice Hall 1995 L di/dt V DD L Vin i(t) Vout CL L Digital Integrated Circuits Interconnect © Prentice Hall 1995 L di/dt: Simulation 5.0 vout 4.0 5V Vout(V) t 3.0 tfall = 4 nsec 2.0 tfall = 0.5 nsec 1.0 0.0 40mA 20mA t 20 IL (mA) iL 10 0 0.5 vL t VL (V) 0.2V 0.3 0.1 -0.1 -0.3 2 4 6 t (nsec) 8 10 Signals Waveforms for Output Driver connected To Bonding Pads (a) vout; (b) i L and (c) v L. The Results of an Actual Simulation are Shown on the Right Side. Digital Integrated Circuits Interconnect © Prentice Hall 1995 Choosing the Right Pin Bonding Wire Chip L Mounting Cavity L’ Lead Frame Pin Make Rise- and Fall Times as slow as possible Digital Integrated Circuits Interconnect © Prentice Hall 1995 Decoupling Capacitors + Bonding Wire Board Wiring SUPPLY Cd CHIP Decoupling Capacitor Digital Integrated Circuits Interconnect © Prentice Hall 1995 The Transmission Line r r l r l r l Vin x g Digital Integrated Circuits l c g c Interconnect g c Vout g c © Prentice Hall 1995 Lossless Transmission Line Parameters speed of light in vacuum Digital Integrated Circuits Interconnect © Prentice Hall 1995 Wave Propagation Speed Digital Integrated Circuits Interconnect © Prentice Hall 1995 Wave Reflection for Different Terminations Digital Integrated Circuits Interconnect © Prentice Hall 1995 Transmission Line Response (RL= ) 5.0 4.0 VDest VSource V 3.0 2.0 RS = 5Z0 1.0 (a) 0.0 4.0 V 3.0 2.0 1.0 RS = Z0 (b) 0.0 8.0 V 6.0 4.0 2.0 0.00.0 Digital Integrated Circuits RS = Z0 /5 5.0 t (in t lightf) Interconnect 10.0 (c) 15.0 © Prentice Hall 1995 Lattice Diagram VSource VDest 0.8333 V + 0.8333 1.6666 V + 0.8333 2.2222 V + 0.5556 2.7778 V + 0.5556 t + 0.3704 3.1482 V 3.5186 V + 0.3704 3.7655 V + 0.2469 4.0124 V + 0.2469 ... L/ Digital Integrated Circuits Interconnect © Prentice Hall 1995 ECL Gate Line Response Vcc Vc c RC Vcc Vcc RC RC L=2cm Vin Vref RB Z0= 100 RB I EE V EE IEE V EE VEE (a) -0.5 10k Vout -1.0 100 -1.5 -2.00 Digital Integrated Circuits 0.5 1.0 t (nsec) Interconnect 1.5 2.00 © Prentice Hall 1995 Output Buffer Model VDD Clamping L = 10nH 20 106 562 8 43 224 Vin Diodes VDD 1500 L = 5nH 900 Z 0 = 100 C L= 5pF L = 10nH Digital Integrated Circuits CL Vout RL (a) Interconnect © Prentice Hall 1995 Output Buffer - Response 10.0 Clamped Vout 5.0 CL = 5pF RL = 10k Vin Unclamped 0.0 -5.0 CL = 5pF RL = 100 Vout 4.0 (b) 2.0 0.0 -2.0 CL = 25pF RL = 100 Vout 4.0 2.0 0.0 -2.0 Digital Integrated Circuits 0 20 t (nsec) Interconnect 40 60 © Prentice Hall 1995 When to Consider Transmission Line Effects? Digital Integrated Circuits Interconnect © Prentice Hall 1995 Packaging Requirements • Electrical: Low parasitics • Mechanical: Reliable and Robust • Thermal: Efficient Heat Removal • Economical: Cheap Digital Integrated Circuits Interconnect © Prentice Hall 1995 Bonding Techniques Wire Bonding Substrate Die Pad Lead Frame Digital Integrated Circuits Interconnect © Prentice Hall 1995 Tape-Automated Bonding (TAB) Sprocket hole Film + Pattern Solder Bump Die Test pads Lead frame Substrate (b) Die attachment using solder bumps. Polymer film (a) Polymer Tape with imprinted wiring pattern. Digital Integrated Circuits Interconnect © Prentice Hall 1995 Flip-Chip Bonding Die Solder bumps Interconnect layers Substrate Digital Integrated Circuits Interconnect © Prentice Hall 1995 Package-to-Board Interconnect (a) Through-Hole Mounting Digital Integrated Circuits (b) Surface Mount Interconnect © Prentice Hall 1995 Package Types Digital Integrated Circuits Interconnect © Prentice Hall 1995 Package Parameters Digital Integrated Circuits Interconnect © Prentice Hall 1995 Multi-Chip Modules Digital Integrated Circuits Interconnect © Prentice Hall 1995
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