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Challenges and Opportunities for System SW in the CMP Era Chuck Moore AMD Senior Fellow June 2007 WIOSCA Workshop Panel Unexpected lessons learned during the past decade Strength of the compatibility requirement Change occurs much more slowly than people want to believe x86 & IBM S/390 longevity have lapped most RISC architectures Our history shows: Viable products don’t bet on wildly incompatible solutions Actual results weakest link in the HW/SW symbiotic relationship The economic realities of our industry can be painful The best technology rarely wins Simplicity usually trumps complexity Time-to-Market Power issues emerged as the one of the most limiting constraints of modern chip design 06/09/07 WIOSCA Panel - ISCA 2007 2 Some Specific Challenges Dealing w/ the implicit serial “structural compatibility” requirement of most of today’s applications Optimization balance between single-thread performance and throughput performance Building reliable platforms from increasingly unreliable technology Control mechanisms to appropriately manage non-traditional resources 06/09/07 Power, Heat, Maintenance, Errors, and more coming … WIOSCA Panel - ISCA 2007 3 Some Specific Opportunities System-level ISA Coprocessor enablement “It’s the synchronization, stupid ” Abstraction and compatibility Think page ops, table lookups, transforms, etc Envision the “7-layer ISO model for computing ” Scarcity versus abundance 06/09/07 Abundant: Scarce: transistors, designers, raw FLOPs pwr-eff, bw-eff, TTM, flexibility, programmer productivity WIOSCA Panel - ISCA 2007 4