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6332 VLSI Project Proposal
The Study of Strained Silicon Transistors for High-Performance Low-Power
Logical Circuits Applications
Jinrong Yuan
Huihui Wang
10.14.2010
1.
Introduction
PMOS/NMOS transistor structure which features a strained silicon epitaxy-layer
grown on relaxed SiGe film can greatly improve charge carrier mobility and is
utilized to achieve high speed channel and dramatic performance enhancement. To
maintain high speed with low power near threshold operation critically challenged the
state of the art circuit design methodologies pertain to ITRS (International
Technology Roadmap for Semiconductors) requirements [1].
The strained silicon to improve mobility instead of the conventional Si has been
recognized as an important technology for meeting the ITRS criterion [2-5].
Compared to traditional unstrained devices, the strained silicon transistors have higher
IDS with lower VT, so it’s a better current drive source. However, the high leakage
current (low performance) of the s-Si due to its inherent property (like lower VT), is a
trade-off of the high speed circuits. Hence, the logical circuit designs such as
optimizing strained and unstrained transistors as well as the stack ones distributed in
the logic circuits will be an interesting technology, considering the high performance
and low power.
In this project work, we will try to look into
1) The performance of separate strained NMOS/PMOS devices, properties like IDS
vs VGS, with different strain parameters;
2) Delay comparison of the inverters with conventional Si and s-Si transistors;
3) Delay comparisons of the no-stack and stacked inverters with s-Si;
4) Supply voltage effects on the delay comparison of both conventional Si and s-Si
inverters;
5) Leakage current of both stacked and no-stack inverters;
6) Optimizations of the supply voltage, the strained silicon and stacked Si for a
register considering the delay and leakage current.
2. Initial Simulation Results
At the beginning of the work, we finished first two tasks mentioned above. We
started with studying the strained silicon effects on the electrical properties such as
current (Id) and voltage (Vgs). Then we simulated the transistors with the strained
silicon effects on the gate delay of the inverters which is the basic circuit for further
work. The following results are based on the BPTM [6] and simulated in Ocean. The
Fig. 2.1 and Fig.2.2 show that the threshold voltage decreases with the increasing
strain for both PMOS and NMOS due to the increasing charge carrier mobility. Fig
2.3-2.5 show that the gate delay is reduced with the increasing strain in PMOS,
NMOS only and both PMOS and NMOS for C=50pF.
In addition, some interesting phenomenon is found during the simulation. For
example, the delay of PMOS (tpLH) will increase if we just increase the strain of the
NMOS. Right now we have no legitimate answer to this. Meanwhile, the output
voltage will decrease with increase strain in NMOS. The possible reason is the
increasing leakage current causes larger voltage change from VDD via PMOS.
3. Future work
Based on the results we have so far, it’s worth looking into those possible designs
to optimize a certain circuit with strained silicon devices.
A 6T SRAM or a register might be the next step goal to see thoroughly how the
strained devices contribute to the leakage current and what is the best way to optimize
the circuit with the combination of strained and unstrained transistors, such as using
stack design to reduce leakage in proper positions. It might also be interesting to see
how the different strain affects the speed and the leakage current at the same time thus
to adjust different transistors to achieve the best performance and the highest speed of
the circuit.
Fig. 2.1 PMOS with different strain1-5 low to
high
Fig. 2.2 NMOS with different strain1-5 low
to high
Fig 2.3 Changing strain in PMOS only effect
on the gate delay
Fig 2.4 Changing strain in NMOS only effect
on the gate delay
Fig. 2.5 Strain changing in both PMOS and
NMOS effects on the gate delay
4. Work distribution and Time Table
Task People
1
10.14
2
10.14
3
11.4
4
11.4
5
11.4
6
11.30
NMOS (Jinrong)
PMOS (Huihui)
Delay of inverter with s-Si in NMOS only (Jinrong)
Delay of inverter with s-Si in NMOS and PMOS (Huihui)
Delay of s-Si inverter with stack (Jinrong)
Delay of s-Si inverter without stack (Huihui)
Leakage current of stacked s-Si inverters (Huihui)
Leakage current of no-stack s-Si inverters (Jinrong)
Supply voltage effects on the delay of conventional Si inverters (Jinrong)
Supply voltage effects on the delay of s-Si inverters (Huihui)
Huihui (Delay)
Jinrong (Power)
5. References
[1] International Technology Roadmap for Semiconductors, http://www.itrs.net/.
[2] H. Ramakrishnan, S. Shedabale, G. Russell, and A. Yakovlev, ‘Stacked Strained Silicon Transistors for
Low-power High-performance Circuit Applications’, 2008 Electronic Components and Technology
Conference.
[3] C.-H. Jan, P. Bai, J. Choi, G. Curello, S. Jacobs, J. Jeong, K. Johnson, D. Jones, S. Klopcic, J. Lin, N.
Lindert, A. Lio, ‘A 65nm Ultra Low Power Logic Platform Technology using Uni-axial Strained Silicon
Transistors’, 2005 IEEE.
[4] S.G. Badcock, A.G. O’Neill, E.G. Chester, ‘Device and circuit performance of SiGe/Si MOSFETs’,
Solid-State Electronics 46 (2002) 1925–1932.
[5] Mark Bohr, ‘The Invention of Uniaxial Strained Silicon Transistors at Intel’, Intel Corporation.
[6] Berkeley Predictive Technology Model (BPTM) “45nm BSIM 3 model cards”.