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6332 VLSI Project Review
Huihui Wang
Jinrong Yuan
10.05.2010
1. Introduction
Starting with 90 nm technologies the performance enhancements of
CMOS started to diminish through standard device scaling such as
shrinking the gate length and thinning the gate oxide due to several
physical limitations in miniaturization of MOSFETs. Thus, new channel
structures and materials, which mitigate the stringent constraints
regarding the device design, have recently stirred a strong interest. These
so-called Technology Boosters [1] include strained silicon channels,
ultrathin SOI, metal gate electrodes, multigate structures, ballistic
transport channels, as well as others. Strained silicon channels have been
recognized as an important technology to improve the mobility [2-4].
2. Paper Review
Two types of strains, the biaxial and uniaxial strained silicon have
advantages and disadvantages considering the mobility gain, fabrication
complexity and cost [2].
For Fabrication, several methods are used to realize the strained
silicon. A common technique is to grow strained silicon on relaxed
SixGe1–x. However, this method introduces a lower bandgap material
(SixGe1–x) into the body of the MOSFET, which requires additional care
to avoid punch-through [3]. One novel structure to induce uniaxial strain
is the Epitaxial Source/Drain (ESD) transistor. After formation of the gate
stack, S/D extensions and spacer, a silicon recess etch is performed. Then,
selective heteroepitaxy is used to grow a strained material in the S/D
regions [2]. Also a different approach, proposed by Intel [7], is to
introduce SixGe1–x pockets into the source and drain of the PMOS
device. These pockets create compressive stresses in the channel area.
The NMOS device was fabricated using a standard NMOS process flow
but, at the end of the process flow, a highly tensile silicon-nitride cap
layer was deposited, which covered the source, drain, and gate stack [6].
For electrical properties, the different relationships of drain current
(Ids), source-drain voltage (Vds), gate-source voltage (Vgs) and
body-source voltage (Vbs) are studied with different mobility gain and
body effect with BPTM (Berkeley Predictive Technology Model) [5].
Research shows that the mobility of the strained silicon devices is ~70%
higher than the universal MOSFET mobility and lower threshold voltage
[8]. Also, the delay of 90nm CMOS device is studied as 5.5ps [2]. In
addition, the strained silicon of 45nm device in the memory and logic are
both optimized [5].
3. Simulation Results
The results are obtained by using the BPTM models in HSPICE. Now,
we just do some practice for PMOS and NMOS.
Fig. 3.1 Id v.s. Vds of PMOS for different Vgs
Fig. 3.2 Id v.s. Vgs of PMOS for different Vbs
Fig 3.3 Ids v.s. Vds for different Vgs
Fig 3.4 Ids v.s. Vds with/without the body effect
4. Further work
This paper reviews the strained silicon influences on CMOS in term
of the different strain types, fabrication processes and electrical properties.
Based on the connection with the course, we plan to focus on the strain
types like uniaxial and biaxial strain influences on different current and
voltage relationships for the device and circuits, how to reduce power
consumption, and how to improve the transient performance and other
electrical properties.
5．References
[1] International Technology Roadmap for Semiconductors, 2004 Edition, http://www.itrs.net.
[2] K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. and
ford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson and M. Bohr, ‘Delaying Forever:
Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology’, 2004 Symposium on VLSI
Technology Digest of Technical Papers.
[3] http://www.synopsys.com/Tools/TCAD/ProcessSimulation/Pages/SentaurusProcess.aspx.
[4] M. Reiche, O. Moutanabbir, J. Hoentschel , U. Gösele, S. Flachowsky and M. Horstmann,
Strained Silicon Devices’, Solid State Phenomena Vols. 156-158 (2010) pp 61-68 (2010) Trans
Tech Publications, Switzerland doi:10.4028/www.scientific.net/SSP.156-158.61.
[5] Rajani Kuchipudi and Hamid Mahmoodi, ‘Strain Silicon Optimization for Memory and
Logic in Nano-Scale CMOS’, Proceedings of the 8th International Symposium on Quality
Electronic Design (ISQED'07).
[6] Raghvendra S. Saxena and M. Jagadesh Kumar, ‘A New Strained-Silicon Channel Trench-gate
Power MOSFET: Design and Analysis’, IEEE Trans. on Electron Devices, Vol.55, pp.3229-3304,
November 2008.
[7] T. Ghani et al., ‘A 90nm High Volume Manufacturing Logic Technology Featuring Novel
45nm Gate Length Strained Silicon CMOS Transistors,’ in IEDM Technical Digest, Washington,
DC, USA, pp. 978–980, December 2003.
[8] K. Rim et al., ‘Strained Si CMOS (SS CMOS) technology: opportunities and challenges’,
Solid-State Electronics, 47, pp. 1133-1139, 2003.