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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on April 19, 2006 by Seng Oon Toh (sengoon@eecs)
Borivoje Nikolić
EE 141
Homework #9: Activity Factor and Sequential Circuits
Problem #1
G2
A
G4
G1
B
G6
G3
C
G5
D
50 fF
Circuit A
A
B
C
D
G2
G1
50 fF
Circuit B
Let’s evaluate the effect of logic choice on power dissipation. Circuit A is an AND4
implemented as a NAND2 chain while Circuit B implements the same function using a 4
input gate.
a) Size circuit A and circuit B for minimum delay with Cin of 3 fF and Cout of 50 fF.
Report your answer in terms of the input capacitance seen at each gate.
b) Given that P(A=0) = P(B=0) = P(C=0) = P(D=0) = 0.25, calculate the probability
of energy consuming transitions P(0 → 1) at the outputs of the gates in both
circuits.
c) Assuming both circuits are operating at 500 MHz, calculate the dynamic power
consumption of the circuit. Assume γ = 1, Vdd = 2.5V, and only consider
capacitances at the inputs and output of the gates.
Problem #2
Consider the simple state machine shown above. A, B, and C represent combinational
logic blocks with the following properties:
tminA = 200 psec; tmaxA = 1 nsec;
tminB = 300 psec; tmaxB = 2 nsec;
tminC = 100 psec; tmaxC = 0.5 nsec;
The L-units represent positive latches clocked by . L has a setup time of 150 psec and a
delay of 250 psec (td-q when latch is transparent). Tc-q is 100 psec and thold is 100 psec.
The clock has a period T and is high for a duration of Ton. The duty cycle of the clock
hence equals 100 Ton/T %.
a) Determine the conditions on the clock necessary to avoid the occurrence of races.
b) Determine the absolute minimum clock period for this circuit to work correctly as
well as the maximum duty cycle.
c) Suppose that due to some sloppy clock-network routing, the clock signal at L1
arrives 100ps earlier than the clock signal at L2. Calculate the absolute minimum
clock period for this circuit to work properly as well as the maximum duty cycle.
Problem #3
Clk
1
2
1
Vx
A
B
2
Out
PMOS: 2
NMOS: 1
C
2
2
2
2
2
1
The circuit above is a Limited Switch Dynamic Logic (LSDL) NOR3 gate which is a
circuit family used in high performance datapaths. It is essentially a domino gate
followed by a latch. The relative sizing of the gates has been annotated on the schematic.
a) What is the purpose of the shaded transistors?
b) Assuming no propagation delay, complete the following ideal timing diagram.
Clk
A
B
C
Vx
Out
c) Calculate tsetup of the gate (tsetup is defined as the minimum period of time where
inputs have to be stable before the clock transitions into the latched state in order
for the correct value to be latched) in terms of intrinsic delay tp0. Assume γ=1.
d) The Clk signal is usually a positive level pulse. What would be the minimum
positive pulse-width of Clk (in terms of tp0) to ensure that a correct value is
latched?
e) Assuming that A=B=C=1, compare the activity factor at node Out to the activity
factor at node Vx which would be the output of a standard domino logic gate.
What can you infer about the dynamic power consumption of static gates being
driven by this gate compared to domino logic?