Download Logis6cs( ELEC327:(Lecture(6( Today( Prac6cal(Power(Measuring(

Logis6cs(
ELEC327:(Lecture(6(
Serial(Communica6on(
&  No#lectures#next#week!#
&  Next#labs:#
–  Low(power((due(1/31)(
–  Serial(communica6ons((due(2/7)(
–  Midterm(projects((demo(2/19)(
Today(
&  Power(measuring(
&  Serial(communica6ons(
Prac6cal(Power(Measuring(
Lab(4(
&  Workshop(Lab(6(K(Convert(ADC(sampling(code(
to(“low(power”(
&  Measure(power(using(DMM(
&  Write(a(0.5(Hz(LED(blink(func6on(for(lowest(
and(highest(power.(Document(your(
measurement(technique.(
Communica6ons(
&  The(simplest(is(parallel(
–  One(way(
&  There(may(be(mechanism(for(
peripheral(to(get(aYen6on(of((
μC((i.e.,(interrupt,(or(poll)(
(
(
Mul:ple#(8#
typically)#data#
lines#
μC#
“Latch”(
Peripheral#
“CS”(
–  Two(way(
&  We(need(another(line(to((
differen6ate(between(read((
and(write.(
&  Half(duplex((one(way(at(a(6me)(
&  Full(duplex((both(ways(at(once;((
needs(two(sets(of(data(lines.(
(
(
(
Data#
lines#
μC#
“Latch”(
Peripheral#
“CS”(
“R/~W”(
&  This(is(resource(expensive((pins,(realKestate…)(in(terms(of(
hardware,(but(easy(to(implement,(and(fast.(
Serial(Communica6ons(
&  Many(fewer(lines(are(required(to(transmit(data.((This(is(requires(
fewer(pins,(but(adds(complexity.(
(
(
Data(
(
(
Clock(
μC#
Peripheral#
(
“CS”(
(
(
(
(
&  Synchronous(communica6ons(requires(clock.((Whoever(controls(
the(clock(controls(communica6on(speed.(
&  Asynchronous(has(no(clock,(but(speed(must(be(agreed(upon(
beforehand((baud(rate).(
MSP430G2553(
Universal(Serial(Communica6on(
Interface(
&  SPI(
A
&  I2C(
Vdd(
SPI(
Slave(
R(
R(
SDA(
&  InterKIntegrated(Circuit(Interface(SCL(
&  Single(Master/Mul6ple(Slaves(
B
SCLK(
MOSI(
MISO(
SSN(
SPI(
Master(
&  Serial(Peripheral(Interface(
&  Single(Master/Single(Slave(
USCI(
!  USCI_A0
! 
supports:
!  SPI (3 or 4 wire)
!  UART
!  IrDA
USCI_B0 supports:
!  SPI (3 or 4 wire)
!  I2C
USCI(Serial(Protocols(
µC(
Master(
&  UART(
&  Universal(Asynchronous(Receiver/
TransmiYer(
&  Full(duplex(
R/T(
DAC(
Slave(
Tx(
Rx(
ADC(
Slave(
µC(
Slave(
Rx(
Tx( R/T(
Protocols …
51
Asynchronous(Serial((RSK232)(
&  Commonly(used(for(oneKtoKone(communica6on.((
&  There(are(many(variants,(the(simplest(uses(just(two(lines,(TX(
(transmit)(and(RX((receive).(
&  Transmission(process((9600(baud,(1(bit=1/9600=0.104(mS)(
– 
– 
– 
– 
– 
Transmit(idles(high((when(no(communica6on).(
It(goes(low(for(1(bit((0.104(mS)(
It(sends(out(data,(LSB(first((7(or(8(bits)(
There(may(be(a(parity(bit((even(or(odd(–(error(detec6on)(
There(may(be(a(stop(bit((or(two)(required(
RS232(Voltage(levels(
&  From(processor(side,(0V=logic(0,(((((((((((3.3V=logic(1(
&  In(a(“serial”(cable(+12→+3V=logic(0,((((K3→K12V=logic(1(
(
(
(
(
(
RS232(–(Handshaking(
&  Some(RS232(connec6ons(using(handshaking(lines(between(
DCE((Data(Communica6ons(Equipment)(and(DTE((Data(
Terminal(Equipment).(((
–  RTS((Ready(To(Send)(
&  Sent(by(the(DTE(to(signal(the(DCE(it(is(Ready(To(Send.(
–  CTS((Clear(To(Send)(
&  Sent(by(the(DCE(to(signal(the(DTE(that(it(is(Ready(to(Receive.(
–  DTR((Data(Terminal(Ready)(
&  Sent(to(DTE(to(signal(the(DCE(that(it(is(ready(to(connect(
–  DSR((Data(Set(Read)(
&  Sent(to(DC(to(signal(the(DTE(that(it(is(ready(to(connect(
&  In(prac6ce(if(these(handshaking(lines(are(used(it(can(be(
difficult(to(set(up(the(serial(communica6ons,(but(it(is(quite(
robust(once(working.(
&  There(is(also(soqware(handshaking((XON/XOFF)(
&  DTE(and(DCE(have(different(connector(pinouts.(
UART(code(
void main(void)
{
WDTCTL = WDTPW + WDTHOLD;
BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ;
P1SEL = BIT1 + BIT2 ;
P1SEL2 = BIT1 + BIT2;
UCA0CTL1 |= UCSSEL_2;
UCA0BR0 = 8;
UCA0BR1 = 0;
UCA0MCTL = UCBRS2 + UCBRS0;
UCA0CTL1 &= ~UCSWRST;
IE2 |= UCA0RXIE;
}
//
//
//
//
//
//
//
//
//
//
//
//
MSP430#USCI#in#UART#mode#
(also(USART(peripheral)(
UART#mode#features#include:#
& (7K(or(8Kbit(data;((odd,(even,(or(nonKparity(
& (Independent(transmit(and(receive((
& (LSBKfirst(or(MSBKfirst(data((
& (Receiver(startKedge(detec6on(for(autoK
wake(up(from(LPMx(modes(
& (Independent(interrupt(capability(for(
receive(and(transmit(
& (Status(flags(for(error(detec6on(and(
suppression(
& (BuiltKin(idleKline(and(addressKbit(
communica6on(protocols(for(
mul6processor(systems(
& (Status(flags(for(address(detec6on(
Echo received character, RX ISR used. Normal mode is LPM0.
USCI_A0 RX interrupt triggers TX Echo.
Baud rate divider with 1MHz = 1MHz/115200 = ~8.7
ACLK = n/a, MCLK = SMCLK = CALxxx_1MHZ = 1MHz
__bis_SR_register(LPM0_bits + GIE);
SPI((a(synchronous(interface)(
(Serial(Peripheral(Interface(K(Motorola)(
MSP430G2xx3
----------------/|\|
XIN|| |
|
--|RST
XOUT||
P1.2/UCA0TXD|------------>
|
P1.1/UCA0RXD|<------------
// Clock = 1MHz
// P1.1 = RXD, P1.2=TXD
//
//
//
//
//
//
SMCLK
1MHz 115200 (Formulae in data sheet)
1MHz 115200
Modulation UCBRSx = 5
**Initialize USCI state machine**
Enable USCI_A0 RX interrupt
// Enter LPM0, interrupts enabled
// Echo back RXed character, confirm TX buffer is ready first
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR(void)
{
while (!(IFG2&UCA0TXIFG));
// USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF;
// TX -> RXed character
}
&  Two(types(of(devices,(masters(and(slaves.(((
&  We’ll(consider(only(one(master,(but(
mul6ple(slaves.(
&  Signals(
– 
– 
– 
– 
SCLK:(Serial(CLocK,(set(by(Master(
MOSI:(Master(Out,(Slave(In(
MISO:(Master(In,(Slave(Out(
~SS:(Slave(Select(
&  Each(slave(gets(its(own(slave(select((other(lines(
are(shared)(
&  Pulling(line(low(selects(slave(
SPI(and(the(clock(
SPI(Capabili6es(
(intro)(
&  Clock(idles(low(
&  Master(pull(slave(select(line(low(to(select(device.(
&  First(bit(of(data(gets(put(on(MISO(and(MOSI((
(so(a(byte(goes(both(ways)(
&  Data(gets(shiqed(out((typically(8(bits,(but(not(necessarily)(
?  Always full-duplex
–  Communicates in both directions simultaneously
–  Transmitted (or received) data may not be meaningful
?  Multiple Mbps transmission speeds
–  0-50 MHz clock speeds not uncommon
?  Transfer data in 4 to 16 bit characters
?  Supports multiple slaves
–  The(data(gets(put(on(bus(on(falling(edge(of(clock((or(SS).(
–  The(data(gets(read(on(the(rising(edge(of(clock.(
17
SPI(and(the(clock(
(the(hard(truth)(
Unfortunately,(clock(can(be(set(many(ways(as(determined(by(clock(polarity(and(phase.(
&  CPOL=0:(Base(value(of(the(clock(is(0(
–  CPHA=0:(Data(read(on(rising(edge,(put(on(bus(on(falling(edge(of(SCLK.((i.e.,(clock(is(low).(
(Case(from(previous(slide)(
–  CPHA=1:(Data(read(on(falling(edge,(put(on(bus(on(rising(edge((i.e.,(clock(is(high).(
&  CPOL=1:(Base(value(of(the(clock(is(1(
–  CPHA=0:(Data(read(on(falling(edge,(put(on(bus(on(rising(edge((i.e.,(clock(is(high).(
–  CPHA=1:(Data(read(on(rising(edge,(put(on(bus(on(falling(edge((i.e.,(clock(is(low).(
SPI(tradeoffs:(the(pros(and(cons(
?  Pros
– 
– 
– 
– 
Fast for point-to-point connections
Easily allows streaming/constant data inflow
No addressing in protocol, so it’s simple to implement
Broadly supported
?  Cons
– 
– 
– 
– 
Slave select/chip select makes multiple slaves more complex
No acknowledgement (can’t tell if clocking in garbage)
No inherent arbitration
No flow control (must know slave speed)
20
SPI#and#SCI#
SPI(is(used(everywhere!(
&  Peripherals(
–  LCDs(
–  Sensors(
–  Radios(
–  Lots(of(other(chips(
&  Microcontrollers(
–  Almost(all(MCUs(have(SPI(masters(
–  Some(have(SPI(slaves(
21
SPI(Code(
// MCLK = SMCLK = default DCO ~1048k, BRCLK = SMCLK/2
//
/|\ ---------------------//
TLC549
| |
XIN |32kHz
//
--------------|RST
XOUT|//
|
CS|<---|P3.0
|
//
|
DATAOUT|--->|P3.2/UCB0SOMI
|
// ~>| IN+ I/O CLK|<---|P3.3/UCB0CLK
P5.1|--> LED
void main(void)
{
volatile unsigned int i;
char data;
P5DIR |= 0x02;
P3SEL |= 0x0C;
P3DIR |= 0x01;
UCB0CTL0 |= UCMST+UCSYNC+UCMSB;
UCB0CTL1 |= UCSSEL_2;
UCB0BR0 = 0x02;
UCB0BR1 = 0;
UCB0CTL1 &= ~UCSWRST;
while(1)
{
P3OUT &= ~0x01;
UCB0TXBUF = 0x00;
while (!(IFG2 & UCB0RXIFG));
}
//
//
//
//
//
//
P5.1 output
P3.3,2 option select
P3.0 output direction
8-bit SPI mstr, MSb 1st, CPOL=0, CPHS=0
SMCLK
Set Frequency
// **Initialize USCI state machine**
// Enable TLC549 (A/D) , ~CS (~SS) reset
// Dummy write to start SPI
// USCI_B0 RX buffer ready?
// data = 00|DATA
P3OUT |= 0x01;
// Disable TLC549, ~CS (~SS) set
if(data>=0x7F) P5OUT |= 0x02;
else P5OUT &= ~0x02;
// data = AIN > 0.5(REF+ - REF-)?
// LED off
}
data = UCB0RXBUF;
LED On
SPI#mode#features#include:#
&  7K(or(8Kbit(data(length(
&  LSBKfirst(or(MSBKfirst(data(
&  Master(or(slave(modes(
&  Selectable(clock(polarity(
and(phase(control(
&  Programmable(clock(
frequency(in(master(mode(
&  Independent(transmit(and(
receive(
&  Con6nuous(transmit(and(
receive(
&  Independent(interrupt(
capability(for(receive(and(
transmit(
&  (Slave(opera6on(in(LPM4(
I2C(or(I2C(
(InterKIntegrated(Circuit(–(Philips)(
&  As(with(SPI(a(masterK(
slave(system.(
&  Also(called(a(2Kwire(bus.(
It(Has(only(clock(and(data,(with(pullKup(resistors((Rp(in(
diagram).(
&  Lines(can(be(pulled(low(by(any(device,(and(are(high(
when(all(devices(release(them.(
&  There(are(no(“slaveKselect”(lines(–(instead(the(devices(
have(“addresses”(that(are(sent(as(part(of(the(
transmission(protocol.(
&  Four(max(speeds((100(kbS((standard),(400(kbS((fast),(1(
MbS((fast,plus),(and(3.4(MbS((high0speed)(
Open(Collector(
Building(an(I2C(Bus(
?  If IC Output is...
–  Not Driven (OFF)
 The transistor is off and
looks like an open circuit
–  Driven (ON)
 The transistor is on, and
the bus line is tied
Example Open Collector Circuit
Author: Yan bellavance http://en.wikipedia.org/wiki/File:OpencollectorV3.png
(pulled) to ground
I2C(clock(
& 
& 
& 
& 
?  If no device is driving the bus...
–  They all look like open circuits
–  Bus voltage is Vdd
?  If any device is driving the bus...
–  Current flows Vdd through RPullup
–  Bus voltage is 0 V
Vdd
(3.3~5V)
RPullup
(10~100 kΩ)
I2C(transac6on(
&  TransmiYer/receiver(differs(from(master/slave(
Not(a(“tradi6onal”(clock(
Normally(is(kept(“high”(using(a(pullKup(
Pulsed(by(the(master(during(data(transmission(
Master(could(be(either(the(transmiYer(or(
receiver(
–  Master(ini6ates(transac6ons(
–  Slave(responds(
&  TransmiYer(sets(data(on(SDA(line,(slave(ACKs(
–  For(a(read,(slave(is(transmiYer(
–  For(a(write,(master(is(transmiYer(
–  Slave(device(can(hold(clock(low(if(needs(more(6me(
&  Allows(for(flow(control(
27
28
I2C(start(condi6on(
I2C(address(transmission(
&  Data(is(always(sampled(on(the(rising(clock(
edge(
&  Address(is(7(bits((or(10(bits)(
&  An(8Kth(bit(indicated(read(or(write(
?  Master pulls SDA low while SCL is high
?  Normal SDA changes only happen when
SCL is low
(
–  High(for(read(
–  Low(for(write(
&  Addresses(assigned(by(Philips/NXP(
–  For(a(fee(
&  Was(covered(by(patent(
29
I2C(data(transmission(
30
I2C(stop(condi6on(
&  TransmiYed(just(like(address((8(bits)(
&  For(a(write,(master(transmits,(slave(
acknowledges(
&  For(a(read,(slave(transmits,(master(
acknowledges(
&  Transmission(con6nues(
?  Master pulls SDA high while SCL is high
?  Also used to abort transactions
–  Subsequent(bytes(sent(
–  Con6nue(un6l(master(creates(stop(condi6on(
31
32
I2C(Write(a(Single(Byte(
1. 
2. 
3. 
4. 
5. 
6. 
7. 
Other(Features(
&  You(can(transfer(mul6ple(bytes(in(a(row(
(
&  (
(
(
(
(
&  At(any(6me,(slave(can(hold(SCL(low(to(slow(transfer(
down((called(“clockKstretching”)(
All:(allow(SDA,(SCL(start(high(
Master:(SDA(low(to(signal(start(
Master:(Send(out(SCL,(and(7(bit(address(followed(by(0((~W)(on(SDA(
Slave:(Pull(SDA(low(to(signify(ACKnowledge(
Master:(Send(out(8(data(bits(on(SDA(
Slave:(Ack(
All:(allow(SDA(to(go(high(when(SCL(is(high((stop)(
&  For#“Read”,##
3.  Master:(Address(following(by(1((R)(on(SDA(
5.  Slave:(Send(out(8(data(bits(on(SDA(
6.  Master:(Ack(
&  Any(device(that(malfunc6ons(can(disable(bus.(
//
//
//
//
//
//
//
//
//
//
//
I2C(and(SCI(
I2C(Code(
The#I2C#features#include:#
&  Compliance(to(Philips(I2C(specifica6on(
&  Slave(receiver/transmiYer(mode(
&  Standard(mode(up(to(100(kbps(and(
fast(mode(up(to(400(kbps(support(
&  Programmable(UCxCLK(frequency(in(
master(mode(
&  Designed(for(low(power(
&  (Slave(receiver(START(detec6on(for(
autoKwake(up(from(LPMx(modes(
&  (Slave(opera6on(in(LPM4(
Demo - USCI_B0 I2C Master Interface to DAC8571, Write
Description: Using UCB0TXIE, a continuous sine wave is output to
external DAC using a 16-point look-up table. Only one start
is executed. Data is handled by the ISR and the CPU is in LPM0.
MCLK = SMCLK = TACLK = BRCLK = 1MHz
DAC8571 I2C address = 0x4C (A0 = GND)
-----------------------------|XIN
P3.1/UCB0SDA|<--------------->|SDA
|
32kHz |
P3.2/UCB0SCL|---------------->|SCL I2C
|
-|XOUT
|
|
SLAVE
|
|
I2C MASTER
|
GND|A0
|
void main(void) {
WDTCTL = WDTPW + WDTHOLD;
P3SEL |= 0x06;
UCB0CTL1 |= UCSWRST;
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC;
UCB0CTL1 = UCSSEL_2 + UCSWRST;
UCB0BR0 = 11;
UCB0BR1 = 0;
UCB0I2CSA = 0x4c;
UCB0CTL1 &= ~UCSWRST;
IE2 |= UCB0TXIE;
UCB0CTL1 |= UCTR + UCTXSTT;
UCB0TXBUF = 0x10;
__bis_SR_register(CPUOFF + GIE);
}
//
//
//
//
//
//
Stop Watchdog Timer
Assign I2C pins to USCI_B0
Enable SW reset
I2C Master, synchronous mode
Use SMCLK, keep SW reset
fSCL = SMCLK/11 = 95.3kHz
//
//
//
//
//
//
Set slave address
Clear SW reset, resume operation
Enable TX ready interrupt
I2C TX, start condition
Write DAC control byte
Enter LPM0 w/ interrupts
// USCI_B0 Data ISR
#pragma vector = USCIAB0TX_VECTOR
__interrupt void USCIAB0TX_ISR(void) {
static unsigned char ByteCtr;
}
UCB0TXBUF = Sine_Tab[ByteCtr++];
ByteCtr &= 0x0f;
// Transmit data byte
// Do not exceed table
Soqware(UART(Implementa6on(
&  A(simple(UART(implementa6on,(using(the(Capture(&(Compare(
features(of(the(Timer(to(emulate(the(UART(communica6on(
&  HalfKduplex(and(rela6vely(low(baud(rate((9600(baud(recommended(
limit),(but(2400(baud(in(our(code((1(MHz(DCO(and(no(crystal)(
&  BitK6me((how(many(clock(6cks(one(baud(is)(is(calculated(based(on(the(
6mer(clock(&(the(baud(rate(
&  One(CCR(register(is(set(up(to(TX(in(Timer(Compare(mode,(toggling(
based(on(whether(the(corresponding(bit(is(0(or(1(
&  The(other(CCR(register(is(set(up(to(RX(in(Timer(Capture(mode,(similar(
principle(
&  The(func6ons(are(set(up(to(TX(or(RX(a(single(byte((8Kbit)(appended(by(
the(start(bit(&(stop(bit(
USB(COM(Port(Communica6on(
&  Emula6on(hardware(implements(emula6on(features(as(well(
as(a(serial(communica6ons(port(
&  Recognized(by(Windows(as(part(of(composite(driver(
&  UART(Tx/Rx(pins(match(SpyKBiKWire(JTAG(interface(pins(
Applica6on(note:((hYp://focus.6.com/lit/an/slaa078a/slaa078a.pdf((
HI,(LO,(IN(
Two bus configuration models
Sources(
&  Prabal Dutta/Pat Pannuto – EECS373
–  hYp://web.eecs.umich.edu/~prabal/teaching/
eecs373Kf11/slides/lec10.ppt(
&  Erik(Cheever(–(Engineering(91(
–  hYp://www.swarthmore.edu/NatSci/echeeve1/
Class/e91/Lectures/E91(10)Serial.pdf(
&  TI(MSP430(Workshop(
Some wires have been renamed
Master and multiple independent
slaves
Master and multiple daisychained slaves
http://www.maxim-ic.com/appnotes.cfm/an_pk/3947
http://upload.wikimedia.org/wikipedia/commons/thumb/f/fc/
SPI_three_slaves.svg/350px-SPI_three_slaves.svg.png
40
I2C uses
I2C bus transactions: data transfer
?  Originally used by Philips inside television sets
?  Now a very common peripheral bus standard
?  Intended for use in embedded systems
?  Philips, National, Xicor, Siemens, … all use
?  Also used in PCs
?  RTC
?  Temperature sensors
?  Variant is the SMBus (system management bus)
41
Multi-Master Arbitration
(Bus Contention)
?  What does it mean to be multi-master?
?  How do we actually make that work?
42
I2C Scales...
? 
? 
? 
? 
I2C
Standardizes peripheral classes
SCK, SDA
Philips/NXP
?  What other features does this allow?
–  Clock stretching
–  Repeated start
44