Download 2102-282 Digital Electronics - IC Design & Application Research Lab.

Tutorial I
Circuit Simulation
Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory
June 24, 2005
B.Supmonchai
Outline

Introduction to SPICE

Basic Commands and elements in SPICE

SPICE MOSFET models

Device Characterization

Pitfalls and Fallacies
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SPICE Simulations
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B.Supmonchai
Simulations in IC Processes

Fabricating chips is expensive and time-consuming;
need good simulation CAD tools and hard work.
High
Level of Abstraction
Low
2102-545 Digital ICs
Architecture
Predict throughput and memory access
patterns at the RTL, for design decision such
as pipelining and cache organization
Logic
Predict function of digital circuits and verify
correct logical operation of designs - HDL
Circuit
Use device models and netlist to predict
circuit voltages and currents, which indicate
performance and power consumption - SPICE
Process
How factors in a process (e.g., time and
temperature) affect device physical and
electrical characteristics - SUPREME
SPICE Simulations
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B.Supmonchai
Introduction to SPICE

Simulation Program with Integrated Circuit Emphasis
 Developed in 1970’s at Berkeley
 Written in FORTRAN for punch-card machines
 Circuits elements are called cards
 Complete description is called a SPICE deck

SPICE has been regarded as de facto standard in circuit
simulation.

Commercial releases of SPICE (e.g., PSPICE and
HSPICE) typically contain a much larger selection of
refined models.
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SPICE Simulations
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B.Supmonchai
SPICE Decks

Writing a SPICE deck is like writing a good
program
 Plan: sketch schematic on paper or in editor
 Modify existing decks whenever possible
 Code: strive for clarity
 Start with name, email, date, purpose
 Generously comment
 Test:
 Predict what results should be
 Compare with actual
 Garbage In, Garbage Out!
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SPICE Simulations
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B.Supmonchai
SPICE Elements
Letter
R
C
L
K
V
I
M
D
Q
W
X
E
G
H
F
2102-545 Digital ICs
Element
Resistor
Capacitor
Inductor
Mutual Inductor
Independent voltage source
Independent current source
MOSFET
Diode
Bipolar transistor
Lossy transmission line
Subcircuit
Voltage-controlled voltage source
Voltage-controlled current source
Current-controlled voltage source
Current-controlled current source
SPICE Simulations
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B.Supmonchai
Units in SPICE
Letter
Unit
Magnitude
a
atto
10-18
f
femto
10-15
p
pico
10-12
n
nano
10-9
u
micro
10-6
m
milli
10-3
k
kilo
103
x
mega
106
g
giga
109
Ex: 100 femtofarad capacitor = 100fF, 100f, 100e-15
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SPICE Simulations
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B.Supmonchai
Sources

DC Source
Vdd vdd gnd 2.5

Piecewise Linear Source
Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8

Pulsed Source
Vck clk gnd PULSE 0 1.8 0ps 100ps 100ps 300ps 800ps
PULSE v1 v2 td tr tf pw per
td
tr
pw
tf
v2
v1
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per
SPICE Simulations
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B.Supmonchai
Example: RC Circuit
* rc.sp
* [email protected] 2/2/03
* Find the response of RC circuit to rising input
*-----------------------------------------------* Parameters and models
*-----------------------------------------------.option post
R1 = 2KΩ
Vin
C1 = 100fF
+
Vout
-
*-----------------------------------------------* Simulation netlist
*-----------------------------------------------Vin
in
gnd
pwl
0ps 0 100ps 0 150ps 1.8 800ps 1.8
R1
in
out
2k
C1
out
gnd
100f
*-----------------------------------------------* Stimulus
*-----------------------------------------------.tran 20ps 800ps
.plot v(in) v(out)
.end
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time
)
0.
20.0000p
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(ab
legend:
a: v(in)
b: v(out)
v(in)
2.0000
1.5000
1.0000
500.0000m
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B.Supmonchai
RC Circuit Result (Textual)
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SPICE Simulations
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B.Supmonchai
RC Circuit Result (Graphical)
2.0
v(in)
v(out)
1.5
1.0
0.5
0.0
0.0
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100p 200p 300p 400p 500p 600p 700p 800p 900p
t(s)
SPICE Simulations
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B.Supmonchai
MOSFET Elements

M element for MOSFET
Node Name
Mname drain gate source body type
+ W=<width> L=<length>
+ AS=<area source> AD = <area drain>
+ PS=<perimeter source> PD=<perimeter drain>

Example:
M1
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3
1
0
0
NMOD
L=1U
SPICE Simulations
W=10U
AD=120P
PD=42U
12
B.Supmonchai
MOSFET Models

Earlier SPICE versions had three built-in
MOSFET models:
 LEVEL 1 (MOS1) - Square law I-V characteristic
 LEVEL 2 (MOS2) - Detailed analytical MOSFET
 LEVEL 3 (MOS3) - Semi-empirical

MOS2 and MOS3 include second-order effects
such as velocity saturation, mobility
degradation, subthreshold conduction, and
DIBL.

All three LEVELs do not provide good fits to
the characteristics SPICE
of modern
devices.
Simulations
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B.Supmonchai
MOSFET Models (2)

For modern submicron devices, the Berkeley
Short-Channel IGFET Model (BSIM) is the most
widely used (commercially and academically).
 BSIM version 1, 2, 3v3, and 4 are implemented as
SPICE level 13, 39, 49, and 54, respectively

BSIM is a very elaborate model that are derived
from the underlying device physics but use an
enormous number of parameters to fit the behavior
of modern transistor.
 BSIM version 3v3 requires over 27 pages of over 100
parameters and device equations to describe the model.
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SPICE Simulations
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B.Supmonchai
Selection of Models

The level (type) of MOSFET model to be used
in a particular simulation can be specified
through the .MODEL statement in SPICE.

With the statement, the user can describe a large
number of model parameters including geometry
of the device such as channel length and width.
M1
3
1
0
0
12
5
L=1U
W=10U
PMOD
L=1.2U
AD=120P
PD=42U
MDEV32
14
.MODEL
NMOD
NMOS (LEVEL=1 VTO=1.4
.MODEL
+
+
PMOD
PMOS (VTO=-2 KP=3.0E-5 LAMBDA=0.02 GAMMA=0.4
CBD=4PF CBS=2PF RD=5 RS=3 CGDO=1PF
CGSO=1PF CGBO=1PF)
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NMOD
W=20U
SPICE Simulations
KP=4.5E-5
CBD=5PF
CBS=2PF)
15
B.Supmonchai
NMOS Transistor Circuit Model
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SPICE Simulations
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B.Supmonchai
LEVEL 1 Model Equations

Corresponding to our unified model for manual
analyses in the class.

Basic Current Models:
IDS

0
VGS  VT

 W eff

VDS 
  k'
1   VDS VGS  VT   VDS VDS  VGS  VT

2 
 Leff

k' W eff
2

VDS  VGS  VT
1   VDS VGS  VT 
2 Leff
where
2102-545 Digital ICs
Vt  VT 0  
 2
SPICE Simulations
F
 VSB  2 F
cutoff
linear
saturation

17
B.Supmonchai
LEVEL 1 Model Equations (II)

Completely characterized by the five electrical
parameters: k’, VT0, , |2F|, and  (KP, VTO,
GAMMA, PHI, and LAMBDA in SPICE)
 Physical parameters, e.g., tox (TOX) can be specified
in stead of the electrical parameters.
 If both present simultaneously in the model,
electrical parameters always override physical
parameters.

Though grossly inaccurate, LEVEL 1 offers a
quick, useful estimate of the circuits.
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SPICE Simulations
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B.Supmonchai
LEVEL 2 and 3 Model Equations

Improved models for the drain current
 Level 2: A number of semi-empirical corrections
have been added to the basic equations.
 Level 3: Majority of the model equations are
empirical
 Improving accuracy
 Reducing complexity in calculation.

Although more accurate, LEVEL 2 and 3 models
are still insufficient to achieve good agreement
with experimental data for the deep submicron
devices.
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SPICE Simulations
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B.Supmonchai
Parasitic Capacitances

SPICE models use separate sets of equations in
cut-off, linear, and saturation modes to calculate
the device parasitic capacitances.

Gate Capacitances: SPICE uses a simple model
that represents the charge storage effect by three
nonlinear two-terminal capacitors: CGB, CGS, and
CGD (please see chapter 2 for the detail)
 Required geometry information: gate oxide thickness
(TOX), channel width (W), channel length (L), and
the lateral diffusion (LD).
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SPICE Simulations
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B.Supmonchai
Parasitic Capacitances (2)

Junction Capacitance: SPICE uses the simple
pn-junction model to simulate the parasitic
capacitances of the source and drain diffusion
regions.
CSB 
CDB 
C j  AS
 VSB  j
1



0 
C j  AD
M
 VDB M j
1

  0 

C jsw  PS
 VSB  jsw
1



0 
C jsw  PD

 VDB M jsw
1

  0 
M
where AS and AD are the source and the drain areas; PS and
PD are the source and the drain perimeters, respectively

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B.Supmonchai
Parasitic Capacitances (3)

Cj is the zero-bias depletion capacitance per unit area at
the bottom plate of the drain or the source diffusion
region. (CJ in SPICE)

Cjsw is the zero-bias depletion capacitance per unit length
at the side-wall plate. (CJSW)

Mj and Mjsw are the junction degrading coefficients of the
bottom and side-wall plates, respectively. (MJ, MJSW)
 0.5 for abrupt juction and 0.33 for linearly graded junction

0 is the built-in junction potential which is actually a
function of the doping densities (PB for bottom plate
and PHP (MOS) or PBSW (BSIM) for side walls)
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B.Supmonchai
Example: NMOS I-V Characteristics
* mosiv.sp
Ids
*-----------------------------------------------* Parameters and models
*-----------------------------------------------.include '../models/tsmc180/models.sp'
.temp 70
.option post
Vgs
*-----------------------------------------------* Simulation netlist
*-----------------------------------------------*nmos
Vgs
g
gnd
0
Vds
d
gnd
0
M1
d
g
gnd
gnd
NMOS
W=0.36u L=0.18u
4/2
Vds
*-----------------------------------------------* Stimulus
*-----------------------------------------------.dc Vds 0 1.8 0.05 SWEEP Vgs 0 1.8 0.3
.end
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B.Supmonchai
Example: I-V Characteristics
250
Vgs = 1.8
200
Vgs = 1.5
150
Ids
(A)
Vgs = 1.2
100
Vgs = 0.9
50
Vgs = 0.6
0
0.0
2102-545 Digital ICs
0.3
0.6
0.9
Vds
1.2
SPICE Simulations
1.5
1.8
24
B.Supmonchai
Example: Inverter Transient Analysis
•inv.sp
* Parameters and models
*-----------------------------------------------.param SUPPLY=1.8
.option scale=90n
.include '../models/tsmc180/models.sp'
.temp 70
.option post
8/2
a
y
4/2
* Simulation netlist
*-----------------------------------------------Vdd
vdd
gnd
'SUPPLY'
Vin
a
gnd
PULSE
0 'SUPPLY' 50ps 0ps 0ps 100ps 200ps
M1
y
a
gnd
gnd
NMOS
W=4
L=2
+ AS=20 PS=18 AD=20 PD=18
M2
y
a
vdd
vdd
PMOS
W=8
L=2
+ AS=40 PS=26 AD=40 PD=26
* Stimulus
*-----------------------------------------------.tran 1ps 200ps
.end
**Unloaded
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SPICE Simulations
inverter**
25
B.Supmonchai
Example: Inverter Transient Results
Overshoot
v(a)
v(y)
1.8
1.44
Very fast
edges
tf = 10ps
(V) 1.0
tpdf = 12ps
tpdr = 15ps
tr = 16ps
0.36
0.0
0.0
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50p
100p
t(s)
SPICE Simulations
150p
200p
26
B.Supmonchai
Subcircuits

Common elements can be declared as subcircuits
 SPICE Decks are easier to read and maintain.
.subckt inv a y N=4 P=8
M1 y a gnd gnd NMOS W='N' L=2
+ AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10'
M2 y a vdd vdd PMOS W='P' L=2
+ AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10'
.ends

Ex: Fanout-of-4 Inverter Delay
 Reuse inv
 Shaping
 Loading
2102-545 Digital ICs
Device
Under
Test
Shape input
a
2
X1
1
SPICE Simulations
b
8
X2
4
c
32
X3
16
Load
d
Load on
Load
128
512
e
f
X4
X5
64
256
27
B.Supmonchai
Example: FO4 Inverter Delay
* fo4.sp
* Parameters and models
*---------------------------------------------------------------------.param SUPPLY=1.8
.param H=4
.option scale=90n
.include '../models/tsmc180/models.sp'
.temp 70
.option post
* Subcircuits
*---------------------------------------------------------------------.global vdd gnd
.include '../lib/inv.sp'
* Simulation netlist
*---------------------------------------------------------------------Vdd
vdd
gnd
'SUPPLY'
Vin
a
gnd
PULSE
0 'SUPPLY' 0ps 100ps 100ps 500ps 1000ps
X1
a
b
inv
* shape input waveform
X2
b
c
inv
M='H'
* reshape input waveform
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B.Supmonchai
Example: FO4 Inverter Delay (2)
X3
X4
x5
c
d
e
d
e
f
inv
inv
inv
M='H**2' * device under test
M='H**3' * load
M='H**4' * load on load
* Stimulus
*---------------------------------------------------------------------.tran 1ps 1000ps
.measure tpdr
* rising prop delay
+
TRIG v(c) VAL='SUPPLY/2' FALL=1
+
TARG v(d) VAL='SUPPLY/2' RISE=1
.measure tpdf
* falling prop delay
+
TRIG v(c) VAL='SUPPLY/2' RISE=1
+
TARG v(d) VAL='SUPPLY/2' FALL=1
.measure tpd param='(tpdr+tpdf)/2'
* average prop delay
.measure trise
* rise time
+
TRIG v(d)
VAL='0.2*SUPPLY' RISE=1
+
TARG v(d)
VAL='0.8*SUPPLY' RISE=1
.measure tfall
* fall time
+
TRIG v(d)
VAL='0.8*SUPPLY' FALL=1
+
TARG v(d)
VAL='0.2*SUPPLY' FALL=1
.end
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B.Supmonchai
Example: FO4 Inverter Delay Results
2.0
a
b
1.5
c
d
1.0
(V)
e
tpdf = 66ps
tpdr = 83ps
f
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
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B.Supmonchai
Device Characterization

Modern SPICE models are so complicated that
the designer cannot easily read key performance
characteristics from the model files.

A more convenient approach is to run a set of
simulations and then extract parameters and
other interesting data, e.g., I-V characteristics,
threshold voltage, effective resistance and
capacitance.
 Various methods to find these parameters and the
required simulations are described in the literature.
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B.Supmonchai
Device Characteristics Comparison
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SPICE Simulations
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B.Supmonchai
Pitfalls and Fallacies

Failing to estimate diffusion and interconnect parasitics
in simulations
 Diffusion capacitance can account for more than 50% of the
delay of a high fan-in, low fanout gate. Make sure that the area
and perimeter of the source and drain are included in the
simulation.
 RC delay of the long wires dominate the path delay but it is
difficult to estimate.

Good models describe not only the circuit but also the
input edge rates, the output loading, and parasitics such
as diffusion capacitance and interconnect.
 Gate delay is strongly dependent on the rise/fall time of the
input and even more strongly on the output loading
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SPICE Simulations
33
B.Supmonchai
Pitfalls and Fallicies (2)

SPICE is prone to Garbage in, Garbage out! So
do not blindly trust the results from SPICE.
 Failing to account for hidden scale factors
 Identifying incorrect critical path
 Choosing inappropriate transistor sizes
 Compare results of a design with carefully selected
transistor sizes to a convention design with poorly selected
sizes.

Do not use SPICE in place of thinking
 Do not use SPICE too much. Circuit simulation
should be guided by analysis
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SPICE Simulations
34
B.Supmonchai
Pitfalls and Fallacies (3)

Rule of Thumbs:
“Assume SPICE decks are buggy until proven otherwise.”
 If the simulation does not agree with your
expectations, look closely for errors or inadequate
modeling in the deck.
 Motto: Check and Recheck!
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SPICE Simulations
35