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Combiner functionalities
BEAM PERMIT CONTROL
Beam dump line survey from the Threshold comparators (TC)
through P0 daisy chain lines.
TESTS
Related to the Beam Interlock
Related to the HV (use of VME DBT)
ANALOG GENERATION
Control of the HV with 0-10V
Modulation of the HV
ANALOG ACQUISITION
Monitor of the HV1 :
U level & U modulation (separate channels)
I
level
Monitor of the HV2 :
same as HV1
VOLTAGES SURVEY
VME 5V, 3.3V, ±12V
P0 FPS 5V, ±15V
HV PS1 & PS2 min/max V & I
Combiner functionalities : Tests
BIL Beam Inhibition Lines
(test of the lines between DAB and Combiner).
Inhibition test for the LBIS
(LHC Beam Interlock System - Combiner).
HTAT step of the HT.
Step of the HT activating a TEST_CFC on the tunnel card.
HTLF Low frequency modulation of the HT
Modulation of the high tension power supplies an analysis of
the running sums.
HT monitoring
Continuous check of the voltage and current for the 2 power
supplies.
VME Supplies monitoring
Continuous check of the 5V, 3.3V and ±12V.
P0 Floating Supplies
Continuous check of the 5V and ±15V.
Combiner functionalities
BLETC
P0 Connector
Beam permit related parts
P2 Connector
BLECS
(down)
or BIS
Power Supplies
Comparators
Logic
Beam Energy (Serial)
Beam Energy (Serial)
CTRV
BLECS
(up)
Beam Dump (M & UM)
Beam permit
decision unit
Auto-test
Bloc
Post-mortem
Beam permit
Beam info
FPGA
Beam permit
HV1
HV2
Comparators
VME PS 4x
P0 PS 3x
12 lines
Combiner functionalities
Beam permit related parts
Beam Permit from TC (M)
Beam Permit to BIS (MA)
Beam Permit from TC (U)
Beam Permit to BIS (MB)
Beam Permit from BLECS (MA)
Beam Permit to BIS (UA)
Beam Permit from BLECS (MB)
Beam Permit from BLECS (UA)
Beam Permit
decision unit
Beam Permit from BLECS (UB)
Beam Permit to BIS (UB)
Post-mortem
or
Login
Beam Energy Failure
Auto-Test Failure
Inhibits
Time Stamps (orbit counter)
FPGA
Synchro & Clocks from BOBR
Combiner functionalities
Registers structure
VME
DEBUG
VME MUX
Register
Other source
DEBUG
Application
DEBUG
External
memory
Interface
VME
Register
Combiner functionalities
Auto-test overview
BLECS
“Combiner”
Control
0-6.8V
Real
excitation
signal
Optical
Link
BLETC
VME
HV
(Vin*300)
SURFACE
TUNNEL
BLECF
Current
BLM chamber
HV 0-2000V
Combiner functionalities
HV1
HV2
P2 Connector
BLETC
P1 & P2 Con.
Auto-test related parts
VME
SLAVE
VME
MASTER
DAC
ADC
Potentiometers LEDS
FPGA
SRAM
Control Access
SPI
Auto-test
logic
SPI
I2C
NV
Memory
Control
Registers
Phase & Gain
tracking
Beam permit
decision unit
Signal
Generation
SRAM
Combiner functionalities
Auto-test related parts
TC
(16 max)
VME
MASTER
UNIT
Real Excitation
Signal
NV
Memory
2-PORT RAM
4x128x32bits
Phase & Gain
tracking
Thresholds
Decision
Unit
2-PORT RAM
4x128x32bits
Phase & Gain
tracking
Thresholds
Decision
Unit
1 TC
2-PORT RAM
4x128x32bits
Phase & Gain
tracking
Thresholds
Decision
Unit
2-PORT RAM
4x128x32bits
Phase & Gain
tracking
Thresholds
Decision
Unit
Excitation Signal frequency 0.3Hz
Sample per period 128
Number of period 3
Number of channel in parallel 16 (1 TC)
Total time for one create 3*1/0.3Hz*16TC = 160s
The combiner need to access the VME bus every 1/.3Hz*128 = 26ms
Combiner functionalities
BEAM PERMIT CONTROL
+5V
Task :
Receive the Beam Dump request
From the Threshold Comparators
(TC) and transmit it to the Beam
Interlock System (BIS)
TC N
(DAB)
Beam dump
TC - TC
TC - Comb
TC N
(DAB)
COMB 1
COMB 2
Beam permit
Comb – Comb
Comb - BIS
TC 1
(DAB)
TC 2
(DAB)
TC N
(DAB)
COMBINER 3
+3.3V
BIS
Combiner functionalities
BEAM PERMIT CONTROL
Beam dump lines :
1) From TC to TC
2) From TC to the Combiner
Lines from TC board N-1
Lines to TC board N+1
or to the Combiner
Lines from FPGA
Needs frequency
>1MHz to retrig the
One shot
Combiner functionalities
BEAM PERMIT CONTROL
Beam permit lines :
1) From Combiner to Combiner
2) From Combiner to Beam interlock (BIS)
Lines from Combiner board N-1
Lines from FPGA of the
combiner representing all
other sources of beam
dump:
Voltage survey, non
satisfying test, etc
Lines to Combiner board,
next create or to the BIS
Combiner functionalities
BEAM PERMIT CONTROL
Beam permit lines Combiner to BIS
User.Permit.A+
IC1
R2
D1
R1
User.Permit.A-
D2
One shot output state
Q
1
0
1
0
Inv. Q
0
1
1
0
Beam permit
PERMIT
DUMP
DUMP
DUMP
Normal states
Fault state
T1
‘A’
T2
R4
Combiner functionalities
BEAM PERMIT CONTROL
PCB Implementation
Beam Dump lines from the TC
Beam permit lines from
previous combiner to
next combiner or BIS
Combiner functionalities
ANALOG GENERATION
The high voltage power supplies for the ionization chambers are controlled by analog signals
0-10V.
There is an analog sum done between the 2 outputs of the DAC, the modulation signal is
attenuated with a potentiometer digitally controlled.
Serial
Peripheral
Interface
From the
FPGA
Offset
16 bits
DAC8532
Modulation
Pot digitally
Controlled
(8 bits steps)
Inter Integrated Circuit (I2C)
bus to the FPGA
Analog
SUM
To the HV supply
0-10V Voltage
Control
Combiner functionalities
ANALOG GENERATION
SCHEMATIC
Combiner functionalities
ANALOG ACQUISITION
The high voltage power supplies have monitor analog output to view the voltage and current levels, there
is 1 channel for the current and 2 channels of digitalization for the voltage (offset and low frequency
modulation
Buffer
Serial
Peripheral
Interface
To the
FPGA
LP
Filter
Instrumentation
amplifier
Offset compensation
+15V
ADC
GAIN
From the HV supply
0-10V Voltage Monitor
Inter Integrated
Circuit (I2C) bus to
the FPGA
Digital pot.
Digital pot.
+0V
Buffer
LP
Filter
From the HV supply
0-10V Current Monitor
Combiner functionalities
ANALOG ACQUISITION
Combiner functionalities
ANALOG  DIGITAL CONVERSIONS
PCB Implementation
Analog generation for the 2 HV PS
Digitalization of the
information coming
from the 2 HV power
supplies
RC filter close to
the connector to
cut the eventual
high frequencies
induced by the
digital components
Combiner functionalities
VOLTAGES SURVEY HV SUPPLY
There is a second survey of the HV power
supplies level with comparators with fixed level
(to be determined)
Lower and higher limit for the voltage and lower
and higher limit for the current.
Resistor calculated for the schematic shown
U min = 1333V
U max = 1666V
Combiner functionalities
VOLTAGES SURVEY
VME & P0 floating PS
VME POWER SUPPLIES:
5V, 3.3V, ±12V
P0 FLOTING POWER SUPPLIES:
5V, ±15V
Combiner functionalities
VOLTAGES SURVEY
1) HV SUPPLIES
2) VME & P0 floating PS
Survey VME PS
Survey P0 floating PS
Survey HV PS
Combiner functionalities
Commune lines between crates
COMB 2
Open drain lines
COMB 1
COMB 3
Comb 1
Comb 2
Comb 2
release line release line release line
Begin test
Wait state
Task :
1) Synchronize the beginning of
the auto-test because it’s only
the COMB 3 which control the
HV PS for all the 3 creates.
2) Other task ?
Combiner prototypes and production test
A.
FIRST VERSION PROTOTYPE
As fast as possible on production with test points as much as
possible on the analog lines.
=> Functional test of these prototypes.
B.
EVALUATION
modification of the JTAG test developed for the DAB (60%
coverage on the DAB) and/or use of a test board & JTAG (90%
coverage on the DAB).
Visual & functional test for the analog parts.
C.
NEW PROTOTYPES
D.
TEST DEVELOPMENT
E.
PRODUCTION