Download Lecture 14

14. Introduction to Digital Logic Families
14.1
14.2
14.3
14.4
14.5
14.6
Digital Logic Gates
nMOS Logic Families
Dynamic MOS Logic Families
CMOS Logic Families
TTL Logic Families
ECL Logic Families
1
EE3601-14
Electronics Circuit Design
14.1 Digital Logic Gates
•Basic logic gates are summarized below. Note that logic circuits are
represented in the forms :•1.
Logic Symbol
•2.
Logic Equation
•3.
Truth Table
•4.
Timing Diagram
symbol and eqation
Buffer
A
QA
A
truth table
Q
0 0
1 1
output is the same as input
alternate gate
timing diagram
A
1
0
Q
1
0
t
t
Parallel Input OR \ AND
A
Inverter
A
A
QA
output is the reverse of input
Q
0 1
1 0
1
0
Bubbled Buffer
t
Q
1
0
EE3601-14
Electronics Circuit Design
QA
A
A
A
A
QA
t
Parallel Input NOR \ NAND
2
A
OR
A
B
Q  A +B
output is '1' if '1' is present at any input
A
B
Q
0
0
1
1
0
1
0
1
0
1
1
1
t
B
Bubbled NAND
t
Q
t
A
NOR
A
B
Q  A +B
output is '0' if '1' is present at any input
A
B
Q
0
0
1
1
0
1
0
1
1
0
0
0
t
B
Bubbled AND
t
Q
EE3601-14
Electronics Circuit Design
t
3
A
A
B
AND
QA B
output is '0' if '0' is present at any input
NAND
A
B
QA B
output is '1' if '0' is present at any input
t
A
B
Q
B
0
0
1
1
0
1
0
1
0
0
0
1
Q
A
B
Q
0
0
1
1
0
1
0
1
1
1
1
0
Bubbled NOR
t
t
A
t
B
Bubbled OR
t
Q
t
EE3601-14
Electronics Circuit Design
4
A
EX-OR
A
B
Q  A B
Q  AB AB
output is '0' if the inputs are equal
A
B
Q
0
0
1
1
0
1
0
1
0
1
1
0
AND \ Bubbled AND
t
B
t
Q
A
B
Q  AB AB
t
A
EX-NOR
A
B
Q  A B
Q  A B A B
output is '1' if the inputs are equal
A
B
Q
0
0
1
1
0
1
0
1
1
0
0
1
OR \ Bubbled OR
t
B
t
Q
t
EE3601-14
Electronics Circuit Design
A
B
Q  A B A B
5
14.2 nMOS Logic Families
nMOS and pMOS, how they works
pMOS will open or Qp (off) when
VGS ≥ 0 (zero or positive)
5V
V
=0 +5
V GS S
QP (off)
G
5V
V GS
V
>0S
G
D
D
G
5V
QP (off)
QP (off)
D
D
D
D
-5V
QP (on)
G
0
Qn (on)
0V
S
+5
QP (on)
G
D
D
D
D
D
S
S
Qn (off) 0V
=0
V
5V
Qn (off)
G
S
S
V
0
0V
V
=-5 S +5
V GS
D
G
≤0
nMOS will conduct or Qn
(on) when VGS > 0 (high)
VG
S
5V
-5V
S
V 0V
=-5 S
S
VG
S
+5
VG
=+
5V
0
S
Qn (on)
S
=+
S
S
G
VG
VG
Qn (on)
0V
0
pMOS will conduct or Qp (on)
when VGS ‹ 0 (negative)
0
Qp (on)
+5
Qn (off)
nMOS will open or Qn (off) when
VGS ≤ 0 (zero or negative)
EE3601-14
Electronics Circuit Design
nMOS NOR gate, how it works
nMOS “NOR” gate
VDD
VDD
Qn1
Output
Qn1
Qn2
A
Output
Qn3
B
A
Qn2
B
Qn3
Whenever Gate is 1(>0) Qn will conduct (=on)
Whenever A or B is 1 Qn will conduct (=switch will close)
Whenever Gate is 0(=0) Qn will open (=off)
Qn1 Gate is always 1(=Vcc) and will be on all the
time acting as a resistance to pass the current for
any of the two transistors below
A
B
Qn2
Qn3
Output
A
0
0
1
1
0
1
0
1
off
off
on
on
off
on
off
on
(=VDD)1
(=0) 0
(=0) 0
(=0) 0
B
Output
Any logic 1 present at input, output is zero
= NOR logic
EE3601-14
Electronics Circuit Design
7
Example: Draw nMOS “Inverter” gate and show how it works
A
Output
VDD
VDD
Qn1
Qn1
Output
Output
Qn2
A
A
Qn2
Whenever A is 1 Qn2 will conduct (=switch will close)
Qn1 Gate is always 1(=Vcc) and will be on all the
time acting as a resistance to pass the current for
transistor below
A
Qn2
Output
0
1
off
on
(=VDD)1
(=0) 0
EE3601-14
Electronics Circuit Design
Example: Draw nMOS “OR” gate and show how it works
A
Output
B
VDD
VDD
VDD
VDD
Qn4
Qn4
Qn1
Y
Output
Qn1
Output
Qn5
Y
Qn2
A
B
Qn3
Y
Qn5
Qn3
B
A
Qn2
Whenever A or B is 1 Qn will conduct (=switch will close)or Y=0
When Y is 0 Qn5 will open (=switch will open)or Output=1
When Y is 1 Qn5 will conduct (=switch will close)or Output=0
A
0
0
1
1
B
0
1
0
1
Qn2
off
off
on
on
Qn3
Y
Qn5
off
on
off
on
(=VDD)1
(=0) 0
(=0) 0
(=0) 0
on
off
off
off
Output
(=0) 0
(=VDD)1
(=VDD)1
(=VDD)1
A
B
Any logic 1 present at input, output is 1 = OR logic
EE3601-14
Electronics Circuit Design
Y
Output
nMOS NAND gate, how it works
VDD
VDD
Qn1
Qn1
Output
Output
Qn2
A
A
Qn2
B
Qn3
Qn3
B
Whenever A or B is 1 Qn will conduct (=switch will close)
A
B
Qn2
Qn3
0
0
1
1
0
1
0
1
off
off
on
on
off
on
off
on
Output
(=VDD)1
(=VDD)1
(=VDD)1
(=0) 0
A
B
Any logic 0 present at input, output is 1 = NAND logic
EE3601-14
Electronics Circuit Design
Output
14.3 Dynamic MOS Logic Families
When power consumption and physical size are prime design
consideration, as in digital watches and calculators, Dynamic MOS logic
is the one to meet those requirements.
Power consumption is minimized by relying on the inherent capacitance
of MOS transistors to store logic levels (to remain charged or
discharged) and by using clock signals to turn on transistors for very
brief interval of time only.
nMOS gate with Substrate grounded, is a fundamental component of
Dynamic logic circuits. It is completely symmetrical Drain and Source
terminals are indistinguishable. Current can flow in either direction
through the device. They can be named terminal 1 and 2 and C1 and C2
are the capacitance at each terminal.
1
2
C1
C2
G
EE3601-14
Electronics Circuit Design
Dynamic MOS, how it works
* When “G” is low nMOS will be off and no current will pass through it
1
1
2
C1
Hi
Or
Low
C2
2
C1
Hi
Or
Low
C2
G
G
When G is Lo nMOS is off no matter what
the level of C1 or C2 is
C1 discharges into C2
transfering the Hi from 1 to 2
1
Hi
2
Lo
C2 discharges into C1
transfering the Hi from 2 to 1
Lo
1
2
+
Hi
+
0
G
S>
C2
>0
G
C1
S
V
C2
VG
C1
G
Hi
Hi
When both C1 and G are Hi
When both C2 and G are Hi
* When “G” is high nMOS will be on and Hi will pass through it to Lo capacitor
EE3601-14
Electronics Circuit Design
Dynamic MOS Inverter , how it works
Whenever Gate of nMOS is 1(>0) Qn will conduct (=on)
Then transfer of charge Lo or Hi from one terminal
to other terminal will take place
Whenever Gate of nMOS is 0 (=0) Qn will open (=off)
There will be no transfer of Lo or Hi from one terminal to the
other
Vin
1
0
You have to
use 2 clocks
to invert 0
to 1
F1
VDD
Qn1
F1
F2
Qn3
You have to
use 2 clocks
to invert 1
to 0
at t1 F1= 1 then Vin(=Lo) will be inverted at VC1 (=Hi)
Output
Qn2
C1
C2
VC1 at t2 F2= 1 then VC1 (=Hi) will be transferred to VC2(=Hi)
Vin
F2
Whenever F1 = 1 C1 will be invert of Vin
Whenever F2 = 1 C1 and C2 will transfer Hi
from one another
at t3 F1= 1 then Vin(=Hi) will be inverted at VC1 (=Lo)
VC2
1
VDD
F1
t1
Qn2
C1
t3
t4
Output
Qn3
Vin
t2
at t4 F2= 1 then VC1 (=Lo) will be transferred to VC2(=Lo)
F2
Qn1
0
C2
EE3601-14
Electronics Circuit Design
13
Dynamic MOS - NOR , how it works
VDD
VDD
Qn1
F1
F1
Qn4
F2
Qn1
Output
Qn3
Qn2
A
C1
B
C2
Output
Qn4
A
Qn2
B
Qn3
C1
C2
F2
Whenever F1 = 1 C1 will be NOR logic of A,B
Whenever F2 = 1 C1 logic will transfer to C2
Input any 1
present
Output = 0
F1 F2
After 2 clocks
EE3601-14
Electronics Circuit Design
14
Dynamic MOS - NAND , how it works
VDD
VDD
Qn1
F1
F1
Qn4
F2
Qn1
Output
Qn2
A
C1
C2
Output
Qn4
A
Qn2
B
Qn3
C1
C2
F2
Qn3
B
Whenever F1 = 1 C1 will be NAND logic of A,B
Input any 0
present
Output = 1
Whenever F2 = 1 C1 logic will transfer to C2
F1 F2
After 2 clocks
EE3601-14
Electronics Circuit Design
15
HW on Dynamic MOS
1(a) Dynamic MOS circuit shown below, what are the logic obtained at points K,L,M
and Output after F1 and after F2? Fill up the logics (1 or 0) in the following
table.
(b) What is the overall logic that can perform by this given circuit?
(c) Draw equivalent switching circuit and logic symbol of this circuit.
A
B
0
0
0
1
1
0
1
1
K
after
L
after
F1
M
after
F2
F1
Output
After
F2
VDD
VDD
F1
Qn1
F1
Output
M
K
L
F2
A
F2
B
EE3601-14
Electronics Circuit Design
16
14.4 CMOS Logic Families
nMOS has disadvantage having delay when switch on and off due to one
upper nMOS acting as resistive load when output changing from Lo to Hi
and also lower nMOS acting as small R when output changing from Hi to
Lo. See below.
VDD
VDD
R
charge
discharge
Output
Output
Input
Hi
Lo
Hi
Input
C
C
Hi
no
delay
delay
Lo
no
delay
r
Lo
delay
nMOS Inverter produce delay at the output
EE3601-14
Electronics Circuit Design
CMOS has no or little delay when switch on and off due to one upper
pMOS acting as switch when output changing from Lo to Hi and also
lower nMOS acting as switch when output changing from Hi to Lo. See
below.
Switch but
no R
VDD=1
VDD=1
Qp
Qp
charge Output
1
Hi
0
Input
Hi
Lo
Input
C
Qn
1
Hi
Lo
no
delay
discharge
Output
Qn Hi 0
C
No R
Lo
Lo
No delay
CMOS Inverter produce no significant delay at the
output due to switching property of both MOSFET
EE3601-14
Electronics Circuit Design
CMOS - Inverter , how it works
VDD
VDD
Whenever A is 0 VGS of Qp < 0 (Qp=on)
and VGS of Qn =0 (Qn=off) then Output=VDD
Qp
A=0
Output
VDD
A=0
Qn
Output
A
VDD
Qn
Whenever A is 1 VGS of Qp = 0 (Qp=off)
and VGS of Qn > 0 (Qn=on) then Output=0
A=1
A
Output
0
1
VGS(p)
Qp
<0
on
=0
off
EE3601-14
Electronics Circuit Design
VGS(n)
=0
>0
Qn
Output
off
on
(=VDD)1
Qp
Output
0
A=1
A
Qp
Qn
(=0) 0
19
CMOS – NAND gate , how it works
VDD
QpA
VDD
Gate of Qp = 0 (Qp=on)
QpB
Gate of Qp > 0 (Qp=off)
Output
Qn is in series and Qp is in parallel = NAND
QnA
A
Gate of Qn > 0 (Qn=on)
QnB
Gate of Qn = 0 (Qn=off)
B
VDD
A=0 QpA
B=0
VDD
A=0 QpA
QpB
B=1
B=0
QnA
QnB
A=1
QpB
Output
=1(VDD)
A=0
QpA
B=0
Output
=1(VDD)
A=0
B=1
VDD
VDD
QnA
QnB
A=1
QpB
QpA
B=1
QpB
Output
=0
Output
=1(VDD)
A=1
B=0
When zero is present at any Input, Output will be 1
QnA
A=1
QnA
QnB
B=1
QnB
When 1 present at both Input, Output will be 0
EE3601-14
Electronics Circuit Design
20
CMOS – NOR gate , how it works
VDD
Gate of Qp = 0 (Qp=on)
QpA
Gate of Qp > 0 (Qp=off)
QpB
Qn is in Parallel and Qp is in series = NOR
B
QnA
Gate of Qn > 0 (Qn=on)
Output
QnB
Gate of Qn = 0 (Qn=off)
A
VDD
A=1
B=1
VDD
QpA
A=1
QpB
B=1
QpA
A=0
QpB
Output
=0
A=1 QnA
B=1 QnB
B=1
QpA
B=0 QnB
A=0
QpB
Output
=0
A=1 QnA
VDD
VDD
B=0
QpA
QpB
Output
=1(VDD)
Output
=0
A=0
QnA
When 1 present at any Input, Output will be 0
A=0 QnA
B=1 QnB
B=0 QnB
When 0 present at both Input, Output will 21
be 1
EE3601-14
Electronics Circuit Design
14.5 TTL Logic Families
Transistor – Transistor Logic (TTL)
Advantage of TTL logic circuit is that input current is zero at high (5V) input and it is reverse
at low (0V) input. Because of this many TTL gates can be fan-out to output of one gate.
TTL Inverter gate , how it works
A=1(5V)
Q1
1. A = 1 (high = 5V) then (VBE1 = 0)
A=0
Q2
A
Q1
Q2
Y
0 (0V)
on
off
1 (5V)
1 (5V)
off
on
0 (0V)
IC2RC2=0
Y=1(5V)
Q2
IC1=-IB2
1. A = low = 0V then
2. Q1 opens
2. Q1 conducts
3. But PN junction current from Base to
Collector of Q1 (ID1 = IB2 flows)
4. Q2 conducts and produces = IC2RC2 drop
3. IB2 flows out of Q2
5. If RC2 is chosen so that IC2RC2 drop = 5V
then Y=0
6. A = 1 is inverted to Y = 0
EE3601-14
VCC=5V
Q1
E+
Y=0
ID1=IB2
IC2=0
IB1
IC2RC2=5V
VB
E=
0
IB1=0
IC2
-VB
VCC=5V
(VBE1 = 0.7V)
4. Q2 opens then IC2RC2 no drop
5. Y = 1 (high= 5V)
6. A = 0 is inverted to Y = 1
Electronics Circuit Design
22
TTL Inverter gate (open Collector) , how it works
A=0
Y=F
(Floating)
Q2
IC2
IB1=0
A=1(5V)
Q3(off)
IC1=-IB2
ID1=IB2
0
Q1
VCC=5V
IC2=0
E=
-VB
E+
IB1
VB
VCC=5V
Q3(On)
E+
-VB
Q1
Q2
Q3
Y
0 (0V)
on
off
off
F (Float)
1 (5V)
off
on
on
0 (0V)
-
A
E
A=0
IC2RE2=0.7V
VB
+
0
=
E
VCC=5V
Y=0
Q1
VB
IC2RE2=0V
Q2
VCC=5V
IB1
Q1
IC2=0
R=pull up
resistor
Q2
Q3(off)
IC1=-IB2
VB
A
Q1
Q2
Q3
Y
0 (0V)
on
off
off
1 (5V)
1 (5V)
off
on
on
0 (0V)
0
=
E
IC2RE2=0V
Y=1(5V)
EE3601-14
Open Collector output (= 0V or 5V)
with external pull up resistor Electronics Circuit Design
TTL –NAND gate (open Collector), how it works
VCC=5V
VCC=5V
A=0
B=0
A=0
B=1
-VB
E+
IB1
A=1
B=0
Q1(on)
IC2=0
Q2(off)
Q3(off)
IC1=-IB2
Y=1(5V)
VB
When Zero present
at any input
R=pull up
resistor
0
=
E
IC2RE2=0V
VCC=5V
BE
=
0
VCC=5V
IC2
Q1(off)
Q2(on)
V
A=1
B=1
ID
Q3(on)
Y=0(0V)
VB
ID=IB2
R=pull up
resistor
7
0.
=
E
When One present
at both input
IC2RE2=0.7V
A
B
Q1
Q2
Q3
Y
0
0
on
off
off
1 (5V)
0
1
on
off
off
1 (5V)
1
0
on
off
off
1 (5V)
1
1
off
on
on
0 (0V)
EE3601-14
Electronics Circuit Design
TTL –NAND Totem pole gate, how it works
VCC=5V
IB3=0
A=0
B=0
A=0
B=1
Q1(on)
-V
BE +
IB1
A=1
B=0
Q4(on)
Q2(off)
Y=1(5V)
IC1=-IB2
VB
When Zero present
at any input
Q3(off)
This gate works faster because of Q4
When it is “on” has no resistive delay. Q4
Acts as a switch (no delay)
E
0
=
IC2RE2=0V
VCC=5V
IC2
ID=IB2
Q1(off)
=0
Q2(on)
V BE
A=1
IB3=0
Q4(off)
Y=0(0V)
Q3(on)
VB
B=1
When One is
present at both
input
7
0.
=
E
IC2RE2=0.7V
Diode at the Emitter of Q4
When it is “on” has an extra drop of 0.7V
so that Base of Q4 is 1.4V higher than Y
which will secure Q4 not to conduct when
Q3 is “on”
A
B
Q1
Q2
Q3
Q4
Y
0
0
on
off
off
on
1 (5V)
0
1
on
off
off
on
1 (5V)
1
0
on
off
off
on
1 (5V)
1
1
off
on
on
off
0 (0V)
EE3601-14
Electronics Circuit Design
TTL –OR gate, how it works
VCC=5V
A=1
Q1
(off)
B=1
A=1
Q1
(on)
Q3
IC5
(on/off/on)
Q2
Q4
(on/on/off)
Q1
(off)
B=1
1. Q1 or Q2 is “off” when A or B is 1 (5V)
2. when Q1 or Q2 is “off” Q3 or Q4 is “on”
Q7(on)
B=0
Q2
(off)
IB7
IB6=0
Q6(off)
Q5(on)
Q2
(on)
VB
Q2
(off)
A=0
Q1
Q8(off)
3. Whenever Q3 or Q4 is “on” VBE of Q5=0.7V
4. when VBE of Q5=0.7V,Q6 or Q8 is “off” and Q7 is “on”making output Y=1(5V)
5. Then when A or B is 1 (5V) output Y=1(5V)ÞOR gate
0
=
E
IC6RE6
=0V
IC5RE4
=0.7V
Y=1(5V)
VCC=5V
IB6
Q1(on)
IC2
Q3(off)
IB7=0
A=0
When “Zero”
is present at
both input
Q6(on)
Q2(on)
Q4(off)
VB
Q8(on)
3. Whenever Q3 and Q4 are “off” VBE of Q5=0V
4. when VBE of Q5=0V,Q6 and Q8 are “on” and Q7 is “off”making output Y=0(0V)
7
0.
=
E
IC6RE6
=0.7V
IC5RE4
=0V
2. when Q1 and Q2 is “on” Q3 and Q4 are “off”
Y=0(0V)
Q5(off)
B=0
1. both Q1 and Q2 is “on” when A or B is 0 (0V)
Q7(off)
5. Then only when A and B is 0 (0V) output Y=0(0V)ÞOR gate
A
B
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Y
0
0
on
on
off
off
off
on
off
on
0 (0V)
0
1
on
off
off
on
on
off
on
off
1 (5V)
1
0
off
on
on
off
on
off
on
off
1 (5V)
1
1
off
off
on
on
on
off
on
off
1 (5V)
EE3601-14
Electronics Circuit Design
TTL –EXOR gate, how it works
1. A to Q7 Emitter and B to Q7 Base are both inverters
2. If A and B are both 1 or 0 , Q7 Emitter and Q7 Base will be both 0 or 1
3. When Q7 Emitter and Q7 Base are both 0 or 1, VBE (Q7) = 0 making Q7 off.
4. When Q7 off, Q8 also off. making Q9 Base High = 1,
5. Q9 base to output Y is inverter therefore Y = 0
6. If Y = 0 when two inputs A and B are equal it is (EX-OR LOGIC)
7. But when A=1 and B=0, Q7 Emitter=0 and Base=1 making Q7 to
conduct and then Q8 to conduct. Then Q9 Base Low = 1, and Y=1
8. But when A=0 and B=1, Q7 Emitter=1 and Base=0
making Q7 to off but
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then Q8 to conduct. Then Q9 Base LowElectronics
= 1, and Y=1
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TTL Device Listings
Type Number
Description
7400
Quad 2-input NAND
7401
Quad 2-input NAND open collector
7402
Quad 2-input NOR
7403
Quad 2-input NOR, open collector
7404
Hex inverter
7405
Hex inverter, open collector
7406
Hex inverter, open collector to 30 (V)
7407
Hex buffer/driver, open collector to 30 (V)
7408
Quad 2-input AND
7409
Quad 2-input AND, open collector
7410
Triple 3-input NAND
7411
Triple 3-input AND
7414
Hex Schmitt-tngger inverters
7420
Dual 4-input NAND
7421
Dual 4-input AND
7427
Triple 3-input NOR
7430
8-input NAND
7432
Quad 2-input OR
7486
Quad 2-input XOR
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14.6 ECL Logic Families
•The Emitter Coupled Logic (ECL) family operates at the highest speed of all of the logic
families studied in this text.
•This happens because none of the transistors are operated in saturation.
•Since propagation delays of 1 to 2 ns are achievable, ECL is useful in highspeed applications such
as radar signal processors, computers, and data transmission.
•There are fewer chips in the ECL family than in TTL
Differential Amplifier
•When one source voltage is larger than the
other, the transistor associated with that higher
voltage will be ON and the other transistor will
be OFF
•ON transistor will have low collector voltage
and the OFF transistor will have high collector
voltage
•Therefore output voltage of the BJT with
larger input source will have smaller value which
is INVERTER LOGIC
•But output voltage at the collector of the other
BJT will have larger value in which case is
BUFFER LOGIC
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Emitter Coupled Logic
• The differential amplifier with input voltages
are as follows:
•Input voltage source voltage is applied to one of
the transistor and the other transistor input
voltage is a fixed internally generated reference
voltage of (-1.3V)
• Collector of the input BJT is the Inverter
output and the collector of the other BJT is the
Buffer output
•Logic level of the ECL is (-0.9V) for logic high
•Logic level of the ECL is (-1.7V) for logic low
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When Input logic is high ( -0.9V)
3. When VB1 = -0.9V (high)
1. VB1 = -1.3V reference
4. VB1X= -0.9-(-5.2) = 4.3V
5. But VB2X= -1.3-(-5.2) = 3.9V
2. -Vcc = -5.2V at point “X”
6. VB1 > VB2 then Q1 will be ON making VBE1=0.8V
7. VR3=4.3-0.8=3.5V
8. Therefore VBE2=3.9-3.5=0.4V (cutoff Q2VBE < 0.5V)
9. Q2 will be OFF = VC2 is high = Buffer Output
10. Q1 will be ON & VC1 is low = Inverter Output due to drop at R1
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When Input logic is low ( -1.7V)
10. VC2 is low due to drop at R2
3. When VB1 = -1.7V (low)
1. VB1 = -1.3V reference
4. VB1X= -1.7-(-5.2) = 3.5V
5. But VB2X= -1.3-(-5.2) = 3.9V
2. -Vcc = -5.2V at point “X”
6. VB1 < VB2 then Q2 will be ON making VBE2=0.8V
7. VR3=3.9-0.8=3.1V
8. Therefore VBE1=3.5-3.1=0.4V (cutoff Q1 VBE< 0.5V)
9. Q1 will be OFF = VC1 is high = Inverter Output
10. Q2 will be ON & VC2 is low = Buffer Output due to drop at R2
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Four-input ECL OR/NOR logic gate
0V
Emitter Follower
-0.1
Differential Amplifier
-0.1
-0.9
-0.9
-1.3V
-0.9(high at C )
-0.9(high)
-1.7V(low)
-5.2V
If any of the input A or B or C or D is high, Q5 will be OFF making less drop at RC2
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Two-input ECL OR/NOR logic gate
0V
Emitter Follower
Differential Amplifier
-0.9
-0.1
-0.1
-0.9
-0.9(high) OR
-1.7V(low)NOR
-1.3V
-5.2V
-0.9(high)
If any of the input A or B is high, Q3 will be OFF making less drop at R5
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ECL Device Listings
Type Number
Description
10100/10500
Quad 2-input NOR with strobe
10101/10501
Quad OR/NOR
10102/10502
Quad 2-input NOR
10103/10503
Quad 2-input OR
10104/10504
Quad 2-input AND
10105/10505
Triple 2-3-2-input OR/NOR
10106/10506
Triple 4-3-3-input NOR
10107/10507
Triple 2-input exclusive OR/exclusive NOR
10109/10509
Dual 4-5 input OR/NOR
10110
Dual 3-input 3-output OR
10111
Dual 3-input 3-output NOR
10113/10513
Quad exclusive OR
10117/10517
Dual 2-wise 2-3-input OR-AMD/OR-ANDinvert
10118/10518
Dual 2-wide 3-input OR-AND
10119/10519
4-wide 4-3-3-input OR-AND
10121/10521
4-wide OR-AND/OR-AND-invert
10123
Triple 4-3-3-i bus driver
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