Download Lecture 14

CS 3501 - Chapter 3 (3A and 10.2.2)
Part 7 of 8
Dr. Clincy
Professor of CS
Dr. Clincy
Lecture
Slide 1
Sequential Circuits Vs Combinational Circuits
New Input
Current
State or
Output
Current State or output
of the device is
affected by the
previous states
Flip Flops
Previous
State or
Output
Circuit
Sequential Logic
Previous
State or
Output
New Input
Dr. Clincy
Circuit
Combinatorial or Combinational Logic
Current
State or
Output
Current State or output
of the device is only
affected by the current
inputs
Lecture
2
NOTE
Your book doesn’t do a good job in
showing you how to derive or design
sequential circuits (using state and state
assignment tables) – the next 2 lectures
will do so – please pay close attention to
the next 2 lectures in understanding how
to derive sequential circuits.
Dr. Clincy
Lecture
Slide 3
Clock - Sequential Circuits
• State changes are controlled by clocks (clock ticks).
• Circuits can change state on the rising edge, falling
edge, or when the clock pulse reaches its highest
voltage – edge triggered.
• Level-triggered circuits change state when the clock
voltage reaches its highest or lowest level.
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Lecture
4
Current
State or
Output
S and R stand for set and reset respectively
constructed from a pair of cross-coupled
NOR gates
the stored bit is present on the output
marked Qa
If S and R inputs are both low, maintains
the Qa and Qb in constant state,
If S (Set) is pulsed high while R is held
low, then the Qa output is forced high,and
stays high even after S returns low;
if R (Reset) is pulsed high while S is held
Dr. Clincy
low, then
the Qa output is forced low, and
stays low even after R returns low.
New Input
•
•
•
•
•
•
Notice how the output feeds
the input
Flip Flops
Previous
State or
Output
Circuit
Flip Flops - Sequential Circuits
Previous
State or
Output
Lecture
Think of: Given R=0 and Qa=0,
what can this be ?
5
Gated SR Latch or Flip Flop
• The time at which the latch
is SET or RESET is
controlled by a CLOCK
input
• Called Gated SR Latch
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Lecture
6
Gated D Latch
• Inputs S and R are derived
from a single input D
• Clock pulse controls when
the output is triggered
• Samples the D input at the
time the clock is HIGH and
stores that info until the
next clock pulse
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During the time the clock is high, the
input changed, causing the output to Lecture
change – this is the problem
7
Potential Problem
• Thus far, the assumption
has been the inputs S and R
(or D) not changing while
CLK is HIGH
• What would happen if S, R
and/or D changed ? The
output would change
immediately
• This could be a problem
• To fix this (next ppt)
Dr. Clincy
During the time the clock is high, the
input changed, causing the output to Lecture
change – this is the problem
8
Two Flip Flops Used To Fix Clock Issue
FF1
D
Clock
FF2
D
Q
Clk
Q
Qm
D
Q
Clk
Q
Qs
Q
Q
Use 2 D flip flops – the FF2 clock is set to zero – therefore, if there was a change in FF1 input, D, it wouldn’t
effect the FF2 Q value – FF2 holds the value
(a) Circuit
Clock
D
Qm
Q = Qs
Clock’s negative edge causes change
(b) Timing diagram
D
The arrow only symbolizes “positive
edge” clock - the arrow with the NOT
symbolizes “negative edge” clock
Q
Q
(c) Graphical symbol
Dr. Clincy
Lecture
• If D changes while FF1 CLK is
HIGH, Qm changes immediately Qs stays the same because FF2
CLK=0
• Once the CLK goes LOW, FF2
reacts because its CLK=1 – so it
thens reflects D
9
T Flip Flop
T Flip Flops are good for
counters – changes its
state every clock cycle, if
the input, T, is 1
• Positive-edge triggered flip flop
• Since the previous state of Q was 0,
it complements it to 1
Dr. Clincy
Lecture
10
JK Flip Flop
Combines the behavior of
the SR and T flip flops
• First three entries are the same
behavior as the SR Latch (when
CLK=1)
• Usually the state S=R=1 undefined
– for the JK Flip Flop, for J=K=1,
next state is the complement of the
present state
Can store data like a D Flip Flop or can tie J & K inputs together and use to build counters (like a T flip flop)
Dr. Clincy
Lecture
11
Registers and Shift Registers
A Flip Flop can store ONE bit – in being able to handle a WORD, you will need a number
of flip flops (32, 64, etc) arranged in a common structure called a REGISTER.
• All flip flops are synchronized by a common clock
• Data written into (loaded) flip flops at the same time
• Data is read from all flip flops at the same time
F1
F2
F3
In
Clock
D
Q
Q
D
Q
D
Q
Q
Q
F4
D
Q
Out
Q
A simple shift register.
• Want the ability to rotate and shift the data
• Clock pulse will cause the contents of F1, F2, F3 and F4 to shift right (serially)
• To do a rotation, simply connect OUT to IN
Dr. Clincy
Lecture
12
Registers and Shift Registers
• Can load either serially or in parallel
• When clock pulse occurs,
• Serial shift takes place if Shift’/Load=0 or
• if Shift’/Load=1, parallel load is performed
Dr. Clincy
Lecture
13
Counters
1
T
Clock
Q
T
Q
• 3-stage or 3-bit counter constructed
using T Flip Flops
• With T Flip Flips, when input T=1, the
flip flop toggles – changes state for
each successive clock pulse
• Initially all set to 0
• When clock pulse, Q0=1, therefore
Q’=0 disabling Q1 and Q1 disables Q2
(have 1,0,0)
• For the 2nd clock pulse, Q0=0, therefore
Q’=1, causing Q1=1 and therefore
Q’=0 disabling Q2 (have 0,1,0)
• For the 3rd clock pulse, Q0=1, therefore
Q’=0 disabling Q2 and therefore
disabling Q3 (have 1,1,0)
• Etc….
Q
T
Q
Q0
Q
Q
Q1
Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count
0
1
2
3
4
5
6
7
0
(b) Timing diagram
Figure A.35. A 3-bit up-counter.
LSB
000
001
Hmmm
010
011
100
Dr. Clincy 101
110
111
Lecture
14
Called a Ripple Counter