Download Peripherals operate in I 2 C or clocked - Renesas e

Course Introduction

Purpose:
 This course provides an overview of the serial communication interfaces
and data converters on devices in the SH-2 and SH-2A families of 32-bit
RISC microcontrollers, which are members of the SuperH™ series

Objectives:
 Gain a basic knowledge of the features and operation of the serial
communication interface (SCI)
 Discover the extra capabilities of the SCIF version
 Learn about synchronous serial interface options
 Learn basic facts about analog-to-digital converter (ADC or A/D) and
digital-to-analog converter (DAC or D/A) peripherals

Content:

Learning Time:
 22 pages
 3 questions
 20 minutes
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© 2009, Renesas Technology America, Inc., All Rights Reserved
SuperH Peripheral Functions
 Microcontrollers for embedded
system applications require
extensive on-chip peripherals to
 Minimize system chip count
 Reduce overall system cost
 Facilitate small system size, etc.
 Built-in peripheral functions
must
 Provide required capabilities
SH7047 SuperH Series Microcontroller
SH-2 SuperH
32-bit RISC CPU
Data Transfer
Controller
Motor Management
Timer
Bus State
Controller
Watchdog Timer
Interrupt Controller
Compare-Match
Timer
User Break
Controller
A/D Converter
D/A Converter*
 Maintain a basic commonality
within product family, if possible
 Offer an acceptable cost-benefit
compromise, etc.
RAM
Multi-function Timer
Pulse Unit
 Deliver needed performance levels
 Offer design flexibility
Flash
Advanced User
Debugger
Bus
Interface
I/O
Ports
Serial
Communication
Interface
CAN Function
High-performance
User Debug Interface
Clock Pulse
Generator
* included on some SH-2 series devices, but not the SH7047
© 2009, Renesas Technology America, Inc., All Rights Reserved
Serial Communication Interface
 SuperH-series devices feature
two types of serial
communication interface:
 SCI on first-generation devices
 Serial communication interface
with FIFO (SCIF) as well on SH-2A
microcontrollers and newer
SH-2 devices
 16-stage FIFO
 Makes it possible to transmit and
receive data on each channel for
high-speed communication
 SCI and SCIF support
SCIF
asynchronous and clocked
synchronous serial
communication
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Serial Communication Modes
 Asynchronous mode provides
 7- or 8-bit data length
 1 or 2 stop bits
 Even, odd, or no parity
 Parity, framing and overrun
error detection
 Break detection (SH-2A)
 Up to 3Mbit/s operation
Data format in asynchronous mode
 Clocked synchronous mode
Data format in clocked synchronous mode
provides
 8-bit data length
 Overrun error detection
 Up to 5Mbit/s operation
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Full Duplex Communication
 SCI and SCIF offer full
duplex
communication,
allowing simultaneous
transmission and
reception
 Each channel has an
Independent baud rate
generator that uses
none of the
microcontroller’s
timer resources
 The interface supports
internal and external
clock sources
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Baud Rate/Bit Error Calculation
N=

x106 - 1
2n-1
64 x 2 x B
Async
N=

x106 - 1
2n-1
8x2 xB
Sync
 x 106
-1 x 100
Error (%) =
2n-1
(N+1) x 64 x 2 x B
When you choose a baud
rate, consider the
percentage error rate, too!
B: Bit rate (bit / s)
N: BRR setting for baud rate generator ( 0 to 255 )
: Operating Frequency
n: Baud rate generator input clock ( n = 0 to 3 )
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Generating Interrupts
 Four sources can trigger interrupts:
 Tx (FIFO) data empty
 Rx (FIFO) data full
 Receive error
 Break condition (SH-2A)
(Automatically enables)
 If a receive error occurs, it must be cleared before reception
can continue
 With FIFO you can
 Ascertain the quantity of Tx and Rx FIFO data in the buffers
 Keep track of the number of Rx errors
 SCIF can generate a timeout (DR) error in asynchronous
mode
 Rx and Tx interrupts can activate DMAC and DTC transfers
 SCI and SCIF can be put into standby mode to conserve
power
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© 2009, Renesas Technology America, Inc., All Rights Reserved
Modem Flow Control
SCIF in SH-2A devices can generate
modem control signals (/CTS, /RTS)
8
© 2009, Renesas Technology America, Inc., All Rights Reserved
PROPERTIES
On passing, 'Finish' button:
On failing, 'Finish' button:
Allow user to leave quiz:
User may view slides after quiz:
User may attempt quiz:
Goes to Next Slide
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At any time
After passing quiz
Unlimited times
I2C Interface and Peripherals
 I2C is a serial bus interface standard developed by Philips
Semiconductor
 Two SH-2 series I2C peripherals provide an I2C-compatible
bus interface
 IIC2 on earlier devices in the SH-2 series
 IIC3 on SH-2A microcontrollers and newer SH-2 devices
 Select I2C or clocked-synchronous serial formats
 Master and slave modes are supported
 Independent registers make possible continuous data
transmission and reception
 Shift register
 Tx data register
 Rx data register
Peripherals operate in I2C or
clocked synchronous mode
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© 2009, Renesas Technology America, Inc., All Rights Reserved
I2C Bus Format Features
 IIC2 and IIC3 peripherals can
 Automatically generate start and stop conditions
 Automatically transmit acknowledge bit
 Reception acknowledge levels are selectable
 IIC3 (on SH-2A and newer SH-2 devices) has a bit
synchronization/wait function in master mode that
 Monitors SCL per bit
 Synchronizes timing automatically
 Holds SCL low to wait
 Multiple interrupt sources include Tx empty, Tx end, Rx
data full, arbitration lost, NACK detection, and stop
condition detection
 Tx data empty or Rx data full can activate SH-2A DMAC
 Direct bus drive is provided
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Clocked Synchronous Serial
 This format
 Adds more synchronous serial communication channels
 Supports multiple interrupt sources, including Tx data empty, Tx end,
Rx data full, and overrun error
 Tx data empty and Rx data full interrupts can activate
DMAC interrupt handling on SH-2A series microcontrollers
 SDA outputs data in synchronization with the SCL clock
SCL
SDA
Bit 0
Bit 1
Bit 2 Bit 3
Bit 4 Bit 5
Bit 6 Bit 7
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IIC3: I2C Interface on SH-2A MCU
IIC3 External Circuit Connections
IIC3 Implementation
13
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Synchronous Serial Comm. Unit
SSU on the SH-2 series devices
 Communicates with clocked synchronous devices that use separate
input and output pins
 Works in standard clocked synchronous mode
 Supports master and slave modes of operation with internal or
external clock
 Has selectable clock polarity and phase
 Supports full duplex communication with 8-, 16-, and 32-bit-wide data
 Can be configured to send LSB or MSB first
 Provides interrupt sources: Tx end, Tx empty, Rx full, overrun, and
conflict errors
 Triggers DTC for interrupt handling
 Can be put into standby mode to conserve power
14
© 2009, Renesas Technology America, Inc., All Rights Reserved
PROPERTIES
On passing, 'Finish' button:
On failing, 'Finish' button:
Allow user to leave quiz:
User may view slides after quiz:
User may attempt quiz:
Goes to Next Slide
Goes to Slide
At any time
At any time
Unlimited times
Analog-to-Digital Converter
 This peripheral
 Converts analog voltages to numerical values
 Uses successive approximation with up to 12-bit resolution
 Supports up to 16 input channels
 Devices with 2 or 3 ADCs can make simultaneous conversions
on multiple channels
 Latest analog-to-digital converters offer
 As little as 1ms conversion time
 Individual channels with their own 16-bit result register
 Several operating modes are available:
 Single
 Multi (conversion on 1 – 4 or 1 – 8 channels)
 Scan (continuous conversion on 1 – 4 or 1 – 8 channels)
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ADC Features

Sample-and-hold function
 Samples input signal voltage

 Holds voltage constant during
conversion process
Conversion start methods
 Software
 MTU, MTU2, or MTU2S trigger
(MTU2S on SH-2A devices)



 External trigger input
Interrupt generated on
completion of A/D conversion
DMAC or DTC transfer
triggered on end of conversion
Module standby mode to save
power
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ADC Implementation
18
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ADC Conversion Errors
19
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Digital-to- Analog Converter
Features include
Bus Interface

Module Data Bus
 2 output channels
 8-bit resolution
AVCC
 10ms conversion time
(20pF load)
DA0

8-bit D/A
DA1
 Output voltage 0V to AVref

Internal
Data Bus
AVSS
D
A
D
R
0
D
A
D
R
1
D
A
C
R
AVref
DAC holds output voltage
constant, even in software
standby mode
Control Circuit
DACR:
D/A Control Register
DADR0: D/A Data Register 0; DADR1: D/A Data Register 1
DAC can be put in module
standby mode to
conserve power
20
© 2009, Renesas Technology America, Inc., All Rights Reserved
PROPERTIES
On passing, 'Finish' button:
On failing, 'Finish' button:
Allow user to leave quiz:
User may view slides after quiz:
User may attempt quiz:
Goes to Next Slide
Goes to Slide
At any time
After passing quiz
Unlimited times
Course Summary
 Serial communication interfaces
 Analog-to-Digital converter
 Digital-to-Analog converter
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© 2009, Renesas Technology America, Inc., All Rights Reserved