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WEBENCH Power Designer/Architect 1 The WEBENCH Tool Suite Altera PowerPlay Power Architect & FPGAs FPGA/Power Architect WEBENCH Visualizer WEBENCH Power Designer 2 Beginning To End: Design And Prototyping 1. Choose a Part 2. Create a Design 3. Analyze a Design 4. Build It! Custom Prototype Kit Overnight Enter Specifications Optimize for Footprint and Efficiency, Use Graphs to Visualize Design Generate Schematic/ Electrical Analysis Select Part Generate Layout/ Thermal Analysis 3 Prototype Two Ways to Access WEBENCH® Designer • • . 4 Use the entry panel on http://www.national.com OR Go to the product folder for a part WEBENCH Navigation Navigation Icons WEBENCH Tools: Power LED LED Architect Power Architect FPGA Power Architect 5 5 Create and View Design Dashboard 1) Graphs 2) Schematic 3) Optimization 4) Operating values 5) BOM 6) Reporting Simulation Controls Inputs Op Vals Charts Schematic Optimization Op Vals BOM/Change Components Build It® & Report 6 Schematic – Buck Converter Components: Input Capacitor Regulator with integrated FET Inductor Catch Diode Output Capacitor Feedback Network Input Load Feature Controls Current Path with Switch On Current Path with Switch Off 7 Visualize Behavior – Power Dissipation Efficiency = Pout / Pin Diode: Cout: Pin = Vout * Iout + Pdiss Isw*Vf *(1-DutyC) ICoutRMS2 * ESR Switch: DC: IswRMS2 * Rsw * DutyC AC: ½ * Vin * Isw * Inductor: Cin: ILRMS2 * DCR ICinRMS2 * ESR (Trise + Tfall)/Tsw Quiescent: Iq * Vin 8 FET Selection: AC Loss • PswAC = ½ * Vdsoff * Idson * (trise + tfall)/Tsw Regions of power loss (V*I) Vsw Miller Plateau Miller Plateau Vdriver Vth Vth Isw Vg Vsw = -Vds Switch Off On Off Tfall Trise 9 FET Selection: AC Loss • PswAC = ½ * Vdsoff * Idson * (trise + tfall)/Tsw High Freq = High Loss Low Freq = Low Loss Regions of power loss (V*I) Vsw Miller Plateau Miller Plateau Vdriver Vth Vth Isw Vg Vsw = -Vds Switch Off On Trise Off Tfall 10 How To Reduce FET Power Loss • Choose a FET with low RdsOn • Choose a FET with low capacitance • Lower the switching frequency BUT • Lowering frequency affects the inductor selection • We want to keep the inductor ripple current constant – Because this changes the peak switch current and the Vout ripple 11 Inductor Current vs Switch Voltage Inductor Current Switch Voltage 12 Inductor Ripple Current On Time Voltage applied dI = (1/L)*V*dt Inductor Ripple Current (also determines peak switch current and Vout ripple) 13 Inductor Selection – Lower Frequency Higher frequency: On Time Voltage applied dI = (1/L)*V*dt Inductor Ripple Current (also determines peak switch current and Vout ripple) Lower frequency: Lower Frequency = Increased On Time = Increased Inductor Ripple Current = Increased Peak Switch Current and Increased Vout Ripple If L is kept constant, ILpp increases 14 Inductor Selection – Raise Inductance Higher frequency: On Time Voltage applied dI = (1/L)*V*dt Inductor Ripple Current (also determines peak switch current and Vout ripple) Lower frequency with higher inductance: Lower frequency: If L is kept constant, ILpp increases So we need to increase L 15 Effect Of Lower Frequency On Inductor • If we keep the inductor ripple current constant by increasing the inductance: – The inductor gets larger (more turns) – The inductor power dissipation goes up (longer wire) 16 Optimization – Efficiency vs Footprint Left side: Right side: Higher frequency Lower frequency Smaller footprint Lower resistance 17 Optimization Summary • To get high efficiency – Decrease frequency to reduce AC losses – Choose components with low resistance • To get small footprint – Increase frequency to reduce inductor size – Choose components with small footprint • Cost • These parameters are at odds with each other and need to be balanced for a designer’s needs • Tools are available to visualize tradeoffs and make it easier to get to the best solution for your design requirements 18 The WEBENCH Tool Suite Power Architect & FPGAs WEBENCH Visualizer WEBENCH Power Designer 19 WEBENCH VisualizerCalculates 50 Designs In 2 Seconds Recommended Solutions Charts 20 Calculated BOM Footprint, BOM Cost and Efficiency Footprint vs Cost vs Efficiency 21 Graphical Plot Gives At A Glance TradeOffs Click on square to resize the plot to full screen size Hover to see details Click and drag to zoom Change plot parameters Bubble Size = BOM Price 22 Why Are The Solutions Different? 23 Give The Customers What They Want: Best Efficiency, Footprint and BOM Cost • Default Setting: LM22676, 80%, 411mm2, $2.88 • Smallest Footprint: LM25011, 75%, 297mm2, $2.47 • Highest Efficiency: LM3150, 94%, 1320mm2, $6.77 • Comparing different designs up front, achieves better results than optimizing 1 part after creating a design 24 The WEBENCH Tool Suite Power Architect & FPGA Architect WEBENCH Visualizer WEBENCH Power Designer 25 Design This Power Supply In Seconds? Many Loads, Many Supplies • Core Supply [email protected] • FPGA IO [email protected] • Vcca [email protected] • Flash [email protected] • SDRAM [email protected] • CCD [email protected] • PLL [email protected] • Motor Control [email protected] • Miscellaneous [email protected] 9 Loads and 5 Voltages 26 Why Do Designers Use Reference Designs So Frequently For Complex FPGAs? • Cyclone IV GX - EP4CGX150 • User guide: 463 pages, 10MB • 20-30 pages of power details • Spartan-6 - XC6SLX100T Minutes, right? With Confidence? • 40+ separate reference guides and datasheets: ~2000 pages, 90MB • 15 pages critical for power details • Each specification includes challenging requirements and exceptions – Voltage, current, ripple, frequency, accuracy, soft start, supply isolation, and pin specific limitations • Every complete system has additional loads beyond the FPGA loads, adding more to the complexity 27 WEBENCH® FPGA Power Architect Select Device From List Add FPGA Configure Loads 28 Get FPGA Load Current From Vendor Estimation Spreadsheet: Xilinx Spreadsheet calculates the current 29 Update Load Current Into Preconfigured FPGA Dependency Template Voltage, Current, and Special Requirements Included For: • Max Voltage Ripple • Isolated Supplies • Soft Start Next • Post Supply Filters • LDO Preferred Add All Of Your Own Additional System Loads 30 Each Architecture Is Tuned With The WEBENCH Optimizer, Now For Systems Optimizer Dial 8000 Relative System Cost Size 2000 76% System Efficiency 31 92% WEBENCH FPGA Power Architect Selects The Best Solutions For Every Rail Intermediate Rail (12V) Loads Supply 2 (1.25V) Supply 3 (3.3V) Supply 4 (1.8V) Supply 5 (2.5V) 32 Presenting The User With The Intermediate Rail Options And Performance Trade-Offs Intermediate Rail Options Can Be Reviewed & Compared Quickly 12V 3V 5V No I-Rail 12V Lowest Cost 12V 23V 5V Smallest Footprint Highest Efficiency 33 Analyze Performance, Cost and Footprint for Selected Architecture Go Click on Each Supply To Display Detail 34 WEBENCH® FPGA Architect Leverages The WEBENCH Dashboard Click on Each Supply To Analyze Design 35 Advanced Tools Are Available For Further Exploration Share Design System Summary Optimizer Simulation Optimization Graphs Charts Drive Circuits Bill of Materials Prototyping System Op Vals Power Topology & Design Reports 36 Complete FPGA Power Supply Design Reporting – Automatic Generation Your Design From The Top: Inputs, Supplies, Schematics, BOMs 37 Hands On Exercise Design Problem: Goals: Source: 18 – 32V Loads: LCD Panel: 3.3V, 0.2A What is the system with the: Flash Memory: 1.8V, .05A Freescale QorIQ P2020 Smallest footprint Avdd: 1.05V, 1A BVdd: 1.8V, .06A Highest efficiency Cvdd: 1.8V, .02A Lowest cost Gvdd: 1.5V, .9A LVdd: 2.5V, .1A OVdd: 3.3V, .01A SVdd: 1.05V, .4A Vdd: 1.05V, 5.6A XVdd: 1.05V, .4A 38 Summary • WEBENCH Visualizer – View up to 50 designs at a time to get the best solution for a single power supply – Each design optimized for efficiency, cost and size • WEBENCH Power Architect – System level designs for complex multiple load applications – Provides different rail architectures – Each system optimized for efficiency, cost and size • WEBENCH FPGA/Processor Power Designer – Preconfigured FPGA and processor loads including noise/filter requirements • WEBENCH saves you time! 39 Thank You! Try WEBENCH® FPGA Power Architect yourself: http://www.national.com/fpga_power_architect LED Architect: http://www.national.com/led_architect Jeff Perry [email protected]