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Pinewood Derby Timing System Using a Line-Scan Camera Rob Ostrye Class of 2006 Prof. Rudko Project Background System is used to determine time and finish order of cars in a pinewood derby car race Accommodates up to 4 lanes Easy to use, low cost, and accurate Operate from a PC via a USB cable Images taken and displayed on the computer Pinewood Derby Setup Star ter Camera Lens Lanes Timer Implementation Line-Scan CCD camera lens and sensor capable of monitoring up to 4 lanes Xilinx FPGA for core logic and component interfacing Non-Volatile Memory for start up DRAM for holding data 2 Layer PCB interfacing all components Components Used Xilinx XC3S250E VQ100 FPGA (link) 1.2v Switching Power Supply 2.5v and 3.3v LDO Power Supplies TAOS TSL3301 CCD (link) M12 CCD Lens SPI Flash Memory SDRAM 48 MHz System Clock Transient Voltage Suppressor External Connectors USB Trigger Circuit Board Image Sensor 3.3v 5v Power Supplies 2.5v FPGA 1.2v Clock 38 DRAM USB External Trigger Flash Memory Xilinx Spartan 3E FPGA 66 User Input/Outputs accommodates the needs for all of the components chosen 250k system gates allows for a greater range of functionality Small size Availability of software tools and libraries for implementation Power Supplies Switching Supply: 1.2v Low power loss FPGA Core voltage Low Quiescent Current LDO: 3.3v and 2.5v Small footprint Provide enough current for application Image Acquisition CCD: 102x1 Pixels translates to about .17 inches square per pixel when the sensor is placed 13 inches above the trace Serial Interface for easier VHDL implementation Explicit instructions available to control the sensor Fits supply voltage constraints M12 Lens: Focal length of 8.0mm will accommodate about 4 tracks at about 13 inches above the track Fits in an existing part used for the M12 lens System Memory Synchronous DRAM 4x16 64MBit will store high amount of data Control module cores are available Interface easily with the FPGA SPI Flash Memory 4MBit hold enough data for load instructions FPGA has settings for easy implementation Readily available chip due to high consumer demands Programming Interface the sensor with the block RAM within the FPGA Enter data from block RAM into DRAM Take data from the DRAM and read out over USB Use developed cores for: USB interface to the computer SPI Flash interface DRAM reading and writing Cores around the FPGA USB Interface DRAM Interface Image Sensor Interface FPGA SPI Flash Interface Trigger Interface Interface between BRAM and Sensor Block RAM SClock Image Sensor Interface SDin Image Sensor SD Image sensor receives data serially into an 8 bit register which provides instructions to the sensor. ASM for Image Sensor Interface Asynch Reset address = 0 SDin = 0 writeEN = 0 timer = 0 Read BRAM address = address + 1 SDin = BRAM(address) Write pix = 0x16 I Reset SDin = 0 0 1 Defaults timer = timer-1 writeEN = 0 SDin = 0 address = 512 timer = 10MHz Wait start line rate address = 0 timer = -32 0 timer = 0 1 1 Wait state 0 SD timer = 0 0 1 Write Pixel 1 0 address = address + 1 writeEN = 1 0 1 address(2:0) = 0 Line Acquisition Rate 630 s The line scan rate is adjustable based on the timer reset value. 1 line / 630 s ≈ 1600 lines/sec Results Custom designed circuit board with working supply voltages and correct component connections Image sensor interface modeled and proven to work in simulation Adapted to work on a development board Available cores analyzed and chosen Possible Future Development Image acquisition that will read out only the period of time when the cars are under the camera Interface logic cores for integrated operation Set up the external trigger to start device Use SPI flash memory to program the FPGA on startup Develop an algorithm for focusing the lens Resources Birger Engineering, Inc. The project was conducted in conjunction with the company. Provided technical knowledge with respect to hardware and software development Provided software and some of the hardware involved with the project Opencores.org Open source codes and information pertaining to USB, DRAM, SPI flash elements of the project Component Technical Documentation Prof. Rudko
