Download OEM PowerPoint Template

High Efficiency Amplifiers for EDGE Applications
Based on Enhancement-Mode Junction PHEMT
J.C. Clifton, L.Albasha
Sony Semiconductor & Electronic Solutions
M.Willer
Sony CSBD
13th September 2004
Technology: Sony J-PHEMT
JPHEMT Structure
Source
p-Gate
•Higher forward voltage enables positive
drive.
Id, Ig
Id
Drain
Id
InGaAs Channel
Vth
Ig
Ig
Vg
GaAs Sub.
Schottky HEMT
Vf = 0.7 (V)
pn Junction Gate
→ High Vf → High Drain Current
JPHEMT
Vf = 1.2 (V)
Objectives: Designing an EDGE PA
• EDGE functionality required from iteration of current GSM
PA: Dualmode PA.
• Interface to a Direct Modulation Transceiver: to allow future
inclusion of WCDMA for future single GSM/EDGE/WCDMA TX
Architecture.
• Inclusion of EDGE functionality with only a small impact to
the size and cost of the basic GSM solution.
• Meet EVM specifications over VSWR of 3:1 without isolator
and avoid complex calibration/set-up.
• Target EDGE efficiencies 25%+ whilst maintaining current
GSM performance of 55-60%.
Types of EDGE (8PSK) Power Amplifier
Linear/Backed-Off PA Approach
Fixed Vdd=3.5V Operation
GSM/EDGE PA
Pout=28.5dBm
PA
• J-PHEMT gives respectable
efficiency at several dB back-off
whilst maintaining EVM & ACPR
• Simple and robust architecture
Backed off Input
Power, Pin
Coupler for PACL
• Also suited for WCDMA
• Sometimes issues meeting EVM spec
under mismatch conditions: Isolator.
Increased Vgg for linear
operation
• Efficiency suffers under back-off
Polar Loop Approach
• J-PHEMT gives good saturated
efficiency
Log Amplifier
Amplitude
Modulator
Log Amplifier
• Additional efficiency comes at the
expense of much greater complexity
Phase
Modulator
or VCO
S(t)
Limiter
VCO
• Difficult to adopt for WCDMA and
use with direct modulator transceiver
PA
Sin(wt)
Limiter
Phase detector
• Headline efficiency impacted by
consumption within AM-AM and
AM-PM feedback loops
Simulation Test Bench
• 3 Stage PA model based on Agilent Eesof model
on ADS.
• System simulation tool ptolemy to allow
inclusion of AM and PM correction loops.
Simulation of ACPR, EVM, output power and
efficiency.
• Used to simulate Linear/Back-off PA in addition
to various different types of saturated PA.
Saturated PA Architectures
Envelope Elimination and Restoration (EER) Power
Amplifiers for EDGE
Advantage: Drive Level and Power Control (eg drain regulation) similar to
GMSK (constant Envelope)
Issue: Method of Envelope insertion and correction
Corrected Envelope
inserted onto drain or
gate supply
Envelope Detector
Amplitude
Modulator
S(t)
Limiter
Delay
matching
PA
Envelope Detector
Control Characteristics (1mm, 900MHz)
30
Gain (dB)
25
20
15
Gain (dB)
10
5
0
1
1.5
2
2.5
3
3.2
Drain Voltage (V)
20mm E-pHEMT Pin=15dBm
20
EVM (%)
18
16
14
EVM %
12
10
EVM%
8
6
4
2
3
2.5
2
1.5
1
0.5
0
EVM (%)
0
0
0.5
1
Gate Bias V
Gate
1.5
1
1.5
2
Drain Voltage (V)
Drain
2.5
3.5
EER Based on Drain Voltage
Envelope Detector
Amplitude
Modulator
Envelope Detector
Corrected RF Output Signal
S(t)
Limiter
Delay
matching
PA
Corrected Drain
Voltage (max=3.5V)
Associated Drain
Current
RF Output Signal make to
track EDGE Envelope by
AM Correction Loop
Loop Dynamics optimised to
minimise Error Voltage whilst
ensuring loop stability over range
of control and supply voltages
DRAIN VOLTAGE/CURRENT CHARACTERISTICS
PAE: 40-45% using fast DC-DC
converter
Phase Distortions
60° Phase
variation over
envelope
EVM> 11%. AM-PM Correction loop required to reduce EVM to 1.5%
and bring ACPR inside specification:
Log Amplifier
Amplitude
Modulator
S(t)
Log Amplifier
Phase
Modulator
or VCO
Limiter
VCO
PA
Sin(wt)
Limiter
–Phase detector
EER Based on Gate Voltage
Envelope Detector
Amplitude
Modulator
S(t)
20
Degrees
Limiter
Delay
matching
Envelope Detector
PA
Phase error significantly reduced.
Resulting EVM of 3.2%. Further reduced
with the addition of simple pre-distortion
circuit. Simulated PAE of 44%.
Adaptive Bias Control Based on Gate Voltage
LOG
Amp
Input Signal:
Including
Envelope
Amp.
Mod.
LOG
Amp
Gate bias
correction
loop
Delay
matching
m
atching
PA
PA operated in saturated mode. Gate tracking circuit designed to exhibit
constant gain over input envelope. Simulated efficiency of 50%.
Resulting phase variation of <10° over envelope and EVM of 1%.
Phase error due to compression is
partly offset by impact of phase
variation caused by gate bias shifts
required to keep gain constant
Practical Measurements of Gate Correction Circuit with Class
A/B PA out of Compression
Delta 1 [T1]
Ref Lvl
0 dBm
-36.14 dB
400.00000000 kHz
RBW
30 kHz
VBW
30 kHz
SWT
6 ms
RF Att
30 dB
Delta 1 [T1]
Unit
Ref Lvl
dBm
0 dBm
0
-54.30 dB
400.00000000 kHz
RBW
30 kHz
VBW
30 kHz
SWT
6 ms
RF Att
Unit
30 dB
dBm
0
A
A
-10
-10
1
1
-20
-20
-30
-30
1AVG
1SA
-40
-36.1dBc, 400KHz offset
-50
1
1AVG
1SA
-40
-54.3dBc, 400KHz offset
-50
-60
-60
-70
-70
-80
-80
1
-90
-90
-100
-100
Center 900 MHz
Date:
17.JUN.2004
200 kHz/
11:39:04
Span 2 MHz
Center 900 MHz
Date:
17.JUN.2004
200 kHz/
Gate AM correction
circuit reduced EVM
from 16% down to
3%.
Span 2 MHz
11:42:32
Implementation Issues for PA in compression: AM Correction
loop design –extreme sensitivity of gate voltage to EVM and
ACPR.
Linear PA Investigations
Required improvements for product:
• Elimination of output isolator: meet EVM spec in 3:1
Antenna VSWR
• Elimination of output coupler/detector and control feedback
loops: Open Loop Control
• Avoidance of 30-40dB VGA/VVA which impacts power
consumption, size and RX Noise performance (TX SAW not
acceptable)
• Improve efficiency compared to conventional EDGE Linear
Power Amps
Objectives Met with Modified Linear PA
Modifications compared to conventional Linear
PA to Improve Efficiency at back-off and simplify
power control scheme
Modified Linear PA: Measured Performance
DualMode PA
Gate Supply= V1 for GSM
V2 for EDGE
GMSK: Compressed
(V2>V1)
EDGE: Linear
RFin
RFout
GMSK O/P
Matched
Input Step Attenuation: EDGE HI,
GMSK LO
34.5dBm GMSK
28.5dBm EDGE
Vramp (GSM & EDGE)
Vd supply=Vbattery
PAE comparison between New Linear EDGE
PA and Conventional Type
25.00
20.00
Output Pow er (dBm)
15.00
Efficiency (%)
EVM(%)
10.00
Efficiency (%)
Output Power(dBm) & PAE (%)
30.00
25
20
Modified Linear PA
15
10
Conventional
Linear PA
5
0
0
5.00
10
20
30
Output Power(dBm)
0.00
0.00
0.50
1.00
Vram p
1.50
2.00
(excluding VGA consumption required for conventional PA)
Modified Linear PA
Measured Pout/Temperature Characteristics
40
30
20
Pout(dBm)
10
-20C
20C
85C
0
0
0.2
0.4
0.6
0.8
1
-10
-20
-30
Vramp (Volts)
1.2
1.4
1.6
1.8
2
Open-Loop Operation and Mismatch: Measurements
G01 - EVM vs VSWR at 900MHz
G01 - Pout vs VSWR at 900MHz
5.5
5.0
4.5
28.5dBm (High)
30.0
20.0dBm (High)
20.8dBm (Low)
28.0
5.1dBm (Low)
24.0
26.0
4.0
22.0
Pout / dBm
EVM / %
3.5
3.0
2.5
2.0
20.0
18.0
16.0
28.5dBm (High)
14.0
20.0dBm (High)
12.0
20.8dBm (Low)
10.0
1.5
5.1dBm (Low)
8.0
1.0
6.0
0.5
4.0
2.0
0.0
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.4
4.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
VSWR
VSWR
Without isolator
Temperature stable, variable gain PA
RX Noise: -82.3dBm/100KHz @20Mhz
offset from carrier
(-10dBm input power, 28.3dBm Output)
Power Error Budget
Frequency Variation
<
Temperature Variation <
+/-1.0dB
+/-1.0dB
WORST CASE
SPEC(E2)
+/-2.0dB
+/-4.0dB
<
Conclusions
• Promising simulation results for JPHEMT PA in both Saturated
(Polar Loop/EER) and Linear modes, proving capabilities of the
device.
• Adaptive Bias Control of Compressed PA based on gate
envelope tracking looks promising from viewpoint of reduced
complexity and performance. However, significant
implementation issues exist.
• Approach based upon modified linear PA proved best suited to
meeting original objectives.
• EDGE RF functionality possible with very small size/cost
impact to GSM solution. Forward compatibility with WCDMA.
Acknowledgements
• Colleagues at Atsugi Technology Centre: H. Kawasaki, H.
Kawamura and H. Motoyama
• Support from Thomas LeToux, project student from ULP
France/UCL UK.
• Agilent ADS UK team for simulation support.