Download MN5286 - Panasonic Semiconductor

LSIs for DSC
MN5286
CCD Driver LSI
DS1
DS2
RWI
FCK2O
HCLR
VDD
CPOB
PBLK
CLR
TEST1
TEST2
XO
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
SUB
CH4
CH3
CH2
CH1
V4
VSS
V3
V2
V1
STO
TRG
XI
DRV1
DRV2
HD
VD
VSS
VDD
DCLK
DATA
CS
CLKO
ADCLK
(TOP VIEW)
Note) Do not leave any of the VDD and VSS pins open.
int
en
an
ce
/D
isc
on
tin
ue
• Corresponding imaging element:
MN39571PT: 1/2-type 2.31 M-pixel CCD area imaging sensor.
• Supports electronic zooming
• Strobe flash function using an external trigger signal
(serial input)
Output pin (STO) for triggering a strobe flash unit.
• Vertical drive mode (serial or parallel input)
• Supports an electronic shutter function (serial input)
• Low power mode (serial input)
This function shuts down the H1, H2, R, DS1, DS2,
and ADCLK signals and is controlled by serial input
data.
• Supply voltage:
Supports dual supply voltages:
3.3 V±0.3 V
5.0 V±0.5 V (For the H1, H2, and R outputs only.
The 3.3 V±0.3 V supply can also be used
for these outputs.)
• High-speed pulse phase switching pin (This function
can be controlled by 90° step from either serial or parallel inputs.)
This function allows the phase of ADCLK to be modified with respect to CLK0 using the CSEL1 and CSEL2
pins.
1
2
3
4
5
6
7
8
9
10
11
12
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■ Features
36
35
34
33
32
31
30
29
28
27
26
25
M
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The MN5286 is a CCD drive pulse generation LSI that
features the ability to start the system with just the input
of HD, VD, and clock of 2fCK (47.11392 MHz or 49.50000
MHz) signals, and adds camera functions controlled from
external trigger signals.
DEFAULT
RESMD
VSS
VSS5
R
VDD5
H1
H2
VDD5
VDD
CSEL2
CSEL1
■ Overview
Ma
■ Applications
• Digital still cameras
• Cameras for use in factory automation and office equipment.
Publication date: May 2002
SDB00068CEM
1
2
SDB00068CEM
VD
HD
TRG
CS
DCLK
DATA
VSS
VDD
TEST1, TEST2
Mode
determination
test circuit
d i pulse, STO
SUB
p
nTRG
Pl
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Vertical
ww wi co on Serialcdata
high-speed
c
f
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tin circuit
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timing
na Vertical
t laset/reset
HD signal latch
cy
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Horizontal
HCLR
VD signal latch
.
/
set/resete
generation
n/ atio
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XO
DRV1, DRV2
ue
CSEL1, CSEL2
High-speed
pulse decoder
FCK2O, RWI
DEFAULT
XI
CLKO
ce
Divide-by-two /D
circuit
isc
on
tin
Divide-by-two
circuit reset pulse
an
en
int
Ma
Process pulse
decoder
Vertical transfer
pulse decoder
CH pulse
decoder
M
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HCLR
PBLK
CPOB
V1 to V4
STO
SUB
CH1 to CH4
R
H1, H2
DS1, DS2
ADCLK
MN5286
■ Block Diagram
MN5286
■ Pin Descriptions
Pin No.
Pin Name
I/O
Descriptions
1
XI
I
Oscillator input (2fCK clock input)
2
DRV1
I
φV drive mode switching input 1
Notes
Built-in pull-down resistor
of about 51 kΩ.
3
DRV2
I
φV drive mode switching input 2
Built-in pull-down resistor
M
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sc te
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of about 51 kΩ.
4
HD
I
Horizontal synchronizing signal input
5
VD
I
Vertical synchronizing signal input
6
VSS

7
VDD

8
DCLK
I
9
DATA
I
10
CS
I
11
CLKO
O
12
ADCLK
O
13
TRG
I
14
STO
O
15
V1
O
16
V2
O
17
V3
O
18
VSS

19
V4
O
20
CH1
O
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GND
Power supply (3.3 V)
Serial communication clock input
Schmitt input
Serial communication data input
Serial communication data latch input
Schmitt input
Clock output (FCK)
A/D converter clock output
External trigger input
Strobe flash trigger output
φV1 transfer pulse output (negative logic)
φV2 transfer pulse output (negative logic)
φV3 transfer pulse output (negative logic)
GND
φV4 transfer pulse output (negative logic)
ce
/D
isc
on
tin
ue
φV1PD charge readout pulse output
(negative logic)
21
CH2
O
φV3PD charge readout pulse output
(negative logic)
an
CH3
O
24
CH4
Ma
23
int
en
22
SUB
φV5PD charge readout pulse output
(negative logic)
O
φV7PD charge readout pulse output
(negative logic)
O
Photodiode charge substrate sweep pulse
(negative logic)
25
CSEL1
I
ADCLK phase selection 1
Built-in pull-down resistor
of about 51 kΩ.
26
CSEL2
I
ADCLK phase selection 2
Built-in pull-down resistor
of about 51 kΩ.
SDB00068CEM
3
MN5286
■ Pin Descriptions (continued)
Pin Name
I/O
Descriptions
27
VDD

Power supply (3.3 V)
28
VDD5

Power supply for φH, φR (5 V)
29
H2
O
φH2 transfer pulse (positive logic)
30
H1
O
φH1 transfer pulse (positive logic)
31
VDD5

Power supply for φH, φR (5 V)
32
R
O
φR transfer pulse (positive logic)
33
VSS5

Ground for φH, φR
34
VSS

GND
35
RESMD
I
Notes
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Pin No.
All clear release mode switching input
Built-in pull-down resistor
of about 51 kΩ.
36
DEFAULT
I
Input for the output default
Built-in pull-down resistor
of about 51 kΩ.
37
DS1
O
38
DS2
O
39
RWI
I
40
FCK2O
O
CDS pulse 1 output
CDS pulse 2 output
φR pulse width adjustment input
2fCK output
(φR pulse width adjustment output)
HCLR
O
42
VDD

43
CPOB
O
44
PBLK
O
45
CLR
I
TEST1
ce
/D
isc
on
tin
TEST2
I
I
XO
Ma
48
int
en
47
an
46
4
φH clear pulse output
41
Power supply (3.3 V)
OB clamp pulse output
ue
Pre-blanking pulse output
All clear input
Built-in pull-up resistor
of about 51 kΩ.
Test input 1
Built-in pull-down resistor
of about 51 kΩ.
Test input 2
Built-in pull-down resistor
of about 51 kΩ.
O
Oscillator output (2fCK): 3 × ,
An external feedback resistor is required.
SDB00068CEM
MN5286
■ Electrical Characteristics
1. Absolute Maximum Ratings at VSS = 0 V
Parameter
Symbol
Rating
Unit
VDD
− 0.3 to +7.0
V
Input voltage
VI
− 0.3 to VDD+0.3
V
Output voltage (except for TYPE-D)
VO
− 0.3 to VDD+0.3
V
Output voltage (TYPE-D)
VO
− 0.3 to VDD5+0.3
V
Output current (TYPE-HL2)
IO
±6
mA
Output current (TYPE-HL4)
IO
±12
mA
Output current (TYPE-HL8)
IO
±24
mA
Output current (TYPE-HL16)
IO
Power dissipation
PD
Operating temperature
Storage temperature
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Supply voltage
±144
mA
409
mW
Topr
−20 to +75
°C
Tstg
−55 to +150
°C
Note) 1. Type D pins
: H1, H2, R
Type HL2 pin : SUB
Type HL4 pins : V1 to V4, CH1 to CH4, FCK2O, STO, CLKO, CPOB, HCLR, PBLK
Type HL8 pins : DS1, DS2, ADCLK
Type HL16 pins : H1, H2, R
2. The absolute maximum ratings are limiting values under which the chip will not be destroyed.
Operation is not guaranteed within these ranges.
3. All of the VDD and VSS pins must be connected to power supply and ground, respectively.
2. Operating Conditions at VSS = 0 V
Parameter
Symbol
VDD
Level shifter reference voltage
VDD5
Input rise time
ce
/D
isc
on
tin
Operating temperature
ue
Supply voltage
Ta
tr
tf
an
Input fall time
en
Oscillator frequency
int
Recommended external
capacitor value
Ma
Conditions
fOSC1
CXI110
CXO110
Recommended external feedback Rf110
resistor value
Min
Typ
Max
Unit
3.0
3.3
3.6
V
3.0
3.3
3.6
V
−20

75
°C
0

100
ns
0

100
ns
50 MHz Xtal

50

MHz
VDD = 3.3 V
External feedback resistor

T.B.D.

pF
VI = VDD or VSS
VDD = 3.3 V

*

kΩ
CXI
Rf
XI
XO
CXO
Note)
* : Since the oscillator characteristics depend on the oscillator element itself, external capacitances, and other factors,
consult the manufacturer of the oscillator element to determine the circuit constants.
SDB00068CEM
5
MN5286
■ Electrical Characteristics (continued)
3. DC Characteristics at VDD, VDD5 = 3.0 V to 3.6 V, VSS = 0.00 V, fTEST = 50 MHz, Ta = −20°C to +75°C
Parameter
Symbol
Quiescent supply current
Conditions
VI (pull up) = OPEN
VI (pull down) = OPEN
IDDS
Min
Typ
Max
Unit


70.0
µA

10.0
µA
VI (XI) = VDD*1
With either the VSS or the VDD level
M
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is applied at the same time to all of
the other input pins and the I/O pins
of the high-impedance state.
IDDS
Supply current in opertation
IDDO
Level shifter voltage-reference
supply current in operation
IDDO3

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Level shifter voltage-reference
quiescent supply current
VI = VDD or VSS
f = 50 MHz, With the VDD = 3.3 V
outputs left open.

32.0
64.0
mA

19.0
38.0
mA
VDD × 0.7

VDD
V
0

VDD × 0.3
V


±5
µA
VDD × 0.7

VDD
V
CMOS input level pins: HD, VD, RWI, DATA
High-level input voltage
VIH
Low-level input voltage
VIL
Input leakage current
ILI
VI = VDD or VSS
CMOS input level pin with built-in pull-up resistor: CLR
High-level input voltage
VIH
VIL
RIH
0

VDD × 0.3
V
VI = 0.0 V
VDD = 3.3 V
17
51
153
kΩ
VI = VDD


±10
µA

VDD
V
Input leakage current
ce
/D
isc
on
tin
ue
Low-level input voltage
Pull-up resistor
ILIH
CMOS input level pins with built-in pull-down resistors:
DRV1, DRV2, TRG, CSEL1, CSEL2, TEST1, TEST2, RESMD, DEFAULT
en
an
High-level input voltage
VIH
VIL
RIL
Input leakage current
ILIL
Ma
int
Low-level input voltage
Pull-down resistor
VDD × 0.7
0

VDD × 0.3
V
VI = VDD
VDD = 3.3 V
17
51
153
kΩ
VI = VSS


±10
µA
1.95
1.35
VDD × 0.8
V
VDD × 0.2


±5
µA
CMOS level input pins with Schmitt trigger circuit: CS, DCLK
Input threshold voltage
Input leakage current
VT+
VT−
ILI
VDD = 3.0V to 3.6 V
VI = VDD or VSS
Note) *1 : The VDD applied to the CI oscillator pin is a different power supply from the power supply for measuring IDDS.
6
SDB00068CEM
MN5286
■ Electrical Characteristics (continued)
3. DC Characteristics at VDD, VDD5 = 3.0 V to 3.6 V, VSS = 0.00 V, fTEST = 50 MHz, Ta = −20°C to +75°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Push-pull outputs: SUB
VOH
IOH = −1.0 mA
VI = VDD or VSS
VDD− 0.6


V
Low-level output voltage
VOL
IOL = 1.0 mA
VI = VDD or VSS


0.4
V


V
M
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High-level output voltage
Push-pull outputs: V1 to V4, CH1 to CH4, FCK2O, STO, CLKO, CPOB, HCLR, PBLK
VOH
Low-level output voltage
VOL
Push-pull outputs: DS1, DS2, ADCLK
High-level output voltage
VOH
Low-level output voltage
VOL
IOH = −2.0 mA
VI = VDD or VSS
VDD− 0.6
IOL = 2.0 mA
VI = VDD or VSS


0.4
V
IOH = −4.0 mA
VI = VDD or VSS
VDD− 0.6


V
IOL = 4.0 mA
VI = VDD or VSS


0.4
V
IOH = 0 mA
VI = VDD or VSS
VDD5− 0.05


V
IOH = −8.0 mA
VI = VDD or VSS
VDD− 0.6


V
IOL = 8.0 mA
VI = VDD or VSS


0.4
V
IOH = 0 mA
VI = VDD or VSS
VDD5− 0.05


V
IOH = −24.0 mA
VI = VDD or VSS
VDD− 0.6


V
IOL = 24.0 mA
VI = VDD or VSS


0.4
V
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High-level output voltage
Push-pull output pin with level-shifter interface: R
High-level output voltage
VOH
High-level output voltage
VOH
Low-level output voltage
VOL
ce
/D
isc
on
tin
ue
Push-pull output pins with level-shifter interface: H1, H2
VOH
High-level output voltage
VOH
an
High-level output voltage
Ma
int
en
Low-level output voltage
VOL
SDB00068CEM
7
MN5286
■ Application Circuit Example
DS1
DS2
To CD
XO 48
XI:47.11392 MHz
or
49.5000 MHz
TEST2 47
d 1415i STO
V1
V1
TEST1 46
p
n
Pl
l
V2
16 V2
c
CLR 45
a
ea
ne 17 V3lud
V3
PBLK 44
se
es
CPOB 43
p
ma d1819mVSS
V4
V4 la
VDD 42
v
ne in 20 CH1ain foll
htt isit CH1
HCLR 41
d d te2122 CH2
p:/ fo CH2
t ow
FCK2O 40
CH3 en
n
d
i
RWI 39
/w lloCH3
i
n
a
CH4 is
s
a
23 CH4
DS2 38
wi co con24 SUBnce nc g fo
ww SUB
DS1 37
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DRV2
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CSEL2
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HCLR
PBLK
CPOB
To the signalprocessing circuit
1 XI
2 DRV1
3 DRV2
4 HD
5 VD
6 VSS
7 VDD
8 DCLK
9 DATA
10 CS
11 CLKO
12 ADCLK
HD
VD
To the control circuit
ce
/D
isc
on
tin
ue
13 TRG
DCLK
DATA
CS
CLKO
ADCLK
DEFAULT 36
RESMD 35
VSS 34
VSS5 33
R 32
VDD5 31
H1 30
H2 29
VDD5 28
VDD 27
CSEL2 26
CSEL1 25
GND
+3.3 V
+5.0 V
Ma
int
en
an
To the vertical drivers
Note) 1. When φH and φR are used under 3-volt specification, 5 V power supply should be replaced with that of 3.3 V too.
An external feedback resistor must be included in the oscillator circuit.
2. If an external clock signal is used, input a clock signal with a 1:1 duty ratio to either XI or XO.
8
SDB00068CEM
To CD
R
H1
H2
±0.05
±0.10
37
48
13
(0.75)
1
0.50
12
0.20±0.05
0.10
SDB00068CEM
±0.20
36
+0.10
-0.05
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0.10
d
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7.00
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9.00
ce fo
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MN5286
■ Package Dimensions (Unit : mm)
• TQFP048-P-0707B (Lead-free package)
9.00±0.20
7.00±0.10
25
24
0.10 M
(1.00)
0° to 8°
0.50±0.10
Seating plane
9
Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products, and no license is granted under any intellectual property right or other right owned by our company or any other
company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other
company which may arise as a result of the use of technical information described in this book.
M
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sc te
on na
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(3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office
equipment, communications equipment, measuring instruments and household appliances).
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support
systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body.
– Any applications other than the standard applications intended.
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(4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
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(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita
Electric Industrial Co., Ltd.