Download Design Considerations for Designing with Cree SiC Modules Part 1.

Design Considerations for Designing with
Cree SiC Modules Part 1.
Design Considerations for Designing with Cree SiC Modules Part 1.
Understanding the Effects of Parasitic Inductance
Scope:
The effects of power circuit parasitic inductances are an important consideration in the application and
characterization of SiC MOSFET modules. Of particular importance are turn-on conditions where internal
module voltage overshoots can be a concern; as well as EMI considerations.
Introduction:
Because silicon carbide (SiC) MOSFETs provide significant improvements in system electrical and
volumetric efficiencies to minimize overall system cost, they have been implemented in modules that
make SiC technology more attractive to design engineers in high power applications. The incorporation
of SiC technology into power modules combines the fast switching speed of silicon (Si) MOSFETs with the
low conduction loss of Si IGBTs at voltages of 1.2kV and higher. The key to successfully leveraging these
improvements, especially the faster switching speed, requires paying careful attention to system parasitics;
specifically stray inductances and capacitances beyond what is typically incurred for IGBT modules.
This application guide provides an intuitive understanding of these enhanced parasitic effects and explains
how to mitigate them in order to realize optimum performance from SiC MOSFET modules. The effects
of parasitic inductance and capacitance can include voltage and current overshoots and ringing. These
parasitics have always existed and are a natural consequence of the device physics involved. However, the
unique combination of high voltage, high current and increased switching speed of SiC MOSFETs requires
careful consideration of the circuit layout to reduce the effects of these parasitics.
REV A
Inductance
CPWR-AN12,
s of Parasitic
ct
fe
Ef
e
th
ng
Understandi
Because faster switching speeds at high voltages and currents give rise to higher dV/dt and dI/dt, voltage
drops across a few nanohenries of stray inductance can be problematic. This application note addresses
these concerns and illustrates how a typical SiC MOSFET module, in this case Cree’s CAS100H12AM1 1.2kV
100A half-bridge, was initially characterized. These techniques are equally applicable to other fast-switching
SiC power modules as well.
Subject to change without notice.
www.cree.com
1
Discussion:
In general, standard application guidelines developed for Si IGBT modules also apply to SiC MOSFET
modules. However, the significantly faster switching speed of the SiC MOSFET module requires a more
comprehensive understanding of the effects of parasitic elements to achieve a successful design of power
electronic equipment. All physical circuits have stray inductance caused by bond wires, board traces, etc.
The voltage drop across this inductance is expressed as the inductance times the rate of rise of current,
or V=L*di/dt. A customary ‘rule of thumb’ for insertion inductance puts it at about 10nH/cm. If the di/
dt is high enough, the voltage drop across this stray inductance can become significant. Furthermore, all
semiconductor switches exhibit some kind of output capacitance; typically proportional to the current rating
of the switch. With its unique capability to switch large currents at high speed, the SiC MOSFET module also
has a finite output capacitance. Because these parasitics form resonant circuits that need to be considered
for optimum application of SiC MOSFET modules, the following discussion will address various techniques to
control voltage overshoots without the use of snubbers.
The following subjects will be discussed:
• Application Considerations
• Parasitic Assessment
• Experimental Results
• Switching Speed vs. Overshoot
• EMI Considerations
Application Considerations:
The most critical parameter to control in the application of the SiC MOSFET module is to ensure that voltage
overshoot does not exceed the maximum device rating. This overshoot is the result of a resonant circuit
formed by the output capacitance of the module and the stray inductance present between the module
and the link capacitors. The voltage overshoot manifests itself at the time when one MOSFET is turned on,
while the other MOSFET is carrying freewheeling current as shown in Figure 1. Assuming the initial condition
that M1 and M2 are off, and freewheeling current from the inductive load is flowing through D1 causing it
to be forward biased, then net voltage across the load be small and negative, equal to the forward drop of
D1. Now, however, consider the case when the M2 is turned on. The upper diode D1, being forward biased
by the freewheeling current, causes an effective short circuit to be formed at the moment of turn-on. A
simplified schematic of this condition is shown in Figure 2, where M2 is replaced with a switch. Current
begins to flow from the link and the net forward current through D1 is Ifreewheel - Ilink. This condition holds
until Ifreewheel = Ilink. At this point, D1 becomes reverse biased and presents a capacitive load to the circuit.
This capacitive load consists of the total of reverse capacitance of D1 and the output capacitance (Coss) of
MOSFET M1. This collective capacitance will be referred to Coss for the remainder of this discussion.
CPWR-AN12, REV A
2 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
Stray Inductance
Stray Inductance
Stray Inductance
Stray Inductance
D1
M1 D1
M1
G1
G1
G1 RTN
G1 RTN
Link
Link
M2
M2
G2
G2
G2 RTN
G2 RTN
D1
D1
Freewheeling
Freewheeling
Current
Current
D1
D1
Inductive
Inductive
Load
Load
S1/D2
S1/D2
Ifreewheel
Ifreewheel
Inductive
Inductive
Load
Load
Ilink
Ilink
Link
Link
D2
D2
S2
S2
Figure 1: Module with inductive load
Figure 1: Figure
Module
with inductive
load
1: Module
with inductive
load
Figure 2: Freewheeling equivalent circuit
Figure 2:
Freewheeling
equivalent
Figure
2: Freewheeling
equivalentcircuit
circuit
As the load voltage rises, current begins to flow through the load as shown in Figure 3. The link
As the
theload
loadvoltage
voltage
rises, current
begins
to through
flow through
theasload
as shown
in3.Figure
3. The link
As
rises,
begins
to flow
theload
load
shown
Figure
The link
) andinthe
remainder
(Ilinkcurrent
– Iload)
current
is now split,
withcurrent
a portion
flowing
through the
(Iload
)
and
the
remainder
(I
– Iload
current
is
now
split,
with
a
portion
flowing
through
the
load
(I
load
is now used
split, with
a portion
flowing
through the
loadis(Iformed
theCremainder
(Ilink – Iload) beinglink
used
to )
load) andby
. A resonant
circuit
being
to charge
Coss
oss and the circuit stray inductance.
A formed
resonant
circuit
formed
Cossinductance.
and the circuit
inductance.
being used
charge circuit
Coss. is
charge
Coss. Atoresonant
Coss andisthe
circuitby
stray
In thisstray
analysis,
it is
In
this analysis,
it is assumed
that thebyload
is inductive.
Further,
it is assumed
that
the load
In this analysis,
is assumed
that
the load
inductive.
Further,
it is assumed
that
the load
assumed
that the it
load
is inductive.
Further,
it is is
assumed
that the
load inductance
will be
significantly
inductance will be significantly greater than the stray inductance shown in Figure 3. Under
inductance
be significantly
greater
the
shown
Figure 3. toUnder
greater
than will
the stray
inductance shown
in than
Figure
3. stray
Underinductance
these conditions,
it isinreasonable
assume
these conditions, it is reasonable to assume that the load does not provide much clamping or
that
theconditions,
load does not
much clamping
or damping
to thenot
resonant
circuit
formed
by Cossorand
these
it isprovide
reasonable
to assume
that the action
load does
provide
much
clamping
the stray
inductance. The circuit then
damping
action to the
resonant
circuit
formed
byshown
C and
the
stray inductance.
Theresonant
circuit then
reduces
to that
in Figure
4. inductance. The circuit then
the stray
damping
action to the
circuit
formed
by Coss
oss and
reduces to that shown in Figure 4.
reduces to that shown in Figure 4.
Stray Inductance
Stray Inductance
Stray Inductance
Stray Inductance
D1
D1
Link
Link
Iload
Iload
Inductive
Inductive
Load
Load
Ilink
Ilink
Coss
Coss
Link
Link
Figure 3: Commutation
Figure 3: Commutation
Figure 3: Commutation
IIlink -- IIload
link
load
Figure 4: Overshoot analysis circuit
4: Overshoot
analysis
circuit
Figure 4:Figure
Overshoot
analysis
circuit
Although
notshown,
shown,
the
resistive
(R)
portion
of resonant
this resonant
circuit
is represented
by the onAlthough
thethe
resistive
(R) (R)
portion
of this
circuit circuit
is represented
by the onresistance
Althoughnot
not shown,
resistive
portion
of this resonant
is represented
by the onresistance
of
switch
(M2
in
this
case)
as
well
as
any
other
resistive
losses
in
the
circuit.
A
of
switch (M2
this case)
any other
resistive
losses
the circuit.
A design
goalcircuit.
is to minimize
resistance
ofinswitch
(M2asinwell
thisas
case)
as well
as any
otherin resistive
losses
in the
A
design
goal
is
to
minimize
this
resistance
as
much
as
possible
in
order
to
realize
the
highest
this
resistance
as
much
as
possible
in
order
to
realize
the
highest
efficiency.
This
causes
the
circuit
to be
design goal is to minimize this resistance as much as possible in order to realize the highest
efficiency.
This
causes
the circuit
to be
underdamped
and across
an overshoot
of some
magnitude
underdamped
and
an
overshoot
of
some
magnitude
should
occur
C
,
which
is
in
effect
across
oss
efficiency. This causes the circuit to be underdamped and an overshoot of some magnitude
is ainclassic
effect acrossorder
MOSFET
This
RLCcharacteristics
series circuit is a
should
across
Coss, which
MOSFEToccur
M2. This
RLC series
circuit is
systemM2.
which
general
is in effectsecond
across MOSFET
M2.
This
RLC series circuitare
is a
should occur
across
Coss, which
classic
second
order
system
which
general
characteristics
are
shown
in
Figure
5.
shown in Figure 5.
classic second order system which general characteristics are shown in Figure 5.
CPWR-AN12, REV A
3 Understanding the Effects
of Parasitic Inductance
3
3
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
2
2
2
Normalized Capacitor Voltage (V)
Normalized
Normalized
Normalized
Capacitor
Capacitor
Capacitor
Voltage
Voltage
Voltage
(V) (V)
(V)
1.75
2
1.75
1.75
1.5
1.75
1.5
1.5
1.25
1.5
1.25
1.25
1
1.25
1
1
0.75
1
0.75
0.75
0.5
0.75
0.5
0.5
0.25
0.5
0.25
0.25
0
0.25
00
2
0
0 0
0
Figure 5: Normalized
0.05 0.05 0.05 0.15 0.15 0.3 0.15 0.05 0.3 0.5 0.3 0.15 0.5 0.9 0.5 0.3 0.9 0.9 0.5 0.9 2
2
4
4
4
6
8
6
6
10
8
8ωn*t 10
10
ω
ωn*t *t 12
12
12
14
14
14
16
2
4 voltage6vs. ω t 8for various
12 of ζ 14
n 10 values
capacitor
n
*t Figure
for
values
Figure 5:
5: Normalized
Normalized capacitor
capacitor voltage
voltage vs.
vs. ω
ωnntt ω
fornvarious
various
values of
of ζζ
16
16
18
16
18
18
18
20
20
20
20
Figure 5: Normalized capacitor voltage vs. ωnt for various values of ζ
Figure 5: Normalized capacitor voltage vs. ωnt for various values of ζ
The natural frequency, ω
n, in radians per second and in Hertz for this system is expressed as
The
natural
frequency,
follows:
ωnn,, in
in radians
radians per
per second
second and
and in
in Hertz
Hertz for
for this
this system
system is
is expressed
expressed as
as
The natural frequency, ω
The natural frequency, ωn, in radians per second and in Hertz for this system is expressed as follows:
follows:
1
follows:
The natural frequency, ωn, in radians per second and in Hertz for this system is expressed as
𝜔𝜔! =
1
1
𝜔𝜔
𝜔𝜔!! =
= 𝐿𝐿𝐿𝐿1
𝐿𝐿𝐿𝐿
𝜔𝜔! =1 𝐿𝐿𝐿𝐿
𝐿𝐿𝐿𝐿
𝑓𝑓! =
1
1
𝑓𝑓
2𝜋𝜋 𝐿𝐿𝐿𝐿
𝑓𝑓!! =
=
2𝜋𝜋 1 𝐿𝐿𝐿𝐿
𝑓𝑓! = 2𝜋𝜋 𝐿𝐿𝐿𝐿
2𝜋𝜋 𝐿𝐿𝐿𝐿
TheThe
optimum
point
for minimum
minimumovershoot
overshoot
with
fastest
is when
the
optimum
pointininthis
thissystem
system for
with
thethe
fastest
rise rise
timetime
is when
the damping
follows:
The
in
for
overshoot
with
ratio,optimum
ζ,ratio,
is unity.
this
particular
circuit,
it iscircuit,
expressed
damping
ζ,point
isInunity.
In system
this particular
it is as:
expressed
as: fastest
The
optimum
point
in this
this
system
for minimum
minimum
overshoot
with the
the
fastest rise
rise time
time is
is when
when the
the
damping
ratio,
ζ,
is
unity.
In
this
particular
circuit,
it
is
expressed
as:
damping
ratio,
ζ,
is
unity.
In
this
particular
circuit,
it
is
expressed
as:
The optimum point in this system for minimum overshoot with the fastest rise time is when the
𝑅𝑅 𝐶𝐶
2 𝑅𝑅 𝐿𝐿 𝐶𝐶 𝜁𝜁𝜁𝜁 =
=
2
𝐿𝐿
𝑅𝑅
2 𝐶𝐶
𝐿𝐿
𝜁𝜁 =
2 𝐿𝐿
damping ratio, ζ, is unity. In this particular
is expressed as:
𝜁𝜁 =circuit,
𝑅𝑅 it 𝐶𝐶
Thus, critical damping is achieved when:
Thus,
critical
damping
achieved
when:
Thus, critical
is is
achieved
when:
Thus,
criticaldamping
damping
is
achieved
when:
Thus, critical damping is achieved when:
1 𝐿𝐿
𝑅𝑅!"#$ = 1
1 𝐶𝐶 𝐿𝐿
𝐿𝐿
2
𝑅𝑅
=
!"#$
𝑅𝑅!"#$ = 2
1
𝐿𝐿
2 𝐶𝐶
𝐶𝐶
Where:
𝑅𝑅!"#$ =
Where:
2 RDS(on)
𝐶𝐶 of the lower switch
Rcrit = Total circuit resistance, typically dominated by the
Where:
= Total circuit resistance, typically dominated by the RDS(on) of the lower switch
Rcrit
Where:
Total
circuit
typically
dominated
of the lower switch
C
==
Output
capacitance
the upper
upper
switch
crit
C =R
Output
capacitance
ofofthe
switch
circuit resistance,
resistance,
typically
dominated by
by the
the R
RDS(on)
R
crit = Total
DS(on) of the lower switch
Where:
C
=
Output
capacitance
of
the
upper
switch
CLcrit
== Output
of the typically
upper
switch
Summation
of stray
inductances
between
the module
link of the lower switch
= Totalcapacitance
circuit
resistance,
dominated
by and
the the
RDS(on)
R
4
C = Output capacitance of the upper switch
4
4
CPWR-AN12, REV A
4 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
4
+ = Summation of stray inductances between the module and the link
+ = Summation of stray inductances between the module and the link
Parasitic Assessment:
Parasitic
Assessment:
Parasitic Assessment:
An example of parasitics assessment has been made for the double pulse setup used to
An example
parasitics
assessment
has been
made for
the double
setup used
to characterize
An
exampleofof
parasitics
assessment
has
been
made
the pulse
double
setup
usedoftotheCree’s
characterize
Cree’s
CAS100H12AM1
1.2kV
100A
half for
bridge
module.pulse
A photograph
CAS100H12AM1
1.2kV
100A
half
bridge
module.
A
photograph
of
the
hardware
is
shown
in
Figures 6 and 7.
characterize
Cree’s in
CAS100H12AM1
hardware is shown
Figures 6 and 7.1.2kV 100A half bridge module. A photograph of the
hardware is shown in Figures 6 and 7.
Gate Driver Board
Gate Driver Board
50mm Module
50mm Module
Gate Driver Board
Gate Driver Board
Figure 6: Double pulse setup top view.
Figure 6: Double pulse setup topFigure
view.6: Double pulse setup top view
Spacer
Spacer
50mm Module
50mm Module
Spacer and CT
Spacer and CT
Figure 7: Double pulse test setup side view.
Figure 7: Double pulse test setup side view.
Figure 7: Double pulse test setup side view
5
5
CPWR-AN12, REV A
5 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
The design consists of a link capacitor printed circuit board directly connected to the module. Spacers
The design consists of a link capacitor printed circuit board directly connected to the module.
are used to facilitate the installation of a current transformer to monitor the module current. The current
Spacers are
used to
thea installation
of a current
theTX22/14/6.4module
transformer
consists
of facilitate
two stages:
first stage consisting
of 10transformer
turns aroundto
a monitor
Ferroxcube
current.
The
current
transformer
consists
of
two
stages:
a
first
stage
consisting
of
10
turns
3E27 core; and the second stage is a Person Electronics current monitor model 2878.
around
a Ferroxcube
core; circuit
and the
second
stage
is a Person
Electronics
The design
consists ofTX22/14/6.4-3E27
a link capacitor printed
board
directly
connected
to the
module.
current
monitor
model
2878.
Spacers are used to facilitate the installation of a current transformer to monitor the module
current. The current
transformer
stages: a first stage consisting
of 10 turns
LINK CAPACITOR
BANK consists of twoSPACERS
MODULE
Test Point 1
nH
20.8 nH
5.3
nH
around a Ferroxcube TX22/14/6.4-3E27
core; and4.5
the
second stage is a Person
Electronics
(TP1)
LC1
LS1
current monitor model 2878.
LINK CAPACITOR BANK
5.3 nH
LC1
Test Point 1
(TP1)
SPACERS
4.5 nH
MODULE
20.8 nH LM1
LS1
LM1
LM2
800V
LM3
LM2
Test Point 2
(TP2)
800V
LM3
Test Point 2
(TP2)
LM4
LC2
LS2
Test Point
Reference
LC2
Figure 8: First Order Parasitics
LS2
Test Point
Reference
LCT1
LM4
CURRENT
TRANSFORMER
LCT1
5.5 nH
CURRENT
TRANSFORMER
5.5 nH
The
individual
were carefully
measured
at 1MHz. However, at these low
Figure 8:
First Order Parasitics
Figure
8: Firstinductances
Order Parasitics
inductance values, there always is a slight amount of ambiguity caused by the repeatability of
the
impedance
meter test
fixture,
as well
as
other
factors
in theHowever,
measurement
process.
The
Theindividual
individual
inductances
were
carefully
measured
at 1MHz.
at these
low values,
The
inductances
were
carefully
measured
at 1MHz.
However,
at these low
inductance
inductance
breakdown
of
the
module,
spacers,
and
current
transformer
is
shown
in
Figure
9.
inductance
values,
always
is a slight
amount
of ambiguity
caused
the repeatability
there
always is
a slightthere
amount
of ambiguity
caused
by the
repeatability
of the by
impedance
meter testof
the impedance
test fixture,
well as other
factorsThe
in inductance
the measurement
process.
The
fixture,
as well as meter
other factors
in theas
measurement
process.
breakdown
of the module,
spacers,
and current
transformer
is shown spacers,
in Figure 9.
inductance
breakdown
of the module,
and current transformer is shown in Figure 9.
Module = 20.8nH
Module = 20.8nH
Module + spacers = 25.31nH
Spacers = 4.5nH
Module + spacers = 25.31nH
Spacers = 4.5nH
Module + spacers + current
transformer = 30.81nH
Current+ transformer
= 5.5nH
Module
spacers + current
transformer = 30.81nH
Current transformer = 5.5nH
Figure 9: Module and interface inductances.
CPWR-AN12, REV A
6 Understanding the Effects
of Parasitic Inductance
6
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
6
The link capacitor printed circuit board is a parallel array of individual capacitors carefully
The
link capacitor
printedplate
circuitstructure
board is atoparallel
array
of individual
capacitors
carefullyof
designed
in a
designed
in a parallel
minimize
stray
inductance.
A schematic
the capacitor
parallel
plate
structure
to
minimize
stray
inductance.
A
schematic
of
the
capacitor
bank
is
shown
in
Figure 10.
bank is shown in Figure 10.
D1
+LINK
R1
220k
2W
R2
220k
2W
MID
R3
220k
2W
R4
220k
2W
-LINK
C1
16 uF
700VDC
C3
16 uF
700VDC
C5
16 uF
700VDC
C7
16 uF
700VDC
C9
16 uF
700VDC
C11
16 uF
700VDC
C13
8 uF
700VDC
MID
C2
16 uF
700VDC
C4
16 uF
700VDC
C6
16 uF
700VDC
C8
16 uF
700VDC
C10
16 uF
700VDC
C12
16 uF
700VDC
C14
8 uF
700VDC
S2
Figure 10: Link capacitor board schematic
The parallel array of series connected
was
designed
to meet voltage requirements
Figure 10:capacitors
Link capacitor
board
schematic
and to provide a midpoint connection to create a half-bridge inverter if desired. There are six
sets of 16µF 700V capacitors and one set of 8µF 700V capacitors, giving total capacitance of
The parallel array of series connected capacitors was designed to meet voltage requirements and to provide
52µF, with a total voltage rating of 1.4kV. Each 16µF capacitor has an equivalent series
a midpoint connection to create a half-bridge inverter if desired. There are six sets of 16μF 700V capacitors
inductance (ESL) of 30nH and each 8µF capacitor has an ESL of 27nH. A careful connection
and one set of 8μF 700V capacitors, giving total capacitance of 52μF, with a total voltage rating of 1.4kV.
using parallel plane transmission line techniques results in a total parasitic inductance of 5.3nH.
Each 16μF capacitor has an equivalent series inductance (ESL) of 30nH and each 8μF capacitor has an ESL
Thus, the total inductance of the test setup is approximately 37.5nH.
of 27nH. A careful connection using parallel plane transmission line techniques results in a total parasitic
inductance of 5.3nH. Thus, the total inductance of the test setup is approximately 36.1nH.
The other reactive component in this analysis is Coss, which refers to the module output
capacitance
withcomponent
the gates in
tied
toanalysis
their respective
sources.
depletion
capacitance,
The
other reactive
this
is Coss, which
refers Being
to the a
module
output
capacitance C
with
oss the
gates
tied
to their
respective
a depletion
capacitance,
varies
with
voltage
and is sources.
shown inBeing
graph
form as Figure
11. Coss varies with voltage and is shown in
graph form as Figure 11.
100
Measured Data
Diode Model
Energy Based
Coss (nF)
10
1
0.1
0
200
400
600
VDS (V)
800
1000
1200
Figure 11: Module Coss
7 as a function of VDS
CPWR-AN12, REV A
7 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
The graph contains three curves: The first is a set of data points showing the direct Coss measured data;
the second is a solid line showing the fit of a spice model of Coss; and the third is a plot of Coss calculated
based on energy. Because Coss significantly varies as a function of VDS, a simple first order analysis is
difficult. However, a reasonable simplifying assumption to analyze resonant behavior around a given steady
state voltage is to use equivalent capacitance based on energy. This energy-based equivalent capacitance
vs. voltage is also provided in Figure 11.
Experimental Results:
An initial two-pulse inductive test was done to evaluate the performance of the test setup. With the link
voltage set to 800V and the peak switching current set to 100A, the initial results are shown in Figure
12. The voltage was measured from voltage TP1 to the test point reference point and the current was
measured by the current transformer, as shown in Figure 8.
Test conditions:
Ipulse = 100A
Vlink = 800V
Vgate = 20/-5V
Rgate = 0 Ω
Load Inductance = 200 μH
1000
250
TP2 to Ref
Current
200
600
150
400
100
200
50
0
-200
Module Current (A)
Point 1 Voltage (V)
800
0
0
50
100
150
200
Time (nsec)
250
300
350
400
-50
Figure 12: Observable module turn-on characteristics
CPWR-AN12, REV A
8 Understanding the Effects
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information, please contact Cree Sales at [email protected].
This test was done with the external gate resistor set to zero. This was done to accentuate the
Although this test was done with the external gate resistor set to zero to accentuate the amount
ringing. with
Operation
with of
zero
ohms
gate resistance
is not recommended.
ofamount
ringing,ofoperation
zero ohms
gate
resistance
is not recommended.
There is a There is a
substantial
amount
of
ringing
present
in
both
signals.
The
steady
state
frequency
is of
25ringing,
MHz
Although
this
test
was
done
with
the
external
gate
resistor
set
to
zero
to
accentuate
the
amount
substantial amount of ringing present in both signals. The steady state frequency
is 25MHz
and
and
this
was
measured
at
300
nsec
to
insure
that
the
internal
voltages
achieved
an
average
operation
with
zero
ohms
of
gate
resistance
is
not
recommended.
There
is
a
substantial
amount
of
ringing
this was measured at 300nsec to ensure that the internal voltages achieved an average steady
steady
statesignals.
current.
note
thatfrequency
the response
is clearly
Therefore,
present
in both
TheAlso
steady
is 25MHz
and thisunderdamped.
was measured
300nsec
to the
ensure
state
current.
Also
note
that
thestate
response
is clearly
under-damped;
therefore,atthe
resonant
that
the
internal
voltages
achieved
an
average
steady
state
current.
Also
note
that
the
response
is
clearly
resonant
frequency
will
be
very
close
to
the
system
natural
frequency.
A
check
of
the
measured
frequency will be extremely close to the system natural frequency. A check of the measured
under-damped;
therefore,
the
resonant
frequency
will be extremely
close
to theand
system
natural
frequency.
parasiticsiscan
be made
calculating
estimated
resonant
frequency
and
comparing
to the
parasitics
performed
by by
calculating
thethe
estimated
resonant
frequency
comparing
it to itthe
A check
of
the
measured
parasitics
is
performed
by
calculating
the
estimated
resonant
frequency
and
measure
result
using
the
aforementioned
equations.
The
voltage
shown
in
Figure
12
is
measured result, using the aforementioned equations. The voltage shown in Figure 12 is
comparing
it to the
measured
result,the
the aforementioned
equations.
The across
voltage the
shown
in Figure
essentially
voltage
across
lower
switch.
Hence,
the voltage
upper
MOSFET
essentially
thethe
voltage
across
theusing
lower
switch;
thus,
the voltage
across
the upper
MOSFET
is12
is essentially
the
voltage
across
the
lower
switch;
thus,
the
voltage
across
the
upper
MOSFET
is
rising
to
is rising
to 800V
steady
state.
equivalent
for at
Coss
at 800V
is 1.045
nF. Using
this
800V
is 1.045
nF. Using
this value,
rising
to 800V
steady
state.
The The
equivalent
valuevalue
for Coss
800V
steady
state.
The
equivalent
value
for
C
at
800V
is
1.045
nF.
Using
this
value,
along
with
36.1nH
valuewith
along
with 36.1
nHinductance
for the inductance
the calculated
natural frequency
is:
along
37.5nH
for the
the oss
calculated
natural frequency
is:
for the inductance the calculated natural frequency is:
11
݂௥௘௦ ≈ ൎ𝑓𝑓!݂௡==
ൌ ʹͷǤͻ‫ݖܪܯ‬
= 25.4 𝑀𝑀𝑀𝑀𝑀𝑀
𝑓𝑓!"#
‫ͳ כ‬ǤͲͶͷ݊‫ܨ‬
2𝜋𝜋ʹߨ√͵͸Ǥͳ݊‫ܪ‬
37.5 𝑛𝑛𝑛𝑛 ∗ 1.045 𝑛𝑛𝑛𝑛
This
closely
agrees
withwith
the
measured
frequency
of 25MHz.
This
closely
agrees
the
measured
frequency
of 25MHz.
This
closely
agrees
with
the
measured
frequency
of 25 MHz.
More insight can be gained by doing a simple AC analysis at the resonant frequency. The simplifying
More
gained
byby
doing
a simple
analysis
at the
resonant
The
Moreinsight
insight
canbebe
gained
doing
a plot
simple
AC
analysis
atofthe
resonant
frequency.
The
assumptions
arecan
illustrated
in Figure
13.
This
isAC
a representation
the
modulefrequency.
current
from
200nsec
simplifying
assumptions
are
illustrated
in
Figure
13.
This
plot
is
a
representation
of
the
module
simplifying
assumptions
are
illustrated
in
Figure
13.
This
plot
is
a
representation
of
the
to 400nsec. First, consider the actual current case where a peak current of 150A occurs at 200nsec, module
current
from
400nsec.
consider
the
actual
current
case
where
a peak
current
currentdown
from200nsec
nsec
to 400 nsec.
First,
consider
the actual
current
case
where
a peak
decaying
to200
130A
atto400nsec.
TheFirst,
first
simplifying
assumptions
are
that
the
100A
load
current
iscurrent
of
150A
occurs
at
200nsec,
decaying
down
to
130A
at
400nsec.
The
first
simplifying
of
150A
occurs
at
200
nsec
decaying
down
to
130A
at
400
nsec.
The
first
simplifying
constant, and that the circuit is lossless, so the current remains at a constant amplitude. The second
assumptions
are
100A
load
current
isstate
constant,
and
thethe
circuit
is lossless,
soso
the
assumptions
arethat
that
the
100A
load
current
is constant
and
that
circuit
is
lossless
the
simplifying
assumption
isthe
that
only
the
AC
steady
condition
is that
considered,
so the
load
current
is now
current
remains
at
a
constant
amplitude.
The
second
simplifying
assumption
is
that
only
the
AC
zero.
The result
is a constant
50A The
peak,second
25MHz sine
wave suitable
for AC analysis.
current
remains
constantamplitude
amplitude.
simplifying
assumption
is that only the AC
steady
is is
considered,
load
current
is is
now
zero.
The
result
is aisconstant
steadystate
statecondition
condition
consideredsosothe
the
load
current
now
zero.
The
result
a constant
amplitude
50A
peak,
25MHz
sine
wave
suitable
for
AC
analysis.
amplitude 50A peak 25 MHz sine wave suitable for AC analysis.
200
200
Current
Current(A)
(A)
150
150
100
100
Actual
Actual
Lossless
Lossless
AC Steady
StateState
AC Steady
50
50
0
0
-50
-50
-100
-100 200
200
250
250
300
Time300
(nsec)
Time
(nsec)
Time
(nsec)
350
350
400
400
Figure 13: Rationalization of steady state sinusoidal analysis
Figure 13:
Rationalization
of steady state
sinusoidal analysis
Figure 13: Rationalization
of steady
state sinusoidal
analysis
The inductive reactance of 1nH of stray inductance (XL = 2*π*fr*L) at 25 MHz is approximately
0.157 Ω. Using the 50A peak value in the AC steady state analysis, a voltage drop of 7.85V/nH
9
9
CPWR-AN12, REV A
9 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
of stray inductance will occur which is about 1% of the link voltage. This is significant because
The inductive reactance of 1nH of stray inductance (XL=2*π*fr*L) at 25MHz is approximately 0.157Ω. Using
the general
‘rule of thumb’ for trace inductance is 10nH/cm which equates to 10% of the link
the 50A peak value in the AC steady state analysis, a voltage drop of 7.85V/nH of stray inductance will
voltage
per
cm.
occur, which is about 1% of the link voltage. This is significant, because the general ‘rule of thumb’ for
Straytrace
inductance
willisaffect
voltage
measurements.
the ring
visible on the TP2
inductance
10nH/cm,
which
equates to 10% In
of Figure
the link 12,
voltage
per cm.
voltage trace actually exceeds 100V for several cycles. The peak current flowing through the
inductance
measurements.
In Figure
ring one
visible
on the
TP2 voltage
trace
lowerStray
MOSFET
is onwill
theaffect
ordervoltage
of 200A.
Assuming an
RDS(on)12,
of the
16mΩ,
would
expect
a
actually
exceeds
100V
for
several
cycles.
The
peak
current
flowing
through
the
lower
MOSFET
is
on
the
maximum voltage drop of approximately 3.2V across the switch. However, as shown in Figure
of 200A.
Assuming
an the
RDS(on)
of 16mΩ,
wouldthe
expect
a maximum
approximately
8, theorder
voltage
at TP2
includes
voltage
dropone
across
switch
plus the voltage
voltagedrop
dropofacross
3.2V
across
the
switch.
However,
as
shown
in
Figure
8,
the
voltage
at
TP2
includes
the
voltage
the stray inductance between the switch and the reference point. Using the aforementioneddrop
ACacross
the switch plus the voltage drop across the stray inductance between the switch and the reference point.
steady state technique 100V peak voltage drop at 50A would be due to perhaps 13 nH of stray
Using the aforementioned AC steady state technique, 100V peak voltage drop at 50A would be due to
inductance
which is reasonable based upon the measurements previously presented. Another
approximately 13nH of stray inductance, which is reasonable based upon the measurements previously
indicator that the voltage observed at TP2 includes stray inductance effects is the approximately
presented. Another indicator that the voltage observed at TP2 includes stray inductance effects is the
90° phase shift between the voltage observed at TP2 and the current through the module.
approximate 90° phase shift between the voltage observed at TP2 and the current through the module.
The amount
of series
resistancefor
forcritical
criticaldamping
damping can
as and
follows:
The amount
of series
resistance
canbe
becalculated
calculated
is as follows:
1 ͵͸Ǥͳ݊‫ܪ‬
ܴ௖௥௜௧ = ඨ
ൌ ʹǤͻͶߗ
2 ͳǤͲͶͷ݊‫ܨ‬
To completely mitigate the initial overshoot, the value of R would have to be equal to or greater
completely
mitigate
initial overshoot,
R wouldan
have
to be equal
toΩ
orinto
greater
than To
2.94
Ω. RDS(on)
of thisthe
module
is typicallythe
16value
mΩ. ofPlacing
additional
2.94
the than
high
2.94Ω.
The
R
of
this
module
is
typically
16mΩ.
Placing
an
additional
2.94Ω
into
the
high
current portion ofDS(on)
this circuit to completely damp this parasitic resonance is not a practicalcurrent
portion
of possible
this circuittotoreduce
completely
damp this
is notthe
practical;
however,
it is
possible
solution.
It is
the amount
ofparasitic
ring by resonance
slowing down
switching
speed
but
to
reduce
the
amount
of
ring
by
slowing
down
the
switching
speed
(but
this
in
turn
increases
the
this increases the amount of switching loss. One of the key advantages of the SiC MOSFET amount
is
of switching loss). One of the key advantages of the SiC MOSFET is fast switching speed and it is possible
fast switching speed. It is possible to nullify this key advantage by slowing the switching speed
nullify this key advantage by slowing the switching speed down too much. Recognizing that there will
downtotoo
much. There will always be some amount of ringing present. An engineering tradeoff
always be some amount of ringing present,an engineering tradeoff needs to be made to ensure that
needs to be done to insure that the voltage overshoot does not damage the device while
voltage overshoot does not damage the device while preserving the switching speed advantage.
preserving the switching speed advantage.
Switching Speed vs. Overshoot:
Switching Speed vs. Overshoot:
The critical issue that needs to be addressed is how to select the optimum switching speed that manages
the internal
overshoot
sacrificing
too to
much
of the
MOSFET’s
speed advantage.
The critical
issuevoltage
that needs
to bewithout
addressed
is how
select
an SiC
optimum
switching
speed thatAn
analytic
solution
to
this
problem
is
not
possible
because
of
the
nonlinear
behavior
of
C
manages the internal voltage overshoot without sacrificing too much of the SiC MOSFET’s
oss. However, an
equivalent
RLC
circuit
can
be
simulated
using
a
model
for
C
.
The
schematic
of
this
simulation
is shown
speed advantage. An analytic solution to this problem is not
oss possible because of the nonlinear
in
Figure
14.
The
results
of
this
analysis
provide
heuristic
guidance
for
the
adjustment
of
switching
behavior of Coss. However, an equivalent RLC circuit can be simulated using model for C oss. speed
without the of
tedium
of a rigorous
solution.
The schematic
the simulation
is analytic
shown in
Figure 14. The results of this analysis provide
heuristic guidance for the selection of switching speed without the tedium of a rigorous analytic
solution.
10
CPWR-AN12, REV A
10 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
L1 = 37nH
Coss
RDS(on)
DC Link
Equivalent circuit
for Coss
Pulse voltage
source to mimic
switch
Figure 14: Simulation schematic
Figure 14: Simulation schematic
A comprehensive “all-parasitics” simulation is extremely complex and time-consuming,
however,this
can be simplified
by is
creating
a circuit
thatand
simulates
conditions
at the instant
A comprehensivetask
“all-parasitics”
simulation
extremely
complex
time-consuming,
however,
this
that
the
lower
switch
starts
to
turn
on.
In
this
case,
the
lower
switch
is
represented
with switch
an ideal
task can be simplified by creating a circuit that simulates conditions at the instant that the lower
pulsed
voltage
source.
This
is
a
reasonable
simplification,
since
during
MOSFET
turn-on,
the is
starts to turn on. In this case, the lower switch is represented with an ideal pulsed voltage source. This
combination
of
gate
resistance
and
Miller
effect
cause
the
drain
dV/dt
to
be
constant.
This
also
a reasonable simplification, since during MOSFET turn-on, the combination of gate resistance and Miller
has
the
practical
aspect
that
the
dV/dt
can
be
directly
controlled
by
the
selection
of
the
effect cause the drain dV/dt to be constant. This also has the practical aspect that the dV/dt can be directly
appropriate
gate
resistor.
The
MOSFET’s
behavior
voltage behavior
fall time during
is mimicked
controlled
by the
selection
of the
appropriate
gate
resistor.during
The MOSFET’s
voltageby
fallan
time
as
a
function
of
voltage
ideal
pulsed
voltage
source
with
a
finite
fall
time.
The
behavior
of
C
oss
is mimicked by an ideal pulsed voltage source with a finite fall time. The behavior
of Coss as a function is
with
by using by
a diode
capacitor.
The model
accurately
fits the
change
of C
of simulated
voltage is simulated
using and
a diode
and capacitor.
The model
accurately
fits the
change
ofoss
Coss
with
the MOSFET
a fixed resistor.
voltage.
resistor
simply
models
the RofDS(on)
voltage.
TheThe
resistor
simply
models
the RDS(on)
the of
MOSFET
as a fixedasresistor.
The
simulation
runvarious
for various
voltage
fall times,
and
two
data
were gathered.
Thehas
The
simulation
waswas
run for
voltage
fall times,
and two
sets
of sets
data of
were
gathered.
The first set
set has
fall time
to below
the period
of the
resonantThese
circuitresults
(25.4MHz).
thefirst
voltage
fall the
timevoltage
set to below
the set
period
of the resonant
circuit
(25.4MHz).
are shown in
These
Figure
15.results are shown in Figure 15.
11
CPWR-AN12, REV A
11 Understanding the Effects
of Parasitic Inductance
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For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
V(coss)
1.8KV
Key:
1.6KV
Green:
Blue:
Red:
Gray:
0.25*tres
0.50*tres
0.75*tres
1.00*tres
50ns
60ns
1.4KV
1.2KV
1.0KV
0.8KV
0.6KV
0.4KV
0.2KV
0.0KV
0ns
10ns
20ns
30ns
40ns
70ns
80ns
90ns
Figure 15: Voltage overshoot as a function of switching speed shorter than resonant period
Figure 15: Voltage overshoot as a function of switching speed shorter than resonant period
The switching speed steps were chosen to be a function of the period of fres where tres = 1/fres.
The
shows
the res
switch
voltage
Theswitching
switching
speed
steps
0.25*t
res. of
The
speed
steps
wereare
chosen
tores
betoa 1.0*t
function
thebottom
period graph
of fres where
tres=1/f
. The switching
As shown,
and the
topare
shows
voltage
C oss. graph
speed
steps
0.25*tthe
1.0*tres.across
The bottom
showsthe
thepeak
switchvoltage
voltageactually
and the reaches
top shows the
res to
point.The
avalanche
forCoss
the
0.25
and the
0.5 peak
case.voltage
The peak
voltage
continues
to for
drop
voltage
across
. As
shown,
actually
reaches
avalanche
theuntil
0.25the
and1/f
0.5
res case.
peak
to drop
until
the
1/fres point.voltage
The general
conclusion
that the overshoot
voltage
The voltage
generalcontinues
conclusion
is that
the
overshoot
decreases
withisincreasing
switching
time.
decreases with increasing switching time.
The second set of simulations involved switching speeds from 1/fres to 2/fres in five steps. The
The
second
of simulations
switching speeds from 1/fres to 2/fres in five steps. The results are
results
areset
shown
in Figureinvolved
16.
shown in Figure 16.
12
CPWR-AN12, REV A
12 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
V(coss)
1.8KV
Key:
1.6KV
Green:
Blue:
Red:
Gray:
Pink:
1.4KV
1.00*tres
1.25*tres
1.50*tres
1.75*tres 2.00*tres
2nd maxima higher than 1st maxima
1.2KV
1.0KV
0.8KV
0.6KV
0.4KV
0.2KV
0.0KV
0ns
10ns
20ns
30ns
40ns
50ns
60ns
70ns
80ns
90ns
Figure 16: Voltage overshoot as a function of switching speed longer than resonant period
Figure 16: Voltage overshoot as a function of switching speed longer than resonant period
These results are particularly interesting, in that the overshoot keeps decreasing with increased
switching
however, the
maximum
value
shifts
from the
first
peak to the
peak.
This
These
resultstime;
are particularly
interesting,
in that
the
overshoot
keeps
decreasing
withsecond
increased
switching
time;
however,
the is
maximum
valueswitching
shifts from
the first
to the second
peak. This
infers
that there is
infers
that there
a particular
speed
thatpeak
minimizes
overshoot.
Several
simulations
a were
particular
switching
speedthis.
that A
minimizes
were
run to investigate
this. A
run to
investigate
measureovershoot.
script wasSeveral
writtensimulations
to report the
maximum
peak voltage
measure
script
written
the
maximum
voltagewas
regardless
of which
peak
it occurs
on, and
regardless
ofwas
which
peaktoitreport
occurs
on,
and thispeak
simulation
done for
several
values
of link
this
simulation
done for
several values
of link
The baseline
resonant frequency
the analysis
voltage.
Thewas
baseline
resonant
frequency
forvoltage.
the analysis
was calculated
using the for
total
was
calculatedand
using
total inductance
the energy
value of
Coss
at the particular
linkThe
at the particular
link
voltage
of interest.
inductance
thethe
energy
referencedand
value
of Coss referenced
voltage
interest.
The
resultsofare
shown
in results
Figure are
17.shown in Figure 17.
13
CPWR-AN12, REV A
13 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
Figure 17: Observed minimum overshoot points as a function of relative fall time for various values of link voltage.
The results show that minimum overshoot occurs for a voltage fall time slightly longer than one period
of the resonant frequency. There are repeated minimums at fall times equal to integer multiples of the
resonant period. Also note that there are relative maximas that occur for multiples of approximately
n+1/2.
It would be of great benefit to get some kind of measurement of the voltage overshoot without the
parasitic effects to confirm that voltage ratings are being observed. Parasitic inductance makes it difficult
to directly measure the overshoot voltage of the upper device during turn-on. However, a fairly simple
simulation can be done to predict the overvoltage. The schematic shown in Figure 18 uses measured
module current data, drive the simulated Coss and observe the voltage. The measured module load current
is a table-based piecewise linear current source the module current during turn on. As before, the diode
and capacitor simulate the behavior of Coss with voltage. The load current is modeled as a constant current
source.
CPWR-AN12, REV A
14 Understanding the Effects
of Parasitic Inductance
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For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
out2
Measured
module current
Equivalent circuit
for Coss
Empirically set
load current
Figure 18: Overshoot voltage estimation simulation
Figure 18: Overshoot voltage estimation simulation
Some empirical tuning needs to be done during the simulation to set the load current to the
Some
tuning
to be done
during
the simulation to
set the load
to the which
value that
valueempirical
that forces
theneeds
overshoot
voltage
to asymptotically
approach
the current
link voltage,
in this
forces
the
overshoot
voltage
to
asymptotically
approach
the
link
voltage,
which
in
this
case
is
800V.
case is 800V.
The CAS100H12AM1 module was used to investigate this method of assessing the voltage overshoot. The
The CAS100H12AM1 module was used to investigate this method of assessing the voltage
module current was gathered in a test circuit shown in Figure 19.
overshoot. The module current was gathered in a test circuit shown in Figure 19.


 





















 

Figure 19 Module test circuit schematic for the CAS100H12AM1
Figure 19: Module test circuit schematic for the CAS100H12AM1
15
CPWR-AN12, REV A
15 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
The conditions of the test were:
Test conditions:
Ipulse = 100A
Vlink = 800V
Vgate = 20/-5V
Rgate = 5.1 Ω
Load Inductance = 200 μH
The measured waveforms are shown in Figure 20.
1600
160
Module Current
1200
VTP2 (V)
140
TP2 to Ref
120
1000
100
800
80
600
60
400
40
200
20
0
-200
Imodule (A)
1400
0
0
50
100
150
200
Time (nsec)
250
300
350
400
-20
Figure 20: Module test waveforms
The lower trace is the actual module current and the upper trace is the overshoot voltage. The load current
source was tuned to 100.7A to allow the overshoot voltage to asymptotically approach 800V steady state
as shown. In this case, the overshoot voltage was approximately 900V and occurred on the third peak.
CPWR-AN12, REV A
16 Understanding the Effects
of Parasitic Inductance
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For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
V(out2)
1.0KV
V(800v)
0.9KV
0.8KV
0.7KV
0.6KV
Estimated overshoot voltage
0.5KV
0.4KV
0.3KV
0.2KV
0.1KV
0.0KV
-0.1KV
I(I1)
160A
Measured module current
140A
120A
100A
80A
60A
40A
20A
0A
-20A
0ns
40ns
80ns
120ns
160ns
200ns
240ns
280ns
320ns
Figure 21: Approximation of voltage overshoot using measured module current
360ns
400ns
Figure 21: Approximation of voltage overshoot using measured module current
17
CPWR-AN12, REV A
17 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
EMI
EMIConsiderations:
Considerations:
EMI Considerations:
The
Thefaster
fasterswitching
switchingspeed
speedofofthe
theSiC
SiCMOSFET
MOSFETmodule
modulecan
cangive
giverise
risetotoEMI
EMIissues
issuesbeyond
beyond
The
faster
switching speed
the modules.
SiC MOSFET
give rise
to gets
EMI issues
beyond
what
is end of
what
isiscustomary
for
IGBT
typical
practice,
EMI
near
the
what
customary
forSi
Siof
IGBT
modules. InInmodule
typicalcan
practice,
EMI
getsaddressed
addressed
near
the
end of
customary
for
Si
IGBT
modules.
In
typical
practice,
EMI
gets
addressed
near
the
end
of
the
product
the
theproduct
productdevelopment
developmentprocess
processwhen
whenlarge
largesections
sectionsofofthe
thedesign
designare
arefrozen;
frozen;however,
however,this
this
development
process
when large
sectionsfreedom
of the design
are frozen;
however,The
severely
limits the
severely
the
ofofdesign
totomitigate
EMI
isistoto
severelylimits
limits
thedegrees
degrees
design freedom
mitigate
EMIissues.
issues. this
Theusual
usualsolution
solution
degrees
ofswitching
design freedom
todown
mitigate
EMI
The usual solution
is to Unfortunately,
slow the switching
speed
down
slow
until
the
EMI
are
method
slowthe
the
switchingspeed
speed
down
until
theissues.
EMIrequirements
requirements
aremet.
met.
Unfortunately,this
this
method
until
the
EMI
requirements
are
met.
Unfortunately,
this
method
compromises
the
key
speed
advantage
compromises
compromisesthe
thekey
keyspeed
speedadvantage
advantageofofSiC
SiCMOSFETs.
MOSFETs. Therefore,
Therefore,ititisisimportant
importanttotoaddress
addressof
SiC
MOSFETs.
Therefore,
it
is
important
to
address
EMI
early
in
the
design
process.
EMI early in the design process.
EMI early in the design process.
One of the critical things to address in the EMI design is the effects of fast dV/dt. Changing the voltage
One
things
the
design
isisthe
effects
Oneofaofthe
thecritical
critical
things
toaddress
address
theEMI
EMI
design
the
effectsofoffast
fastdV/dt.
dV/dt. Changing
Changingthe
the
across
capacitor
results
into
current
flowinin
given
by the
following
equation:
voltage
voltageacross
acrossaacapacitor
capacitorresults
resultsinincurrent
currentflow
flowgiven
givenby
bythe
thefollowing
followingequation:
equation:
𝑑𝑑𝑑𝑑
𝑑𝑑𝑑𝑑
𝐼𝐼𝐼𝐼==𝐶𝐶𝐶𝐶
𝑑𝑑𝑑𝑑
𝑑𝑑𝑑𝑑
AAsmall
smallyet
yetfinite
finitecapacitance
capacitanceexists
existsbetween
betweenthe
thetraces
tracesininthe
theSiC
SiCMOSFET
MOSFETmodule
modulesubstrate
substrate
A small yet finite capacitance exists between the traces in the SiC MOSFET module substrate and
and
andthe
themounting
mountingbaseplate.
baseplate. The
Thehigh
highvalues
valuesofofdV/dt
dV/dtgive
giverise
risetotoextremely
extremelyfast
fastand
and
the mounting baseplate. The high values of dV/dt give rise to extremely fast and significantly large
significantly
large
displacement
current
spikes
that
get
injected
into
the
module
heat
sink.
significantly
large
displacement
current
spikes
that
get
injected
into
the
module
heat
sink. This
This
displacement current spikes that get injected into the module heat sink. This path also exists when using
path
also
exists
when
using
a
SiC
IGBT
module;
however,
the
dV/dt
is
significantly
slower.
This
path
also
exists
when
using
a
SiC
IGBT
module;
however,
the
dV/dt
is
significantly
slower.
This
a SiC IGBT module; however, the dV/dt is significantly slower. This situation is illustrated in Figure 22.
situation
situationisisillustrated
illustratedininFigure
Figure22.
22.
AC
AC
MAINS
MAINS
AC
AC
M1
M1
Common
Common
mode
modechoke
choke
CD1
CD1
HF
HF
OUTPUT
OUTPUT
AC
AC
M2
M2
Heatsink
Heatsink
CD2
CD2
YY
Capacitors
Capacitors
Displacement
Displacementcurrent
currentpath
path
LLSTRAY
STRAY
Common
Commonmode
modecurrent
current
Ground
Ground
Misc
Miscconductive
conductivepathways
pathways
through
throughthe
theenclosure
enclosure
Figure
Figure22:
22: Displacement
Displacementcurrent
currentpath
path
Figure 22: Displacement current path
The
Themodule
modulesubstrate
substratecoupling
couplingcapacitances
capacitancesare
areidentified
identifiedas
asCD1
CD1and
andCD2.
CD2. The
Thefast
fastdV/dt
dV/dt
present
atatthe
output
OUTPUT)
causes
flow
present
thehigh
highfrequency
frequency
output(HF
(HFare
OUTPUT)
causes
displacement
currents
to
flowinto
into
The
module
substrate
coupling
capacitances
identified
as CD1displacement
and CD2. The currents
fast
dV/dtto
present
at the
the
Consider
M2
isisaathe
rapid
change
ininvoltage
theheatsink.
heatsink.output
Consider
thecase
casewhen
whenMOSFET
MOSFET
M2switches:
switches:
there
rapid
change
voltage
high
frequency
(HF the
OUTPUT)
causes
displacement
currents
tothere
flow into
heatsink.
Consider
the
on
which
isisswitches:
connected
totothe
OUTPUT,
and
aadisplacement
through
onthe
thedrain
drain
which
connected
the
HF
OUTPUT,
and
displacement
current
flows
through
case
when
MOSFET
M2
there
is aHF
rapid
change in
voltage
on the draincurrent
which isflows
connected
to the
CD2
and
heatsink.
current
flows
through
conductive
pathways
such
CD2
andinto
into
the
heatsink.The
The
current
flows
through
miscellaneous
conductive
pathways
such
HF
OUTPUT,
andthe
a displacement
current
flows
through
CD2miscellaneous
and into the heatsink.
The current
flows
through
as
mounting
brackets
enclosure
itself.
YYcapacitors
asfasteners,
fasteners,conductive
mountingpathways
bracketsand
andthe
thefasteners,
enclosure
itself. The
The
capacitors
willhave
havesome
someThe Y
miscellaneous
such
as
mounting
brackets
and the will
enclosure
itself.
capacitors will have some effect on directing this current back to the source of M2; however, some stray
18
18
CPWR-AN12, REV A
18 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
effect on directing this current back to the source of M2; however, some stray inductance will be
present to limit their effectiveness. The remainder of the displacement current flows into the
mains ground lead, resulting in additional conductive EMI. Furthermore, this displacement
current flowing
difficult-to-identify
paths inside the
actdisplacement
as a loop antenna,
inductance
will be in
present
to limit their effectiveness.
The enclosure
remainder will
of the
current flows
injecting
voltage
spikes
nearby
wires andconductive
conductors.
This
can be problematic
with control
into
the mains
ground
lead,onto
resulting
in additional
EMI.
Furthermore,
this displacement
current
loops in
and
fault detection circuits.
flowing
difficult-to-identify
paths inside the enclosure will act as a loop antenna, injecting voltage spikes
onto nearby wires and conductors. This can be problematic with control loops and fault detection circuits.
One of the most effective ways to mitigate this issue is to provide a definite local return path for
One of the most effective ways to mitigate this issue is to provide a definite local return path for the
the displacement current. There are some general approaches to mitigating displacement
displacement current. There are some general approaches to mitigating displacement current by essentially
current by essentially breaking the loop and providing a local return path for the displacement
breaking the loop and providing a local return path for the displacement currents. The first approach
currents. The first approach is to simply float the heatsink and provide a current path back to
is to simply float the heatsink and provide a current path back to the source of M2 using an additional
the source of M2 using an additional capacitor. This approach is shown in Figure 23. This
capacitor. This approach is shown in Figure 23. This effectively breaks the path; however, it might not
effectively breaks the path; however, it might not always be possible to do this because of
always be possible to do this because of mechanical or safety constraints. Another option is to connect the
mechanical or safety constraints. Another option is to connect the heatsink to ground through
heatsink to ground through some high permeability choke as shown in Figure 24. The choke will introduce
some high permeability choke as shown in Figure 24. The choke will introduce high impedance
high impedance at high frequencies, while providing a low resistance connection to ground at the mains
at high frequencies, while providing a low resistance connection to ground at the mains
frequency. This approach retains the safety feature of keeping the heat sink grounded.
frequency. This approach retains the safety feature of keeping the heat sink grounded.
CD1
M1
CD1
M1
HF
OUTPUT
HF
OUTPUT
M2
Heatsink
M2
Heatsink
CD2
CD2
C
L
C
Ground
Figure 23: Float heatsink
Figure 24: Inductively isolate heat sink
Figure 23: Float heatsink
Figure 24: Inductively isolate heat sink
19
CPWR-AN12, REV A
19 Understanding the Effects
of Parasitic Inductance
This document is provided for informational purposes only and is not a warranty or a specification.
For product specifications, please see the data sheets available at www.cree.com/power. For warranty
information, please contact Cree Sales at [email protected].
Conclusions and Recommendations:
The customary application guidelines for Si IGBT modules are only a subset of what is needed to optimally
apply SiC MOSFET modules. Power circuit parasitic inductances and capacitances form resonant circuits
that lead to voltage overshoots under hard switched conditions. Due to the extremely fast switching speeds
attainable with SiC MOSFETs, the voltage overshoot occurring at turn-on can easily exceed the maximum
device voltage rating. Introducing loss into the power circuit to damp the overshoots is typically impractical.
Control of the overshoots (without reverting to a snubber) can be effectively accomplished by controlling
the voltage fall time of the corresponding MOSFET that is turning on. This can easily be accomplished by
selecting the appropriate turn-off gate resistance to ensure that the fall time is greater than the period of
the natural frequency of the resonance.
Multiple points of minimum overshoot exist at approximate integer multiples of the resonant frequency
period. The fastest allowable switching speed is achieved by designing the power circuit to push the
resonant frequency as high as possible. The capacitive portion of the resonant circuit is part of the SiC
MOSFET/JBS diode combination and is therefore fixed. The parasitic inductance can be minimized by careful
layout practices.
The fast switching speed of the SiC MOSFET module also requires careful attention to EMI considerations,
which need to be addressed early in the design cycle. Simply slowing down the switching speed to meet
EMI requirements defeats the purpose of using SiC MOSFETs. One of the chief concerns is the displacement
currents flowing through the module baseplate following path. It is recommended that steps be taken to
break unintentional paths by providing highly localized displacement current paths.
Copyright © 2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the
Cree logo, and Zero Recovery are registered trademarks of Cree, Inc.
This document is provided for informational purposes only and is not a warranty or a specification. This product is currently
available for evaluation and testing purposes only, and is provided “as is” without warranty. For preliminary, non-binding product
specifications, please see the preliminary data sheet available at www.cree.com/power.
20
CPWR-AN12, REV A
Understanding the Effects
of Parasitic Inductance
Cree, Inc.
4600 Silicon Drive
Durham, NC 27703
USA Tel: +1.919.313.5300
Fax: +1.919.313.5451
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