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INSTITUTO TECNOLOGICO DE COSTA RICA
ESCUELA DE INGENIERÍA ELECTRÓNICA
CURSO: EL- 4311 ESTRUCTURA DE MICROPROCESADORES
PROF.: Ing. José Alberto Díaz García
4 de Agosto del 2006
PRIMER PROYECTO DE INVESTIGACIÓN
a. INTRODUCCIÓN
Para la solución de sistemas lineales utilizando microprocesadores se requiere
de funciones matemáticas que nos permitan realizar: multiplicaciones, divisiones,
potencias, raíces, logaritmos y antilogaritmos, entre otras. Existen muchos algoritmos
que nos permiten realizar estas funciones, sin embargo desde el punto de vista de la
eficiencia del procesador son procedimientos que lo hacen operar lentamente en la
ejecución de tareas, ya que se necesitan muchos cientos de ciclos de reloj para que se
ejecuten.
Desde el punto de vista analógico el problema fue resuelto hace mucho tiempo,
por ejemplo, en 1985 Analog Devices colocó en el mercado el circuito integrado
AD538 (se adjuntan las hojas de datos) que realiza todas estas funciones.
La idea de este trabajo consiste en realizar un conjunto de módulos
combinacionales desarrollados en un lenguaje de programación orientado a hardware
(Verilog o VHDL) que realicen esas mismas operaciones, para luego insertarlo en un
microprocesador con el fin de resolver modelos matemáticos de sistemas lineales.
b. OBJETIVO GENERAL
Diseñar e implementar una serie de módulos combinacionales empotrados en
un FPGA (Spartan 3) y desarrollados con un lenguaje de programación orientado a
hardware (Verilog o VHDL) que realicen las operaciones de: multiplicación, división,
potencias, raíces, logaritmos y antilogaritmos.
c. OBJETIVOS ESPECIFICOS
1. Diseñar un sistema que contenga módulos para multiplicación, división,
potencias, raíces, logaritmos y antilogaritmos, en lógica combinacional,
utilizando un lenguaje de programación orientado a hardware Verilog o
VHDL y que cumplan con las especificaciones que se suministran.
2. Simular utilizando la herramienta ModelSim de Mentor Graphics, el
comportamiento de cada uno de los módulos.
3. Utilizar las diferentes herramientas que ofrece el paquete ISE de Xilinx para
sintetizar, enrutar y optimizar los diseños digitales.
4. Generar la documentación necesaria que cumpla con las especificaciones
que se suministran.
1
d. ESPECIFICACIONES DE DISEÑO
a. Todo el sistema debe ser combinacional.
b. El sistema debe utilizar la mínima cantidad de recursos del FPGA con el fin
que se puedan empotrar en el microprocesador existente.
c. Utilice el Spartan III, XC3S1000-FT256.
d. No utilice los comandos de suma, resta, multiplicación, división que ofrecen
los lenguajes de programación, ya que estos consumen muchos recursos del
FPGA.
e. Realice una descripción detallada del método utilizado para realizar cada
una de las funciones.
f. Para el diseño del sistema utilice el procedimiento de diseño modular.
g. Debe indicar claramente las especificaciones de las entradas y las salidas.
h. Los datos de entrada deben codificarse en 16 bits y las salidas en 32 bits.
i. Todas las operaciones utilizan operandos enteros.
j. Las señales de selección de las funciones cumplen con la siguiente tabla.
SELECCION
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
FUNCION
Multiplicación
División
Potencia
Raíz
Logaritmo natural
Antilogaritmo natural
e. SIMULACIÓN DE LOS MODULOS.
a.
b.
c.
d.
e.
El archivo de simulación debe incluir como mínimo una prueba para
cada uno de los módulos desarrollados.
Se debe realizar la simulación “post-place and route”, para ello tome
en cuenta que el programa se empotrará en un Spartan III,
XC3S1000-FT256 de Xilinx.
El tiempo de retardo máximo para los módulos que se simularán
debe ser menor o igual a 20nseg.
El programa ISE de Xilinx necesario para esta simulación se
encuentra instalado en las salas de computadores A8 y A7.
Suministre un resumen del proyecto en donde se muestren todos los
recursos que se utilizan.
2
f. DOCUMENTACIÓN.
Incluya como mínimo los siguientes elementos
a. Aspectos generales del trabajo como por ejemplo: portada, sumario,
introducción,
índices,
descripción
del
problema,
conclusiones,
recomendaciones, bibliografía, etc. (según referente a presentación de
informes).
b. Presentación: debe presentar un informe escrito del proyecto y una
versión electrónica donde se incluya:
1.
2.
3.
4.
Informe del proyecto, en formato Word para Windows.
Módulos del sistema (archivos *.v).
Bancos de prueba utilizados para la simulación (archivos *.v).
Incluir el archivo de simulación generado en el modelo “del
emplazamiento y ruteo”.
5. Establezca en su documentación las rutas críticas, suministre una
explicación de sus datos.
6. Analice los diferentes reportes que se generan en cada una de las etapas
del proceso de síntesis.
7. Incluya las relaciones lógica/ruta y área/frecuencia en cuanto al uso del
FPGA, documente y justifique sus datos.
c. Diagramas: Se deben incluir diagramas que permitan el entendimiento del
diseño implementado por ustedes. Oriéntese en el diseño modular, recuerde
que se esta modelando hardware.
d. Los programas deben documentarse según la orientación indicada en el
documento “Documentación de procedimientos” disponible en
www.ie.itcr.ac.cr/jdiaz.
a. EVALUACIÓN.
La evaluación del proyecto es integral, esto es:
a.
Se deben entregar TODAS las partes para ser evaluado. Por ejemplo no se aceptan
trabajos en donde se dejen partes incompletas donde se evidencie su realización con el fin
de obtener simplemente unos puntos para la nota, el proyecto debe tener sentido lógico.
b. En caso de que necesite ayuda sobre aspectos técnicos relacionados con el informe
consulte esta dirección http://www.apastyle.org/ encontrará los estándares para realizar
bibliografías, referencias a documentos encontrados en Internet (referencias electrónicas),
etc.
3
c. La ponderación de cada punto se indica en la Tabla 4.
Tabla 4. Valoración de los puntos abarcados.
DOCUMENTACIÓN
Portada e índices (-1, hasta -10)
Redacción y ortografía (-1, hasta -10)
Introducción (-1, hasta 10)
Diagramas de bloques
Descripciones de señales
Diagramas de estados
Diagramas de flujo
Eficiencia de programación
Programas escritos en Verilog
Conclusiones y recomendaciones
Bibliografía
Archivos con el programa
Archivos de simulación
8
8
10
10
10
10
10
2
1
1
70
SIMULACIÓN
Multiplicación
División
Potencia
Raíz
Logaritmo natural
Antilogaritmo natural
5
5
5
5
5
5
TOTAL
30
100 %
4
COMPLETE M[INOLlTHIC ANALOG MULl'IFlINC'I'I11N CHIP
AD538 ~mbodies~ ( ~with
f lHigh
) ~Performance and Wide Dynamic Range
Performs Multiplication, Division; Computes Powers, Roots, Logs,Antilogs
by Lew Counts, Charles Kitchin, and Steve Sherman
The AD538' is a Real-Time Analog Computational Unit (ACU)
in an 18-pin DIP. It performs the function,
A
0
b
where the OUTl'UT is a positive voltage and the variables, X, Y,
and Z, represent inputs in the form of positive voltage or current.
The ADS38 can be used for multiplication and division (simultaneously), powers and roots, logarithms and antilogarithms, Jts
repertoire ot analog computing operations makes the device useful
in ratio measurements, signal conditioning, linearization, measuremcncof energy andstochastic quantities, andcontrol.
The ADS38's versatility is the serendipitous result of a quest for
a monolithicanalog division circuit that could accurately compute
ratios over a wide dynamic range of denominator values; indeed,
this is its most important application. With a 1000:l dynamic
range (V, = V, = 10 mV, V, = 10 V, V, = 10 V), the maximum
total error (ADS38B) is only 2.5% of output - with no external
trims.
Conventional IC analog multipliers, configured and optimized for
division, have yet to achieve even the modest 100:l dynamic range
specification that might be considered practical for many divider
applications; for example, the premium AD535KW (A?rolog
Dialogue 12-2, 1978) is specified to have maximum total error o f
2% over a 50: 1 dynamic range o t denominator input, with no external trims.
Besides overcoming the dynamic-range limitations of dividers
based on multipliers, the AD538 has low input offsets (100pV or
less) and low noise, essentially proportional to output for outputs
above 10 mV: for I-volt outvut in a 1-kHz bandwidth, peak-topeak output noise is about 1.4 mV. In addition to performing onequadrant multiplication, it can also be configured for division in
nvo quadrants, i.e., a bipolar numerator by a unipolar denominator; and it can calculate a wide range of powers or roots,
whether positive (direct) or negative (inverse), integer or fractional
(for example, 2.25, '/I, - 2). With feedback, it can be configured
to perform rms and vector operations.
Though generally similar in function-and many o t its applications-to the Model 433' module (see Analog Dialogue 6-2
(1972) and Chapter 3-6 of the Nonlinear Circuits ~ o n d b o o k ' ) ,
the ADS38 is considerably more versatile and much lowcr in cost.
Figure 1 is a combined block diagram and pinout of the ADS38;
it comprises five precision op amps-laser-trimmed ro less than
100 FV of offset voltage, an accurate reference source (configurable for -t 10V or +2V), and an error-corrected computing core.
Functionally, the device is disposed into a log-ratio section, an
antilog section, and a voltage reference. High performance, with
the high-yield bipolar process employed, is the result of advanced
circuit design and a thermally balanced chip layout.
'Fortechnicaldata,uscthe
reply card.
'See REFERENCES o n pagc6.
Analog Dialogue 19-1 1985
v.
SIGNAL
GNO
PWR
GNU
Figure 1. Block diagram and pin connectionsoftheAD538.
Functions are determined by the choice of inputs and appropriate
connections of the device's pins. In some cases, one or two external
resistors will be required. In addition to the overall transfer function, the constituent log-ratio and antilog functions-and the reference-are available for independent use.
Volume 19, Number 1,1985- 28 Pages
.iD538Brcaks through with multiple analog functions.
..,.....
Cover
Ediror's Notes, AD1 Authors . . . . . . . . . . . . . . . . . . . . . . . . 2
CDmple~eMonolithir Analog Multifunction Chip,
output = Y (Z/X)"( ~ D s 3 8 ). . . . . . . . . . . . . . . . . . . . . . . 3
Dual 1 ,?-Bit Microprocwsor-Compatible DAC in 0.3'DIP (AD7549) . . . 7
24 X 24-Hit Firrd-Poin! CMOS 1)igital Multiplipr (ADSP- 1024) . . . . . . 8
Low-Cox! Voltage-to-Freqrtency Conuer~erChip (AD654) . . . . . . . . . 10
High-Per{onnunce Precision Ifybid IsoLtion Amplifier (AD29S) . . . . .12
New Plug-In Signal-Conditioning Modules for 3 B Series {3B47,3B17)
. I3
Double-Buffered 14-Bit Monolithic CMOS Multiplying DAC (AD7535) . 14
Low-Cost 8-Bit Monolithic ADC Converts m 1 . 3 6 M
~ a x (AD7820)
15
Sofiwure-Programmable-GainAmplilier-Trackltlold {or
Data-Acquisilion (AD365) . . . . . . . . . . . . . . . . . . . . . . . .
16
~ligl,-PPr/onnrmr~1@Bit. 800-ns AID Conwrter {AD ADC-8 16) . . . . .17
Real-WorldIIOCprds/oriheCMOSSTDDUS(RT1-1280112811128L).
18
Thennometer wilh Resolutfon Better than 0.0001 "C . . . . . . . . . . . . 2D
Ncw-ProduccBriefs:
Fast 8-Bit Monolithic CMOS ADC Convcns in 1 0 (AD7S76)
~
. . . .22
Low-Cost 12-Rit Rnolvcr-to-Digital Convcner (25x0) . . . . . . . . . . 22
Ncw Options in I.IIZG 4-IC-8-Rit Raster I>AC Family . . . . . . . . . . 22
Thermocouple Xmplificrs in Cerdip for T y p j and K (hDS94Q1595Q)
23
Prrcision BiFET Op Amps in Metal and Cerdip (AD61 I ) . . . . . . . . 23
Precision Op Amp with Exisring Second Sources (AD OP-37) . . . . . . 23
16-Bir Hybrid A/D Convcrrcr - 1 7 p maw Conversion Time (AD376) 24
Digital-r~ResolvrrlSynchroTrans~ormcrs-LOH' Profile, low-Frequency . 24
Hr-Kcl for Non-Military Parts - Analog Deviccs PLUS Pragnm . . . . . 24
Mort Authors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LS
New Analog Dcviccs Division Fcllow Namrd: Peter liolloway . . . . . . 25
Worth Re3ding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6
Porpurn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7
.....
hdvcrrixmcnt:
. . . . . . . . . . . . . . Rack Cnvcr
.
...
.
.
,
I
I
CHARACTERISTICS
Although its sub-functions can be used independently, the AD538
is designed and specified as a complete analog computing system,
with overall performance specified for both voltage and current inputs. Its dynamic range is 80dB for voltage signals-from 1mV to
1OV, and its current input range is 0.1 to 4 0 0 p 4 (72dB).
For flexibility, the summing junctions at the inputs of four of the
five amplifiers are accessible for external connections, This makes
it possible to sum several signals-including feedbacks and signals
from current sources-into the same input terminat, and to add
offsets or change the scaling for input voltages.
The wide range of dual power-supply voltages that can be usedfrom ? 18 volts to 2 4 . 5 v o l t q i v e s the user many options, including standard ? 15-volt supplies, the increasingly popular
2 12-volt supplies, and even 2 5 volts (employing the 2-volt reference connection).
Multifunction devices that nominally perform the Y(Z.0oM function have been on the market since 1972, in the form of modules
and-later (in less-complete form)-hybrids. 7he ADS38 is the
first monolithic IC on the market to perform this function. As
Table 1 indicates, though monolithic, it sacrifices neither performance nor completeness-and in fact adds some hitherto unavailable features.
hionolilhic IC
Hybrid lC
(AD538B)
Mixerror ( a s a r n u l ~ ~ p l l r r ]
100: 1 dynamlcrangc
1 O.S%oloutput1 1 5 0 p VA
O r o l ~ ~ w i r l c r a n ~ c 1.04boloucpuc
~
=2(OpVA
Ma%banduidrh
QOkH7.
I n l c r n ~ rcfcrcncr
l
vol~agc I 0 V, 1 V
Supply vol~rgcringc
5 4 . 5 Vro
18 V
Uppcr 11mi1
+18V
Lower limu
14.5V
Supply rurrcnl
4.5 rnA
I'schgc
IR-pli~DIP (IC]
=
Table 1. Examples of salient features of multifunction
device technologies.
HOW ITWORKS
Logarithm
T h e upper portion of the circuit shown in Figurc I computes the
logarithm of the ratio of inputs Z and X. The inputs may be eithcr
current (I, and I,), voltage (V, and V,), or any combination. Voltage inputs, applied at the V, and V, terminals, are converted to
current by the (nominally) 25 k n resistors; the resulting currents,
flowing through the feedback transdiodes, develop logarithmic
voltages at the outputs of A1 and A2. The difference between the
output voltages, taken by subtractor A3, is proportional to the
logarithm of the ratio of the input voltages. The output of A3 is
available at pin 3, labeled "B".
k is Boltzmann's constant, q is the charge on an electron
(Wq = 86.17pV/K), and T is absolute tetnperature in kelvins
("C+ 273.LK). At T = 3OOK (26.8"C), VE=25.85mV for each
power of e, or 59.52mV per decade. This voltage constitutes a
basic logarithmic output; however it would be useful: to
scale the 60-millivolt output to a more convenient level, to cornpensate for the 86pVIK (or 3,330 ppm) temperature sensitivity
(dVJdT = 86.17pV/K), and to buffer the output. This can bc
readily done, as will be seen in the Applications section.
For multiplication and division, it is necessary to add a voltage representing the logarithm of V, or ly and take the antilogarithm, or
exponential. This operation is performed in the lower portion of
Figure 1. The total input current a t rhe summing point of amplifier
AS, determined by V,, I,, andlor any additive currents from
sources wired to that point, flows through the feedback transdiode
and dcvelops a negative voltage at the output of AS proportional
tothe logarithm of that current.
Amplifier A4 i s connected to perform a current-to-voltage conversion, which results in an antilogarithmic operation. With C (pin
12) grounded, and no offset current added at 1 (pin 9), the output
voltage will be equal to the effective Y-input voltage (all currents
at 1, referred to V,). When C is connected to the log-ratio output
of A3 (B), its positive voltage is summed in series with the transdiode basc-emitter voltage drops, and A4 ~erformsthe balancing
operation (inputs and outputs ot this scction referred to Vy
and V,):
therefore,
and
Vc may be derived from an external voltage for direct antilogarithmic operations; however, in the case of multiplication and
division, since Vc= V,and, from (2),
kT
V, = -In'
V
VY
thcn
(4)
Powers ond roots
I f the output of A3 is amplified (by connecting resistance between
terminals A and D to attenuarc its feedback), or attenuated (by
connecting a voltage divider betwecn Band C), the gain or attenuation of the log signal affects the exponent of the (ZM)term. I f
h.1 is the multiplication factor of the resistor-programmed gain or
attenuation, Equation (4) becomes
Vc = MV,'
=
kT
M-In'
q
V
VY
(6)
where VU' is the voltage a t B when h.1 = 1 . Thus, Equation ( I ) . expressed i n voltage, is:
When the AD538 is used for two-variable analog division
(ratios)-r powers and roots-the Vy input is used to sct a convenient scale factor. Amplifier A4 buffers and scales the antilog section output. The output amplifier's summing junction has been
made available to provide for offsetting o r external trimming of
the output stage-and to allow direct connection of the log-ratio
section to this stage, thus pcrmining it to provide the amplified,
buffered output of a straight log amplifier.
Reference
At pins 4 and 5 are output voltages from a stable (1SppnlPC typical) bandgap voltage reference, provided to eliminate the need ior
an external source of the necessary reference voltages. The reference portion o f the AD538 makes available + 10 volts (buffered)
and -1-2volts at the tap of a 5: 1, 20-kn laser-trimmed voltage di-
Analog Dialogue 19-1 1985
vider (3,200-ohm nominal output resistance). Amplification of the
1-2-V
bandgap voltage is determined by the resistance ratio. If 10volt output is not desired (for example, in operation on kS-volt
power supplies), a buffered 2-volt reference may be obtained by
jumpering pins 4 and 5 together.
APPLICATIONS
The following circuits show the basic connection modes for the
ADS38 and may suggest a variety ofuses.
Multiplier
Figure 2 shows the basic connections for multiplication. B is connected dircctly to C, (i.e., M = I ) , and the reference voltage is connected as V,. If the 10-volt reference is used, the output is
V,=V,VJlOV.
Figure 4. Comparison of division errors in the AD538 and
the AD535, when connectedfor division.
scale-factor and the offset-trim scheme shown in Figure 5, the
error can be reduced to 20.25% of reading. The offset trim current is summed at the l, input. This scheme may be used for any
of theAD538 applications, and offset trim currents may beapplied
to any o l the current-summing inputs for optimizing particular
modes of operation.
- v.
--
-
Figure2. Basic connection for multiplying two voltages.
One-Quadrant Divider
Figure 3 shows the basic connections for division. B is connected
directly to C and M is set to 1 .O; the reference voltage is connected
as V,. I f the 10-volt reference is used, the output voltage becomes
v, = I ov VJV,.
Figure 5. Connection of t h e AD538 for multiplication and division ( W X ) , with offset trim for improved accuracy.
Figure 3. Basic connection for dividing t w o variables.
As a divider with 10-volt scaling, the ADS38 has a -3-dB
bandwidth of about 370kHz for 1 to 10-volt levels; at lower
amplitudes, the bandwidth decreases gradually to about 2OOkHr
ac the 2-millivolt input level. The input dynamic range is approximately 74dB, from the 2-mV noise threshold to the 10-volt + clipping level. Figure 4 compares the periormance of the AD538 as a
divider with a typical contemporary multiplier-typedivider.
Division with 2-Qr~adrantN~trneratot
Figure 6 shows how the AD538 divides a numerator that can
swing positive or negative by a positive denominator voltage. l o
insure that the current flowing through the "2" transistor is positive, the numerator and denominator voltages (Zand X) are translated ro reduced currents (1, and I,) through external 34.8-kfl resistors; the denominator is translated into a n additional current
that is summed into the numerator input, V,, by its on-chip 25-kn
Higlt-Performance Mtrltiplier-Divider
Figure 5 shows how the AD538 is configured as a high-performance one-quadrant multiplierldivider, to compute the three-variable function, V y V f l , . Conventional 4-quadrant analog multipliers cannot handle three variables, and-as noted earlier-are all
but unusablewith denon~inatorshavingwidedynamic range.
The circuit has a typical bandwidth of 400kHz for values of V,
varying over a 100: 1 range, from lOOmV to 10 volts. The
maximum error, over a 0 to 10-volt range for the other two variables, will be approximately 20.5% of reading. With the external
Analog Dialogue 19-1 1985
Figure 6. Basic connection for division with
numerator.
bipolar
resistor. As long as the magnitude of numerator signal, 2,is less
than that of X, the current into the Z amplifier will be positive,
with the signal inputs attenuated by a factor, A ( = 2S134.8), relative to the additional numerator input. Thus,
With V, constant, V, (1/A) is constant, and its dc valuc can besubtracted out-if desired-by summing an appropriate current into
input I, pin 9. Trims providecancellarion.
Log Ratio
Figure 7 shows the basic connections for log ratio, using the logratio section and the output amplifier. An overall gain of 15.9 V N
is distributed to minimize errors contributed by the output amplifier: the gain is 5 in the input section and about 3.2 in the output
section. The log-ratio output, at B, is connecred to the summing
junction of the output amplifier (I,, pin 9) via a remperature-variable resistor consisting of two resistors in series-a 90.9-ohm, 1 %
metal-film resistor and a 1,000-ohm, +3,500 ppmPC temperature-compensation resistor. Together, they have a resistance of
1,09 1 ohms with a 3,300 ppmPC tempco. The nominal relationship (if the feedback resistance =25,00Oohms) is
ERROR SPECIFICATIONSOF ANALOG DIVIDERS
Since there are many sources of error in a multifunction component, specifying each individually could, in concept, provide a
means of determining the maximum error for any condition. However, it is often more useful to have a single total errorspecification
that serves as an explicit predictor of performance in a particular
configuration, such as division.
Total error, in the multiplier or divider mode, is the sum of three
terms reflectingnonlinearity, output offset, and numerator offset:
1.O% (reading) + ZSOpV
+
[
F
a
IS O ~ V ]
forV, = lmVtolOV,V, = IOmVto lOV,andV, = Oto 1OV.
The ADS38A's 100:l divider accuracy specfication is + 1% of
reading 2 SOOFV. The B-grade specification is 2 0.5% of reading
22SOpV. AD538 prices start at $17.00 in 100s (A-grade in an
18-pin DfP).
In many cases, the internally trimmed performance of the AD538
will be more than adequate for the application; but for the best
possible dynamic range and accuracy, some form of external trimming should be used. Offset trims have already been discussed, in
relation to Figures. Scale-factor trimscan be implemented by adding variable resistance in series with (voltage) inputs Z or Y, to reducegain, or X, to increasegain. This is yet another demonstration
of the flexibility of the AD538. Figure 8 shows a way of implementingscale-factor trims for positive and negative roots.
w'iiin
Y.
I
IDJIIhI
Figure 7. Connection for high-accuracy log ratio.
In order to minimize any influence from the V, input, it should be
returned to a small negative voltage. If a 1.2-volt AD589 is used
to obtain regulated negative voltage ( - 1.2 V) for offset adiustment (as in the high-accuracy multiplication circuit of Figure 3),
V, can be tied back to - 1.2 volts.
Powers, Including Roots
Often it is necessary to raise a quantity, which may be a ratio, to
a power, which may be positive or negative, greater or less than
unity, and either an integer or a mixed fraction. 7he ADS38 offers
a convenient way to achieve any positive or negative power, from
115 to5, with the addition of one or two external resistors.
For powers less than 1 (i.e., roots), a simple voltage divider attenuates the log-ratio output in the connection between B and C, as
shown in Figure 8. For powers greater than I , the gain of the subtractor must instead be increased, by connecring resistance (RAin
the table of Figure 8) between points A and D to attenuate the subtractor's feedback. For negative powers, inputs Z and X are interchanged (but this works only if the Y input is not active-for convenience, it may be set at 1 .O volts). The resistances listed are the
nominal resistance values specified for standard 1% metal-film
resistors.
POWERS > 1
W W R S rl (ROOTS)
14811
97.611
64.911
48.711
Figure 8. Connections for raising to powers less than 1.0
(roots), with offset and gain trims; tables of resistancevalues
for selected powers and roots.
REFERENCES
Counts, Lew, Charles Kitchin, and Stcvc Sherman, "One-Chip
'Slide Rule' Works with Logs, Antilogs for Real-Time Processing,"
Electronic Design(2 May 1985)
Counts, Lew, and Fred Pouliot, "Versatile New Module: Y[Z/XIM
at Low Cost," Analog Dialogue 6-2 (1972).
Sheingold, Daniel H., ed., Nonlinear Circuits Handbook. Norwood: Analog Devices, 1974 ($5.95).
a
Analog Dialogue 19-1 1985