Download Invite #4 (45minutes), Oral #46 (20+5 minutes)

ISMVL2016 Program (Tentative as of 20160316)
Invite
#4
(45minutes),
Oral
#46
(20+5 minutes)
May 17, Tuesday
9:00 ISMVL Registration
10:00 Post-binary ULSI Workshop
18:00 Reception
May 18, Wednesday
9:00 Opening
9:15 Invited Address I Prof. Yamanoi
Session 1B: Synthesis of Reversible
Circuits (4)
10:20 Session 1A: Circuits I (4)
12:00 Lunch (Symposium Committee)
13:20 Invited Address II Prof. Haseyama
14:20 Session 2A: Circuits II (3)
15:50
Session 3A: Index generation
function (4)
Session 2B: Clone (3)
Session 3B: Algebra I(4)
May 19, Thursday
9:15 Invited Address III Prof. Minato
10:20
Session 4A: From Reversible to
Session 4B: Algebra II (3)
Quantum Circuits (3)
11:40 Excursion with lunch
19:00 Banquet
May 20, Friday
9:15 Invited Address IV
10:15
Prof. Wai Tung Ng
Session 5A: Intelligent medical
Session 5B: Logic I (5)
and welfare engineering(5)
12:20 Lunch (Executive Committee)
13:40
Session 6A: Quantum Gates and
Session 6B: Logic II(4)
Quantum States (4)
15:30 Plenary Session
16:30 Closing
May 18
Invited Address I
9:15-10:00
Elucidation of Brain Activities by Electroencephalograms and its Application to Brain Computer
Interface
Takahiro Yamanoi
[Session 1A: Circuits I]
10:20-12:00
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating
Scheme Daisuke Suzuki, Takahiro Hanyu
CNTFET-RFB: An Error Correction Implementation For Multi-Valued CNTFET Logic
Gopalakrishnan Sundararajan, Chris Winstead
Ternary versus Binary Multiplication with Current-Mode CNTFET-based K-Valued Converters
Mona Moradi, Reza Faghih Mirzaee, Keivan Navi
Design of Ratioless Ternary Inverter using Graphene Barristor
Sunwoo Heo, Jinwoo Noh, Yun Ji Kim, So-Young Kim, Abdul Karim Khan, Byoung Hun Lee
[Session 1B: Synthesis of Reversible Circuits]
10:20-12:00
Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits
ZAID, SALEEM ALI, AL-WARID
An Improved Factorization Approach to Reversible Circuit Synthesis Based on EXORs of Products
of EXORs
Linh Tran, Addison Gronquist, Marek Perkowski, John Caughman
Fault Detection in Parity Preserving Reversible Circuits
Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler
Notes on Majority Boolean Algebra
Anupam Chattopadhyay, Luca Amaru, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De
Micheli
Invited Address II 13:20-14:05
Realization of Associative Image Search: Development of Image Retrieval Platform for Enhancing
Serendipity
Miki Haseyama
[Session 2A: Circuits II] 14:20-15:35
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope
Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya
Ogawa
Double-Rate Equalization Using Tomlinson-Harashima Precoding for Multi-Valued Data
Transmission
Yosuke Iijima, Yasushi Yuminaka
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and
Efficient Intra-Chip Data Transmission
Naoto Sugaya, Masanori Natsui, Takahiro Hanyu
[Session 2B: Clone] 14:20-15:35
Monomial Clones: Local Results and Global Properties
Hajime Machida, Jovanka Pantovic
Centralizing monoids on a three-element set related to binary idempotent functions
Hajime Machida, Ivo G. Rosenberg
Minimal Weighted Clones with Boolean Support
Peter G. Jeavons, Andrius Vaicenavicius, Stanislav Zivny
[Session 3A: Index generation functions] 15:50-17:30
An Efficient Heuristic for Linear Decomposition of Index Generation Functions
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Index Generation Functions based on Linear and Polynomial Transformations
Helena Astola, Radomir Stankovic, Jaakko Astola
An Algebraic Approach to Reducing the Number of Variables of Incompletely Defined Discrete
Functions
Jaakko Astola, Pekka Astola, Radomir Stankovic, Ioan Tabus
A Realization of Index Generation Functions Using Multiple IGUs
Tsutomu Sasao
[Session 3B: Algebra I]
15:50-17:30
Set Representation of Partial Dynamic De Morgan algebras
Ivan Chajda, Jan Paseka
Tolerance Distances on Minimal Coverings
Catalin Zara, Dan A. Simovici
Paraconsistent Double Negation That Can Simulate Classical Negation
Norihiro Kamide
Cut-Free Systems for Restricted Bi-Intuitionistic Logic and Its Connexive Extension
Norihiro Kamide
May 19
Invited Address III 9:15-10:00
Power of Enumeration --- BDD/ZDD-Based Techniques for Discrete Structure Manipulation
Shin-ichi Minato
[Session 4A: From Reversible to Quantum Circuits] 10:20-11:35
Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits
Md Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Technology Mapping of Reversible Circuits to Clifford+$T$ Quantum Circuits
Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation
Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf
Drechsler, Hafizur Rahaman
[Session 4B: Algebra II] 10:20-11:35
Some properties of generalized state operators on residuated lattices
Michiro Kondo, Mayuka F. Kawaguchi
Simple characterizations of perfect residuated lattices
Michiro Kondo
Endpoints of associated intervals
Boris A.Romov
May 20
Invited Address IV 9:15-10:00
SPRUCE, an Embedded Compact Stack Machine for IGBT Power Modules
Wai Tung Ng
[Session 5A: Intelligent medical and welfare engineering] 10:15-12:20
Gray-Scale Morphology Based Image Segmentation and Character Extraction Using SVM
Jianjun Chen, Noboru Takagi
A Low-Voltage and Low-Power CMOS Temperature Sensor Circuit with Digital Output for
Wireless Healthcare Monitoring System
Agung Setiabudi, Ryota Sakamoto, Hiroki Tamura, Koichi Tanno
Dependency Analysis of BMI in Health Checkup Blood Data
Mizuki Higuchi, Kenichi Sorachi, Yutaka Hata
Novel Instrumentation Amplifier Architectures Insensitive to Resistor Mismatches and Offset
Voltage for Biological Signal Processing
Zainul Abidin, Koichi Tanno, Shota Mago, Hiroki Tamura
Study Support System of Character Drawing considering Feeling Evaluation
Ryuichi MURAKAMI, Noriaki MURANAKA
[Session 5B: Logic I] 10:15-12:20
Gibbs Characterization of Binary and Ternary Bent Functions
Radomir S. Stankovic, Milena Stankovic, Jaakko T. Astola, Claudio Moraga
On Constructing Secure and Hardware-Efficient Invertible Mappings
Elena Dubrova
Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors
Rei Ueno, Yukihiro Sugawara, Naofumi Homma, Takafumi Aoki
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation
Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
The Pascal triangle (1654), the Reed-Muller-Fourier Transform (1992), and the Discrete Pascal
Transform (2005)
Claudio Moraga, Radomir Stankovic, Milena Stankovic
[Session 6A: Quantum Gates and Quantum States] 13:40-15:20
New Two-Qubit Gate Library with Entanglement
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
Quantum p-valued Toffoli and Deutsch gates with conjunctive or disjunctive mixed polarity control
Claudio Moraga
Logic Synthesis for Quantum State Generation
Philipp Niemann, Rhitam Datta, Robert Wille
Quantum algorithmic complexity of three-qubit pure states
Martin Lukac, Aikaterini Mandilara
[Session 6B: Logic II] 13:40-15:20
A Study on Realizing Awareness Using 3VL-MLP
Quangfu Zhao
Multi-Valued Problem Solvers
Bernd Steinbach, Stefan Heinrich, Christian Posthoff
A Bit-Vector Approach to Satisfiability Testing in Finitely-Valued Logics
Joan Ramon Soler, Felip Manyà
On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults
Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya, Tsutomu Sasao