Download DC/DC converter

PSDM
POWER STAGE DRIVER MODULE
PSDM-0DN1-5040
POWER STAGE DRIVER MODULE:
DC/DC CONVERTER FOR
IGBT/MOSFET GATE DRIVER
Technical Data
Features
Applications
- Electrical isolation of 3500 VAC
- Switching frequency 500 kHz
- Output voltage monitoring
- Overcurrent and short circuit protection
- Power MOSFETs
and IGBTs driver
Description
The PSDM-DC/DC module is a power supply converter designed to provide a galvanic
isolated, regulated and monitored power to IGBTs and MOSFETs drivers. The Module
requires an Input voltage of 12VDC + 10% and has dual outputs with 15V resp. -4V with a
maximum current of 140mA. This DC/DC module has a unique diagnostic output allowing the
user to monitor the converter output voltage, therefore avoiding damages in the power
stages due to under voltages.
Block Diagram
1
VDC
2
GND
3
VSM
LOGIC
CIRCUIT
LOGIC
CIRCUIT
OSCILLATOR
VCS1
4
VCS2
6
SGND
5
electrical isolation
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PSDM-0DN1-5040
ABSOLUTE MAXIMUM RATINGS
Stresses in excess of the absolute maximum ratings can cause permanent damage to the
device.
Parameter
Test Condition
Symbol
Max
Unit
VDC
13.2
V
VCS1 to VCS2
20
V
Viso
3500
VAC
Tstg
-55 to +125
°C
no derating
Tamb
Tamb
-5 to +85
-5 to +60
°C
°C
total for both output
Po
2.6
W
Supply Voltage for
driver
DC/DC Output
Voltage between VCS1
to VCS2
Test Voltage
50Hz/1s input to outputs
Storage Temperature
Range
Ambient Temperature
Range
Output Power
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PSDM-0DN1-5040
Electrical Characteristics
(VDC=12V and TA=25°C)
DC/DC CONVERTER
Parameter
Test Condition
Symbol
Min
Nominal Power Supply
to GND
VDC
11.8
Typ
Max
Unit
13.2
V
320
mA
Supply Current
IDC
Output Power
Po
2.6
W
Output Voltage 1
to SGND
VCS1
15
V
Output Voltage 2
to SGND
VCS2
-4
V
Output Current 1 and 2
Output Ripple
VDC=15V,
Io=120mA
Io
140
mA
Vrippk-pk
240
mV
η
0.75
%
fSW
500
kHz
Isolation Capacitance
Ciso
12
Isolation Resistance
Riso
Turn-on threshold
Vtr
14.8
VDC
Hysteresis on-off
Output Switching
Monitoring
Vh
1.1
VDC
Efficiency
Switching Frequency
Isolation Voltage
Short circuit protection
VDC=15V,
Io=120mA
VSM
50Hz/1s input to
outputs
VCS1 and VCS2,
VCS1 and SGND,
VCS2 and SGND
Viso
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15
10
0
pF
MΩ
VDC
VDC
3500
VAC
limited 1 sec. maximum
ver 1.0
revision 30.nov.2004
PSDM-0DN1-5040
Mechanical Dimensions
All the measures are in mm.
Distances between pins are 2.54mm.
1.
Mechanical dimensions
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PSDM-0DN1-5040
Pin Designation
PIN N°
SYMBOL
I/O
DESCRIPTION
1
2
3
4
5
6
VDC
GND
VSM
VCS1
SGND
VCS2
input
input
output
output
output
output
power supply +10v…+15V for the DC/DC converter
power supply GND
monitoring DC/DC converter
output power supply DC/DC converter +15V
output power supply DC/DC converter GND
output power supply DC/DC converter -4V
Pin Description
PIN VDC
A stabilized voltage supply between 10V and 15V with respect to GND.
PIN GND
GND is connected to the ground of the electronic power supply.
PIN VSM
This output collects data about DC/DC converter. The voltage across VSM increases, when
more current is needed at the output stage. When VSM achieve the value of the power supply
of the DC/DC converter means that the DC/DC converter has achieved the maximum
transferring power.
PIN VCS1
VCS1 is the isolated output positive power supply for driver logic.
PIN SGND
SGND is the ground isolated from DC/DC converter.
PIN VCS2
VCS2 is the isolated output negative power supply for driver logic.
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PSDM-0DN1-5040
Derating
160
120
N
VI
0.
=1
100
8V
80
N
VI
2.
V
=1
.2
13
N=
VI
60
0V
OUT PUT CURRENT MAX (mA)
140
40
20
0
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
AMBIENT TEMPERATURE (°C)
2.
Derating
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PSDM-0DN1-5040
Application examples
General application single phase
DC BUS +
PSDM-0DN15040
GATE DRIVER
µPC
4
LOAD
PSDM-0DN15040
N
GATE DRIVER
DC BUS -
Application in high current power supply
DC BUS +
PSDM-0DN15040
PSDM-0DN15040
µPC
GATE DRIVER
GATE DRIVER
+
µPC
PSDM-0DN15040
PSDM-0DN15040
µPC
GATE DRIVER
GATE DRIVER
DC BUS -
Application in motor AC inverter
DC BUS +
PSDM-0DN15040
PSDM-0DN15040
GATE DRIVER
µPC
GATE DRIVER
PSDM-0DN15040
µPC
GATE DRIVER
U
V
µPC
W
PSDM-0DN15040
GATE DRIVER
PSDM-0DN15040
µPC
GATE DRIVER
M
PSDM-0DN15040
µPC
GATE DRIVER
DC BUS -
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PSDM-0DO2-5040
POWER STAGE DRIVER MODULE:
SINGLE ISOLATED
IGBT/MOSFET GATE DRIVER
Technical Data
Features
Applications
- Usable for IGBTs and power MOSFETs
- Very smart and suitable case
- Electrical isolation of 3500 VAC
- Switching frequency up to 100 kHz
- Duty cycle from 0% to 100%
- DC/DC converter included
- Output voltage monitoring
- Overcurrent and short circuit protection
- Inverters
- Motor drive
- Converters
- SMPS
- DC/DC converter
Description
The PSDM (Power Stage Driver Module) has been developed for driving in a safe, reliable
and easy way power IGBT or MOSFET transistors. The modules have internal circuitry to
switch off and therefore to protect the power transistor in cases of fault at the output power
stage, like shorts or reduced voltage driver.
The PSDM has an isolated DC/DC converter with 2.4W output power implemented in a
plastic case to supply the drive circuit. The data is transferred by an optocoupler.
Block Diagram
1
VDC
2
GND
3
VSM
LOGIC
CIRCUIT
LOGIC
CIRCUIT
OSCILLATOR
VCS1
4
VCS2
6
SGND
5
VCS1
15
14
VDD
GND
13
VIN
12
FLT
LOGIC
CIRCUIT
GATE
DRIVER
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
electrical isolation
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PSDM-0DO2-5040
ABSOLUTE MAXIMUM RATINGS
Stresses in excess of the absolute maximum ratings can cause permanent damage to the
device.
Symbol
Max
Unit
Supply voltage for
logic interface
Parameter
VDD
5.5
V
Power supply voltage
for DC/DC converter
VDC
15.0
V
Input logic voltage
VIN
5.5
VDC
Active fault voltage
VFLT
80
V
Active fault current
IFLT
50
mA
Input voltage to driver
between VCS1 to VES
VCS1 to VES
20
V
Isolated power supply
VES
-5
V
Viso
3500
VAC
Storage temperature
range
Tstg
-55 to +125
°C
Ambient temperature
range
Tamb
-5 to +80
°C
Po
2.4
W
dv/dt
100
V/ns
Test voltage
Output power
Test Condition
50Hz/1s input to outputs
total for both output
dv/dt
Norm
conform to EN 61248-5
and EN 61558-1
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PSDM-0DO2-5040
Electrical Characteristics
(VDC=12V and TA=25°C)
DC/DC CONVERTER
Parameter
Test Condition
Symbol
Min
Nominal Power Supply
to GND
VDC
10.0
Typ
Max
Unit
15.0
V
320
mA
Supply Current
IDC
Output Power
Po
2.4
W
Output Voltage 1
to SGND
VCS1
15
V
Output Voltage 2
to SGND
VCS2
-4
V
Output Current 1 and 2
Output Ripple
VDC=15V,
Io=120mA
Io
120
mA
Vrippk-pk
240
mV
η
0.75
%
Switching Frequency
fSW
500
kHz
Isolation Capacitance
Ciso
12
Isolation Resistance
Riso
Turn-on threshold
Vtr
14.8
VDC
Hysteresis on-off
Output Switching
Monitoring
Vh
1.1
VDC
Efficiency
VDC=15V,
Isolation Voltage
Short circuit protection
VSM
50Hz/1s input to
outputs
VCS1 and VCS2,
VCS1 and SGND,
VCS2 and SGND
Viso
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15
10
0
pF
MΩ
VDC
VDC
3500
VAC
limited 1 sec. maximum
ver 1.0
revision 30.nov.2004
PSDM-0DO2-5040
Electrical Characteristics
(VDD=5V, TA=25°C, VDC=12V, VES=VCS2=-4V)
IGBT DRIVER
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
VDD
VCS1
VES
4.5
5.0
15
-4
5.5
Nominal Power Supply
to GND
to KGND
to KGND
V
V
V
IDD
25
mA
IDDP
50
mA
IO
IO
1
2
A
A
5.5
0.5
VDC
Supply Current
Peak Supply Current
Gate driver output
Source current
Sink current
t=1.0ms,
duty-cycle=50%
Input Logic Voltage
VIN (high)
VIN (low)
VIN=5V, VDD=5V,
VCS1=15V,
VCS2=-4V
tpLH
tpHL
VCS1=15V,VCS2=-4V
VCS1=15V,VCS2=GND
VINsw
VINsw
Delay Time Input To
Output
Switching Frequency DC
5.0
0.2
300
330
kHz
kHz
100
%
HVDC
600
V
Viso
3500
VAC
0
DC link voltage input
50Hz/1s input to
outputs
ns
ns
100
50
Duty-cycle
Isolation Voltage
4.5
0
Active fault voltage
VFLT
5
80
VDC
Active fault current
Undervoltage lockout
start
Undervoltage lockout
disable
Current sense
overcurrent threshold
voltage
Current sense short
circuit threshold voltage
IFLT
10
50
mA
Desaturation protection
VISOC
11.3
12
12.6
V
VISOC
10.4
11
11.7
V
Vpin11 > 7 V
VISOC
50
65
80
mV
Vpin11 > 7 V
VISSC
100
130
160
mV
Vpin10 > 100 mV
DPRth
6.0
6.5
7.0
V
Undervoltage Lockout
PSDM-0DO2-5040 is equipped of a protection from insufficient gate voltage. Under certain
value the IGBT may operate in the regions which quickly overheat. This is why that below
10 V the device will disable the gate output.
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PSDM-0DO2-5040
Mechanical Dimensions
All the measures are in mm.
Distances between pins are 2.54mm.
3.
Mechanical dimensions
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PSDM-0DO2-5040
Pin Designation
PIN N°
SYMBOL
I/O
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDC
GND
VSM
VCS1
SGND
VCS2
VES
KGND
VO
DPR
ISEN
FLT
VIN
GND
VDD
input
input
output
output
output
output
input
input
output
input
input
output
input
input
input
power supply +10v…+15V for the DC/DC converter
power supply GND
monitoring DC/DC converter
output power supply DC/DC converter +15V
output power supply DC/DC converter GND
output power supply DC/DC converter -4V
external or isolated power supply
isolated power supply GND ( to connect to SGND)
gate terminal
desaturation protection
current sense
active fault output of the driver
input 0-5V, PWM
power supply GND
power supply +5V for the logic interface
Pin Description
PIN VDC
A stabilized voltage supply between 10V and 15V with respect to GND.
PIN GND
GND is connected to the ground of the electronic power supply.
PIN VSM
This output collects data about DC/DC converter. The voltage across VSM increases, when
more current is needed at the output stage. When VSM achieve the value of the power supply
of the DC/DC converter means that the DC/DC converter has achieved the maximum
transferring power.
PIN VCS1
VCS1 is the isolated output positive power supply for driver logic.
PIN SGND
SGND is the ground isolated from DC/DC converter.
PIN VCS2
VCS2 is the isolated output negative power supply for driver logic.
PIN VES
VES is an external power supply for driver logic. Normally VES should be connected to VCS2.
This voltage is used to switch off the MOSFET/IGBT connected to the module.
PIN KGND
KGND is the isolated Kelvin ground that should be connected to SGND.
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PSDM-0DO2-5040
PIN VO
The output VO is the signal output for the IGBT gate drive.
In order to allow the switching speed to be set independently during the turn-on and the
turn-off, two gate resistors and a diode must be used ( for example Rg1 = 22 Ω and
Rg2 = 100 Ω ).
D2
VO
Rg1
9
Rg2
PSDM
KGND 8
0V
0V
2.
Gate driver
PIN ISEN
The input ISEN is used to check the current across the Risen in order to ensure protection from
short circuit and overload of the IGBT that is to sense the emitter current using a current
shunt (Risen value is few mΩ). To remove any high frequency noise is used to put an RC filter
next to Risen using a resistor Rf and a capacitor Cf.
When an overcurrent appears ( VISOC > 65 mV) on the Risen an internal circuit guarantee the
switch off of the IGBT without feedback any signal to the FLT output. The signal error will be
reset when will be another pulse at the signal VIN.
The inductance will be very low when there is a short circuit in the output ( VISSC > 130 mV).
The short circuit signal, measured with the sense resistance Risen, is transferred by an
internal optocoupler and appears at the output pin FLT. When a short circuit is detected, the
IGBT will be turned–off until at the next pulse at the signal VIN.
PSDM
from DPR
to FLT
ISEN
disable
VO
11
Rf
Cf
65mV
Risen
130mV
KGND
3.
8
0V
Current sense Isen
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PSDM-0DO2-5040
PIN DPR
This terminal is used to measure the voltage drop across the turned-on power transistor in
order to ensure protection from short circuit and overload of the IGBT. This involves
monitoring the collector voltage and turning off the device if this voltage rises above a certain
limit. The best method for detecting desaturation is the use of an external fast or super-fast
high voltage clamp diode D1 ( for example 1N4937) and an internal comparator. The PSDM
has a desaturation protection which senses the collector voltage and provides an output
indicating when the device is not fully saturated. When the IGBT is “on” and saturated, D1
will hold down the voltage on the DPR. When the IGBT pulls out of saturation or is not “on”,
the internal current source (270 µA) will pull up the input and trip the comparator. The
comparator threshold is typically 6.5 V (DPRth). The resistor RRV is used to protect the PSDM
from reverse voltage transients and it shouldn’t be bigger than 1kΩ. The error will be
transferred by means of an internal optocoupler to the output pin FLT.
from ISEN
DPR
VCC
D1
Rrv
10
to FLT
270uA
disable
VO
Cblank
6.5V
KGND
8
0V
VIN
PSDM
4.
Desaturation protection Dpr
PIN FLT
The PSDM has an active high fault output. The fault output is internally interfaced to an
optocoupler. The LED drive provides a 10-20mA when on, and provides a low impedance
when off. The circuit integrated is shown below.
VFLT
RFLT
12
FLT
PSDM
14
GND
VCS2
5.
Output fault
FLT pin is enable only if will be used together with DPR or ISEN signal. (see overview 3 and 4).
The voltage VFLT can be pulled from 5V to 15V via a pull-up resistor. Allowed current is
10mA. The transistor in the optocoupler is pulled to GND when an error has been detected.
Therefore if no errors are detected the transistor is open.
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PSDM-0DO2-5040
In the following figures are represented active fault signal versus current sense and versus
desaturation protection. When the voltage through the shunt (RISEN) is more than VISSC we will
find a logic low signal. In the next side if the voltage measured by DPR is more than 6.5V, we
will find signal logic low at the pin FLT active fault.
16
FLT pin 12, A CTIVE FAULT OUTPUT, (V)
FLT pin 12, A CTIVE FAULT OUTPUT, (V)
16
14
12
10
8
6
4
2
14
12
10
8
6
4
2
0
0
90
100
110
120
130
140
150
160
6.1
170
6.
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
DPR pin 11, DESATURATION PROTECTION, (V)
ISEN pin 10, CURRENT SENSE, (mV)
FLT versus CURRENT SENSE
7.
FLT versus DESATURATION
PROTECTION
VDC = 15V, VDD = 5V, VIN = HIGH, TA = 25 °C .
In figure 6 is represented the turn off of the gate terminal when voltage at the pin 10 ISEN
exceed 130mV and having DPR enable (VDPR > 6.5 V). In the other figure the turned off of
the gate terminal appears when the voltage is more than 6.5 V and having ISEN enable (VISEN
> 130 mV).
PIN VIN
The input has a Schmitt trigger characteristic. HIGH level switches the power semiconductor
on; LOW level means a switch off state.
PIN VDD
A stabilized voltage supply between 4.5V and 5.5V with respect to GND.
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PSDM-0DO2-5040
OVERVIEW
Overview 1
VCS1
4
VCS2
6
SGND
5
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
Basic application connecting SGND with , ISEN,
DPR and KGND together.
ISEN and DPR should be connected together to
ground and, in this case you have no
protection of the circuit. If you need only a
single supply, already connected internally,
VES should be connected to the SGND. This
means a decreasing of the Switching
Frequency DC from 100kHz to 50kHz.
Put separate resistances between VO and
IGBT if necessary to optimize the turn-on and
the turn-off of the semiconductor.
15V
-4V
0V
Rg1
D2
Rg2
0V
8.
Basic Application
5V
VIN
t
VO
t
0V
15 V
0V
tpLH
tpHL
9.
Signal curves for the basic application
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PSDM-0DO2-5040
Overview 2
VCS1
4
VCS2
6
SGND
5
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
Dual supply basic application connecting
SGND with ISEN and DPR.
If you want connect a dual supply, connect
VCS2 to VES. Connection the DPR and ISEN to
the SGND means disable the protection
features of the PSDM. As shown in the first
overview the resistances Rg1 and Rg2 should
be choose to optimize turn-on and turn-off of
the semiconductor.
15V
-4V
0V
Rg1
D2
Rg2
0V
10. Dual supply basic application
5V
VIN
t
VO
t
0V
15 V
0V
-4 V
tpLH
tpHL
11. Signal curves for the dual supply basic application
Figure 11 show the delay between input and output signal. Using dual supply we will
have a square wave from VES and VCS1.
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PSDM-0DO2-5040
Overview 3
VCS1
4
VCS2
6
SGND
5
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
Desaturation application connecting VCS2 to
VES to have a dual supply for the gate. Enable
the desaturation protection pin connecting
VCS1 (the main supply) to ISEN. Moreover put a
high voltage diode in series to a resistor
between DPR and the IGBT collector as
illustrated in the picture from the side.
The blank capacitor should be connected from
DPR to VES.
15V
-4V
0V
D1
Rrv
Cblank
Rg1
D2
Rg2
0V
12. Desaturation application
VIN
t
VO
t
65mV
DPR
t
FLT
t
tpLH
tpHL
tCblank
0 < ts < tCblank
13. Signal curves for the desaturation application
As is shown in figure 13 when an error appears, that is when the voltage at pin DPR is
greater than 6.5V, the voltage across the gate of the transistor is kept at VES. This
error is transferred at the pin FLT with a certain delay due to Cblank.
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PSDM-0DO2-5040
Overview 4
VCS1
4
VCS2
6
SGND
5
Current sense application connecting VCS2 to
the VES to have a dual supply.
Using ISEN connector you should put a resistor
RIsen (shunt) between ISEN to KGND. The two
connections, ISEN and KGND should be routed
as a differential pair directly to pin 8 for KGND
and pin 10 for ISEN. To remove any high
frequency noise is used to put an RC filter as
shown in the figure on the left. Capacitor
between DPR and VCS2 is needed.
15V
-4V
0V
Rg1
D2
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
Rg2
Cblank
Rf
Cf
Risen
0V
14. Current sense application
VIN
t
VO
t
130mV
65mV
ISEN
t
FLT
t
tpLH
tpHL
tCblank
0 < ts < tCblank
15. Signal curves for the current sense application
Figure 15 show two types of error. The first is when through the R sense flow more
than 65mV. The gate output VO is disabling until another pulse VIN appears. This is
due to an overcurrent. No signal is transferred to the fault pin FLT.
When a short circuit appear, across RISEN will flow more than 130mV. The output VO
is kept at VES and an error will be transferred to the fault pin FLT. At the next pulse of
VIN the error will be reset.
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PSDM-0DO2-5040
Layout and wiring
Drivers should as a rule be placed as close as possible to the power semiconductors
so that the leads from the driver to the transistors are as short as possible. Lead too
length must be avoided. When the power semiconductors are connected by stranded
wires, it is recommended always to twist the associated leads.
DPR 10
VO
9
PSDM
ISEN 11
twisted wires
KGND
8
0V
16. Twisted wires
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PSDM-0DO2-5040
Application examples
General application single phase
DC BUS +
PSDM-0DO25040
L
LOAD
µPC
N
PSDM-0DO25040
DC BUS -
Application in high current power supply
DC BUS +
µPC
PSDM-0DO25040
PSDM-0DO25040
+
µPC
µPC
PSDM-0DO25040
PSDM-0DO25040
DC BUS -
Application in motor AC inverter
DC BUS +
PSDM-0DO25040
µPC
PSDM-0DO25040
µPC
PSDM-0DO25040
U
V
µPC
W
PSDM-0DO25040
µPC
PSDM-0DO25040
µPC
M
PSDM-0DO25040
DC BUS -
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PSDM-0DT2-5020
POWER STAGE DRIVER MODULE:
SINGLE ISOLATED
IGBT/MOSFET GATE DRIVER
Technical Data
Features
Applications
- Usable for IGBTs and power MOSFETs
- Very smart and suitable case
- Electrical isolation of 3500 VAC
- Switching frequency up to 100 kHz
- Duty cycle from 0% to 100%
- DC/DC converter included
- Output voltage monitoring
- Overcurrent and short circuit protection
- Symmetrical propagation delay
- No ageing effects
- Low jitter
- High speed
- Inverters
- Motor drive
- Converters
- SMPS
- DC/DC converter
Description
The PSDM (Power Stage Driver Module) has been developed for driving in a safe, reliable
and easy way power IGBT or MOSFET transistors. The modules have internal circuitry to
switch off and therefore to protect the power transistor in cases of fault at the output power
stage, like shorts or reduced voltage driver.
The PSDM has an isolated DC/DC converter with 2.4W output power implemented in a
plastic case to supply the drive circuit. The data is transferred by a pulse transformer.
Block Diagram
1
VDC
2
GND
3
VSM
LOGIC
CIRCUIT
LOGIC
CIRCUIT
OSCILLATOR
VCS1
4
VCS2
6
SGND
5
VES
7
KGND
8
VCS1
15
14
13
12
VDD
GND
LOGIC
CIRCUIT
GATE
DRIVER
VIN
FLT
VO
9
DPR
10
ISEN
11
electrical isolation
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PSDM-0DT2-5020
ABSOLUTE MAXIMUM RATINGS
Stresses in excess of the absolute maximum ratings can cause permanent damage to the
device.
Symbol
Max
Unit
Supply voltage for
logic interface
Parameter
Test Condition
VDD
5.5
V
Power supply voltage
for DC/DC converter
VDC
15.0
V
Input logic voltage
VIN
5.5
VDC
Active fault voltage
VFLT
80
V
Active fault current
IFLT
50
mA
Input voltage to driver
between VCS1 to VES
VCS1 to VES
20
V
VES
-5
V
Viso
3500
VAC
Storage temperature
range
Tstg
-55 to +125
°C
Ambient temperature
range
Tamb
-5 to +80
°C
Po
2.4
W
dv/dt
100
V/ns
Isolated power supply
Test voltage
Output power
50Hz/1s input to outputs
total for both output
dv/dt
Norm
conform to EN 61248-5
and EN 61558-1
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PSDM-0DT2-5020
Electrical Characteristics
(VDC=12V and TA=25°C)
DC/DC CONVERTER
Parameter
Test Condition
Symbol
Min
Nominal Power Supply
to GND
VDC
10.0
Typ
Max
Unit
15.0
V
320
mA
Supply Current
IDC
Output Power
Po
2.4
W
Output Voltage 1
to SGND
VCS1
15
V
Output Voltage 2
to SGND
VCS2
-4
V
Output Current 1 and 2
Output Ripple
VDC=15V,
Io=120mA
Io
120
mA
Vrippk-pk
240
mV
η
0.75
%
fSW
500
kHz
Isolation Capacitance
Ciso
12
Isolation Resistance
Riso
Turn-on threshold
Vtr
14.8
VDC
Hysteresis on-off
Output Switching
Monitoring
Vh
1.1
VDC
Efficiency
Switching Frequency
Isolation Voltage
Short circuit protection
VDC=15V,
Io=120mA
VSM
50Hz/1s input to
outputs
VCS1 and VCS2,
VCS1 and SGND,
VCS2 and SGND
Viso
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25 / 37
15
10
0
pF
MΩ
VDC
VDC
3500
VAC
limited 1 sec. maximum
ver 1.0
revision 30.nov.2004
PSDM-0DT2-5020
Electrical Characteristics
(VDD=5V, TA=25°C, VDC=12V, VES=VCS2=-4V)
IGBT DRIVER
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
VDD
VCS1
VES
4.5
5.0
15
-4
5.5
Nominal Power Supply
to GND
to KGND
to KGND
V
V
V
IDD
25
mA
IDDP
50
mA
IO
IO
1
2
A
A
5.5
0.5
VDC
Supply Current
Peak Supply Current
Gate driver output
Source current
Sink current
t=1.0ms,
duty-cycle=50%
Input Logic Voltage
VIN (high)
VIN (low)
VIN=5V, VDD=5V,
VCS1=15V,
VCS2=-4V
tpLH
tpHL
VCS1=15V,VCS2=-4V
VCS1=15V,VCS2=GND
VINsw
VINsw
Delay Time Input To
Output
Switching Frequency DC
5.0
0.2
180
200
kHz
kHz
100
%
HVDC
600
V
Viso
3500
VAC
0
DC link voltage input
50Hz/1s input to
outputs
ns
ns
100
50
Duty-cycle
Isolation Voltage
4.5
0
Active fault voltage
VFLT
5
80
VDC
Active fault current
Undervoltage lockout
start
Undervoltage lockout
disable
Current sense
overcurrent threshold
voltage
Current sense short
circuit threshold voltage
IFLT
10
50
mA
Desaturation protection
VISOC
11.3
12
12.6
V
VISOC
10.4
11
11.7
V
Vpin11 > 7 V
VISOC
50
65
80
mV
Vpin11 > 7 V
VISSC
100
130
160
mV
Vpin10 > 100 mV
DPRth
6.0
6.5
7.0
V
Undervoltage Lockout
PSDM-0DT2-5020 is equipped of a protection from insufficient gate voltage. Under certain
value the IGBT may operate in the region which quickly overheats. This is why that below
10 V the device will disable the gate output.
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PSDM-0DT2-5020
Mechanical Dimensions
All the measures are in mm.
Distances between pins are 2.54mm.
4.
Mechanical dimensions
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PSDM-0DT2-5020
Pin Designation
PIN N°
SYMBOL
I/O
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDC
GND
VSM
VCS1
SGND
VCS2
VES
KGND
VO
DPR
ISEN
FLT
VIN
GND
VDD
input
input
output
output
output
output
input
input
output
input
input
output
input
input
input
power supply +10v…+15V for the DC/DC converter
power supply GND
monitoring DC/DC converter
output power supply DC/DC converter +15V
output power supply DC/DC converter GND
output power supply DC/DC converter -4V
external or isolated power supply
isolated power supply GND ( to connect to SGND)
gate terminal
desaturation protection
current sense
active fault output of the driver
input 0-5V, PWM
power supply GND
power supply +5V for the logic interface
Pin Description
PIN VDC
A stabilized voltage supply between 10V and 15V with respect to GND.
PIN GND
GND is connected to the ground of the electronic power supply.
PIN VSM
This output collects data about DC/DC converter. The voltage across VSM increases, when
more current is needed at the output stage. When VSM achieve the value of the power supply
of the DC/DC converter means that the DC/DC converter has achieved the maximum
transferring power.
PIN VCS1
VCS1 is the isolated output positive power supply for driver logic.
PIN SGND
SGND is the ground isolated from DC/DC converter.
PIN VCS2
VCS2 is the isolated output negative power supply for driver logic.
PIN VES
VES is an external power supply for driver logic. Normally VES should be connected to VCS2.
This voltage is used to switch off the MOSFET/IGBT connected to the module.
PIN KGND
KGND is the isolated Kelvin ground that should be connected to SGND.
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PSDM-0DT2-5020
PIN VO
The output VO is the signal output for the IGBT gate drive.
In order to allow the switching speed to be set independently during the turn-on and the
turn-off, two gate resistors and a diode must be used ( for example Rg1 = 22 Ω and Rg2 = 100
Ω ).
D2
VO
Rg1
9
Rg2
PSDM
KGND 8
0V
0V
3.
Gate driver
PIN ISEN
The input ISEN is used to check the current across the Risen in order to ensure protection from
short circuit and overload of the IGBT that is to sense the emitter current using a current
shunt (Risen value is few mΩ). To remove any high frequency noise is used to put an RC filter
next to Risen using a resistor Rf and a capacitor Cf.
When an overcurrent appears ( VISOC > 65 mV) on the Risen an internal circuit guarantee the
switch off of the IGBT without feedback any signal to the FLT output. The signal error will be
reset when will be another pulse at the signal VIN.
The inductance will be very low when there is a short circuit in the output ( VISSC > 130 mV).
The short circuit signal, measured with the sense resistance Risen, is transferred by an
internal optocoupler and appears at the output pin FLT. When a short circuit is detected, the
IGBT will be turned–off until at the next pulse at the signal VIN.
PSDM
from DPR
to FLT
ISEN
disable
VO
11
Rf
Cf
65mV
Risen
130mV
KGND
4.
8
0V
Current sense Isen
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PSDM-0DT2-5020
PIN DPR
This terminal is used to measure the voltage drop across the turned-on power transistor in
order to ensure protection from short circuit and overload of the IGBT. This involves
monitoring the collector voltage and turning off the device if this voltage rises above a certain
limit. The best method for detecting desaturation is the use of an external high voltage clamp
diode D1 ( for example 1N4007) and an internal comparator. The PSDM has a desaturation
protection which senses the collector voltage and provides an output indicating when the
device is not fully saturated. When the IGBT is “on” and saturated, D1 will hold down the
voltage on the DPR. When the IGBT pulls out of saturation or is not “on”, the internal current
source (270 µA) will pull up the input and trip the comparator. The comparator threshold is
typically 6.5 V (DPRth). The resistor RRV is used to protect the PSDM from reverse voltage
transients and it shouldn’t be bigger than 1kΩ. The error will be transferred by means of an
internal optocoupler to the output pin FLT.
from ISEN
DPR
VCC
D1
Rrv
10
to FLT
270uA
disable
VO
Cblank
6.5V
KGND
PSDM
8
0V
VIN
5.
Desaturation protection Dpr
PIN FLT
The PSDM has an active high fault output. The fault output is internally interfaced to an
optocoupler. The LED drive provides a 10-20mA when on, and provides a low impedance
when off. The circuit integrated is shown below.
VFLT
RFLT
12
FLT
PSDM
14
GND
VCS2
6.
Output fault
FLT pin is enable only if will be used together with DPR or ISEN signal. (see overview 3 and 4).
The voltage VFLT can be pulled from 5V to 15V via a pull-up resistor. Allowed current is
10mA. The transistor in the optocoupler is pulled to GND when an error has been detected.
Therefore if no errors are detected the transistor is open.
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PSDM-0DT2-5020
In the following figures are represented active fault signal versus current sense and versus
desaturation protection. When the voltage through the shunt (RISEN) is more than VISSC we will
find a logic low signal. In the next side if the voltage measured by DPR is more than 6.5V, we
will find signal logic low at the pin FLT active fault.
16
FLT pin 12, A CTIVE FAULT OUTPUT, (V)
FLT pin 12, A CTIVE FAULT OUTPUT, (V)
16
14
12
10
8
6
4
2
14
12
10
8
6
4
2
0
0
90
100
110
120
130
140
150
160
6.1
170
7.
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
DPR pin 11, DESATURATION PROTECTION, (V)
ISEN pin 10, CURRENT SENSE, (mV)
FLT versus CURRENT SENSE
8.
FLT versus DESATURATION
PROTECTION
VDC = 15V, VDD = 5V, VIN = HIGH, TA = 25 °C .
In figure 6 is represented the turn off of the gate terminal when voltage at the pin 10 ISEN
exceed 130mV and having DPR enable (VDPR > 6.5 V). In the other figure the turned off of
the gate terminal appears when the voltage is more than 6.5 V and having ISEN enable (VISEN
> 130 mV).
PIN VIN
The input has a Schmitt trigger characteristic. HIGH level switches the power semiconductor
on; LOW level means a switch off state.
PIN VDD
A stabilized voltage supply between 4.5V and 5.5V with respect to GND.
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PSDM-0DT2-5020
OVERVIEW
Overview 1
VCS1
4
VCS2
6
SGND
5
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
Basic application connecting SGND with , ISEN,
DPR and KGND together.
ISEN and DPR should be connected together to
ground and, in this case you have no
protection of the circuit. If you need only a
single supply, already connected internally,
VES should be connected to the SGND.
Put separate resistances between VO and
IGBT if necessary to optimize the turn-on and
the turn-off of the semiconductor.
15V
-4V
0V
Rg1
D2
Rg2
0V
9.
Basic Application
5V
VIN
t
VO
t
0V
15 V
0V
tpLH
tpHL
10. Signal curves for the basic application
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PSDM-0DT2-5020
Overview 2
VCS1
4
VCS2
6
SGND
5
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
Dual supply basic application connecting
SGND with ISEN and DPR.
If you want connect a dual supply, connect
VCS2 to VES. Connection the DPR and ISEN to
the SGND means disable the protection
features of the PSDM. As shown in the first
overview the resistances Rg1 and Rg2 should
be choose to optimize turn-on and turn-off of
the semiconductor.
15V
-4V
0V
Rg1
D2
Rg2
0V
11. Dual supply basic application
5V
VIN
t
VO
t
0V
15 V
0V
-4 V
tpLH
tpHL
12. Signal curves for the dual supply basic application
Figure 11 show the delay between input and output signal. Using dual supply we will
have a square wave from VES and VCS1.
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PSDM-0DT2-5020
Overview 3
VCS1
4
VCS2
6
SGND
5
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
Desaturation application connecting VCS2 to
VES to have a dual supply for the gate. Enable
the desaturation protection pin connecting
VCS1 (the main supply) to ISEN. Moreover put a
high voltage diode in series to a resistor
between DPR and the IGBT collector as
illustrated in the picture from the side.
The blank capacitor should be connected from
DPR to VES.
15V
-4V
0V
D1
Rrv
Cblank
Rg1
D2
Rg2
0V
13. Desaturation application
VIN
t
VO
t
65mV
DPR
t
FLT
t
tpLH
tpHL
tCblank
0 < ts < tCblank
14. Signal curves for the desaturation application
As is shown in figure 13 when an error appears, that is when the voltage at pin DPR is
greater than 6.5V, the voltage across the gate of the transistor is kept at VES. This
error is transferred at the pin FLT with a certain delay due to Cblank.
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PSDM-0DT2-5020
Overview 4
VCS1
4
VCS2
6
SGND
5
Current sense application connecting VCS2 to
the VES to have a dual supply.
Using ISEN connector you should put a resistor
RIsen (shunt) between ISEN to KGND. The two
connections, ISEN and KGND should be routed
as a differential pair directly to pin 8 for KGND
and pin 10 for ISEN. To remove any high
frequency noise is used to put an RC filter as
shown in the figure on the left. Capacitor
between DPR and VCS2 is needed.
15V
-4V
0V
Rg1
D2
VES
7
KGND
8
VO
9
DPR
10
ISEN
11
Rg2
Cblank
Rf
Cf
Risen
0V
15. Current sense application
VIN
t
VO
t
130mV
65mV
ISEN
t
FLT
t
tpLH
tpHL
tCblank
0 < ts < tCblank
16. Signal curves for the current sense application
Figure 15 show two types of error. The first is when through the R sense flow more
than 65mV. The gate output VO is disabling until another pulse VIN appears. This is
due to an overcurrent. No signal is transferred to the fault pin FLT.
When a short circuit appear, across RISEN will flow more than 130mV. The output VO
is kept at VES and an error will be transferred to the fault pin FLT. At the next pulse of
VIN the error will be reset.
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PSDM-0DT2-5020
Layout and wiring
Drivers should as a rule be placed as close as possible to the power semiconductors
so that the leads from the driver to the transistors are as short as possible. Lead too
length must be avoided. When the power semiconductors are connected by stranded
wires, it is recommended always to twist the associated leads.
DPR 10
VO
9
PSDM
ISEN 11
twisted wires
KGND
8
0V
17. Twisted wires
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PSDM-0DT2-5020
Application examples
General application single phase
DC BUS +
PSDM-0DT25020
L
LOAD
µPC
N
PSDM-0DT25020
DC BUS -
Application in high current power supply
DC BUS +
µPC
PSDM-0DT25020
PSDM-0DT25020
+
µPC
µPC
PSDM-0DT25020
PSDM-0DT25020
DC BUS -
Application in motor AC inverter
DC BUS +
PSDM-0DT25020
µPC
PSDM-0DT25020
µPC
PSDM-0DT25020
U
V
µPC
W
PSDM-0DT25020
µPC
PSDM-0DT25020
µPC
M
PSDM-0DT25020
DC BUS -
http://www.timonta.ch
37 / 37
ver 1.0
revision 30.nov.2004
Timonta AG | Member of Schurter Group
Via San Martino 20 ¦ P.O. Box 1961
CH 6850 Mendrisio | Switzerland
Tel: +41 91 640 07 00 | Fax: + 41 91 640 07 01
mail: [email protected] | www.timonta.ch