Download 2006-02-20

EE539: Analog Integrated Circuit Design; Lecture 20
Nagendra Krishnapura ([email protected])
20 Feb. 2006
Biasing of transistors in Analog ICs
• AC coupling/large caps to short out signal not possible since IC capacitance values are quite small
and it will take enormous area to make capacitors to behave as short at relatively low frequencies
• Common-Drain amplifier: gain is independent of gm and if there is no body effect, change in bias
voltages doesn’t affect the gain.
• Common-Gate amplifier: the current gain is independent of g m . So, changes in bias don’t affect the
gain.
• Common-Source amplifier: gain depends on gm and it is not possible to get constant gain with changes
in bias if we use a single transistor. Either we have to use feedback or we have to go for a differential
amplifier.
Current Mirror
A reference current is made to pass through one transistor by diode connecting it.
s
2I0
VGS = VT +
µCox W
L
Now, if the same VGS is applied to another transistor, then a scaled version of the current flows through it
according to the aspect ratio. Equal aspect ratios give the same current.
Vdd
I0
W/L
I0
nI0
W/L
nW/L
Figure 1: Current Mirror
1
2
We have to design W/L according to the required minimum output voltage constraint.
W
2I0
>
2
L
(µCox )min Vout
If we use a large value of L, we might get a high resistance at DC, but the large capacitance reduces the
resistance at high frequencies. Its the other way around if we use a small value of L. So, we must choose the
value of L depending on the expected frequency of operation.
Fig. 2 shows a common drain amplifier biased using a current mirror.
Vdd
Vdd
Vbias+v
Vbias-VT-Vdsat+v
I0
I0
W/L
W/L
Figure 2: Common Drain biased by current mirror
Cascode current source
We can have a common gate structure above the current source in order to increase the output resistance.
rout =
gm2
1
1
+
+
gds2 gds1 gds1 gds2
I0
Vdd
I0
W/L
VG
M2
I0
W/L
M1
Figure 3: Cascode current source
The downside of this is that the minimum Vout is increased by Vdsat . Now, M2 needs to be biased properly
for the transistors to work in saturation. We see that
s
s
2I0
2I0
= VT +
VGmin = VT + 2
W
W
µCox L
µCox 4L
3
Vdd
I0
I0
Vdd
(W/4)/L
VG
M2
I0
I0
W/L
M1
W/L
Figure 4: Cascode current source properly biased
We can also have a triple cascode structure where we have one more common gate structure on top of the
g
cascode. This results in an increase in rout by a factor of g m . The minimum Vout increases further by Vdsat .
ds
Folded Cascode
In the folded cascode structure, the two transistors are of different type(p and n). An extra current source is
needed to provide bias currents for the two transistors.
Vdd
I1
Vbias1
M1
M2
Vbias2
I0
I0+I1
Vbias3
M0
Figure 5: Folded Cascode
rout ≈
gm2
gds2
1
gds0 + gds1