Download CXP80732A/80740A

CXP80732A/80740A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP80732A/80740A is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, VCR vertical sync separation circuit
and the measuring circuit which measure signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.
Also CXP80732A/80740A provides sleep/stop function
which enables to lower power consumption and ultralow speed instruction mode in 32kHz operation.
100 pin QFP (PIastic)
100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle
During operation 250ns/16MHz (Supply voltage 4.5 to 5.5V)
During operation 122µs/32kHz
• Incorporated ROM capacity
32K bytes (CXP80732A)
40K bytes (CXP80740A)
• Incorporated RAM capacity
800 bytes
• Peripheral functions
— A/D converter
8-bit, 12-channel, successive approximation system
(Conversion time 20.0µs/16MHz)
— Serial interface
Incorporated 8-bit and 8-stage FIFO, 1-channe
(1 to 8 bytes auto transfer)
8-bit serial I/O, 1-channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter
— High precision timing pattern generator
PPG 19 pins 32-stage programmable
RTG 5-pins 2-channel
— PWM/DA gate output
12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14-bit, 1-channel
— VISS/VASS circuit
Pulse duty auto detection circuit
— Remote control receiving circuit
8-bit pulse measuring counter, 6-stage FIFO
• Interruption
21 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP/LQFP
• Piggyback/evaluation chip
CXP87700 100-pin ceramic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume respons bility for any problems arising out of the use of these circuits.
–1–
E94Z09-ST
CXP80732A/80740A
PI5/SCK1
PI4/INT1/NMI
PI3/TO/DDO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0
PB7/PPO15
PB6/PPO14
Pin Configuration 1 (Top View) 100 pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB5/PPO13
1
80
PI6/SO1
PB4/PPO12
2
79
PI7/SI1
PB3/PPO11
3
78
PE0/INT0
PB2/PPO10
4
77
PE1/EC/INT2
PB1/PPO9
5
76
PE2/PWM0
PB0/PPO8
6
75
PE3/PWM1
PC7/RTO7
7
74
PE4/DAA0
PC6/RTO6
8
73
PE5/DAA1
PC5/RTO5
9
72
PE6/DAB0
PC4/RTO4
10
71
PE7/DAB1
PC3/RTO3
11
70
PG0/CFG
PC2/PPO18
12
69
PG1/DFG
PC1/PPO17
13
68
PG2/DPG
PC0/PPO16
14
67
PG3/PBCTL
PJ7
15
66
PG4/SYNC0
PJ6
16
65
PG5/SYNC1
PJ5
17
64
PG6/EXI0
PJ4
18
63
PG7/EXI1
PJ3
19
62
AN0
PJ2
20
61
AN1
PJ1
21
60
AN2
PJ0
22
59
AN3
PD7
23
58
PF0/AN4
PD6
24
57
PF1/AN5
PD5
25
56
PF2/AN6
PD4
26
55
PF3/AN7
PD3
27
54
AVDD
PD2
28
53
AVREF
PD1
29
52
AVSS
PD0
30
51
PF4/AN8
Note)
PF5/AN9
PF6/AN10
PF7/AN11
SCK0
SO0
SI0
CS0
XTAL
EXTAL
VSS
RST
MP
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
–3–
CXP80732A/80740A
PE0/INT0
PI7/SI1
PI6/SO1
PI5/SCK1
PI4/INT1/NMI
PI3/TO/DDO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0
PB7/PPO15
PB6/PPO14
PB5/PPO13
PB4/PPO12
Pin Configuration 2 (Top View) 100 pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB3/PPO11
1
75
PB2/PPO10
2
74
PE2/PWM0
PB1/PPO9
3
73
PE3/PWM1
PE1/EC/INT2
PB0/PPO8
4
72
PE4/DAA0
PC7/RTO7
5
71
PE5/DAA1
PC6/RTO6
6
70
PE6/DAB0
PC5/RTO5
7
69
PE7/DAB1
PC4/RTO4
8
68
PG0/CFG
PC3/RTO3
9
67
PG1/DFG
PC2/PPO18
10
66
PG2/DPG
PC1/PPO17
11
65
PG3/PBCTL
PC0/PPO16
12
64
PG4/SYNC0
PJ7
13
63
PG5/SYNC1
PJ6
14
62
PG6/EXI0
PJ5
15
61
PG7/EXI1
PJ4
16
60
AN0
PJ3
17
59
AN1
PJ2
18
58
AN2
PJ1
19
57
AN3
PJ0
20
56
PF0/AN4
PD7
21
55
PF1/AN5
PD6
22
54
PF2/AN6
PD5
23
53
PF3/AN7
PD4
24
52
AVDD
PD3
25
51
AVREF
Note)
1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
–4–
AVSS
PF4/AN8
PF5/AN9
PF6/AN10
PF7/AN11
SCK0
SI0
SO0
CS0
EXTAL
XTAL
VSS
MP
RST
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PD0
PD1
PD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP80732A/80740A
Pin Description
Symbol
I/O
Description
Output/
Real time
Output
(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
PB0/PPO8
to
PB7/PPO15
Output/
Real time
Output
(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
PC0/PPO16
to
PC2/PPO18
I/O/
Real time
Output
PC3/RTO3
to
PC7/RTO7
I/O/
Real time
Output
PA0/PPO0
to
PA7/PPO7
(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)
Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)
(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)
PD0 to PD7
I/O
PE0/INT0
Input/input
Input pin to request external interruption.
Active when falling edge.
PE1/EC/INT2
Input/input/input
External event Input pin to request
external interruption.
input pin for
timer/counter. Active when falling edge.
PE2/PWM0
Output/output
PE3/PWM1
Output/output
PE4/DAA0
Output/output
PE5/DAA1
Output/output
PE6/DAB0
Output/output
PE7/DAB1
Output/output
AN0 to AN3
Input
Analog input pins to A/D converter. (12 pins)
PF0/AN4
to
PF3/AN7
Input/input
PF4/AN8
to
PF7/AN11
Output/input
(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)
SCK0
I/O
Serial clock (CH0) I/O pin.
SO0
Ouput
Serial data (CH0) output pin.
SI0
Input
Serial data (CH0) input pin.
CS0
Input
Serial chip select (CH0) input pin.
(Port E)
8-bit port. Lower 2 bits are
input pins and upper 6 bits
are output pins.
(8 pins)
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
–5–
CXP80732A/80740A
Symbol
I/O
Description
PG0/CFG
Input/input
Capstan FG input pin.
PG1/DFG
Input/input
Drum FG input pin.
PG2/DPG
Input/input
Drum PG input pin.
PG3/PBCTL
Input/input
PG4/SYNC0
Input/input
PG5/SYNC1
Input/input
PG6/EXI0
Input/input
PG7/EXI1
Input/input
(Port G)
8-bit input port.
(8 pins)
Playback CTL pulse input pin.
Composite sync signal input pin.
External input pin to FRC capture unit.
(Port H)
8-bit output port ; Medium withstand voltage (12V) and high current
(12mA), N-ch open drain output.
(8 pins)
PH0 to PH7
Output
PI1/RMC
I/O/input
Remote control receiving circuit input pin.
PI2/PWM
I/O/output
14-bit PWM output pin.
PI3/TO/
DDO/ADJ
I/O/output/
output/output
PI4/INT1/
NMI
I/O/input/Input
PI5/SCK1
I/O/I/O
PI6/SO1
I/O/output
Serial data (CH1) output pin.
PI7/SI1
I/O/input
Serial data (CH1) input pin.
PJ0 to PJ7
I/O
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)
RST
Input
System reset pin of active "L" level.
MP
Input
Microprocessor mode input pin. Always connect to GND.
Timer/counter, CTL duty detection,
32kHz oscillation adjustment output pin.
Input pin to request external interruption and non
maskable interruption. Active when falling edge.
Serial clock (CH1) I/O pin.
(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.
Positive power supply pin of A/D converter.
AVDD
AVREF
(Port I)
7-bit I/O port.
I/O port can be
specified by bit
unit.
(7 pins)
Input
Reference voltage input pin of A/D converter.
AVss
GND pin of A/D converter.
VDD
Positive power supply pin.
Vss
GND pin. Connect both Vss pins to GND.
–6–
CXP80732A/80740A
Absolute Maximum Ratings
Item
(Vss = 0V)
Symbol
Rating
Unit
–0.3 to +7.0
AVss to +7.0∗1
V
V
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
Medium withstand output voltage
VOUTP
–0.3 to +15.0
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Total of output pins
IOL
15
mA
IOLC
20
mA
Other than high current output
pins: per pin
High current port pin∗3: per pin
Low level total output current
∑IOL
130
mA
Total of output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
VDD
Supply voltage
AVDD
AVSS
Input voltage
Low level output current
V
V
600
380
Remarks
mW
PH pin
QFP package type
LQFP package type
∗1) AVDD and VDD should be set to a same voltage.
∗2) VIN and VOUT should not exceed VDD + 0.3V.
∗3) The high current operation transistors are the N-CH transistors of the PD and PH ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 12 –
CXP80732A/80740A
Recommended Operating Conditions
Item
Supply voltage
Analog power supply
High level
input voltage
Symbol
(Vss=0V)
Min.
Max.
Unit
Remarks
4.5
5.5
V
Guaranteed range during high speed mode
(1/2 dividing clock) operation
3.5
5.5
V
Guaranteed range during low speed mode
(1/16 dividing clock) operation
2.7
5.5
V
Guaranteed operation range by TEX clock
2.5
5.5
V
4.5
5.5
V
Guaranteed data hold operation range
during STOP
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
VIHTS
2.2
VDD
V
VDD
AVDD
VIHEX
VDD – 0.4 VDD + 0.3
V
CMOS schmitt input∗3
TTL schmitt input∗4
EXTAL pin∗5
∗2
TEX pin∗6
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILTS
0
0.8
V
CMOS schmitt input∗3
TTL schmitt input∗4
VILEX
–0.3
0.4
V
EXTAL pin∗5
Operating temperature Topr
–20
+75
°C
Low level
input voltage
TEX pin∗6
∗1) AVDD and VDD should be set to a same voltage.
∗2) Normal input port (each pin of PC, PD, PE0 to PE1, PF0 to PF3, PG, PI and PJ), MP pin.
∗3) Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt
input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.
∗4) Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)
∗5) It specifies only when the external clock is input.
∗6) It specifies only when the event count clock is input.
– 13 –
CXP80732A/80740A
Electrical Characteristics
DC Characteristics
(Ta = –20 to +75°C, Vss = 0V)
Pins
High level
output voltage
VOH
PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
PD, PH
VDD = 4.5V, IOL = 12.0mA
1.5
V
VOL
IIHE
Min.
Typ.
Unit
Symbol
Low level
output voltage
Conditions
Max.
Item
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–10
µA
IILR
VDD = 5.5V,
VIL = 0.4V
–0.1
RST∗1
–1.5
–400
µA
I/O leakage
current
IIZ
PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST∗1
VDD = 5.5V,
VI = 0, 5.5V
±10
µA
Open drain
output leakage
current (N-CH
Tr OFF in state)
ILOH
PH
VDD = 5.5V
VOH = 12V
50
µA
22
45
mA
1.1
8
mA
33
100
µA
7
30
µA
10
µA
20
pF
IILE
Input current
EXTAL
IIHT
IILT
TEX
16MHz crystal oscillation (C1=C2=15pF)
IDD1
VDD = 5V ± 0.5V∗3
SLEEP mode
IDDS1
VDD = 5V ± 0.5V
Supply
current∗2
IDD2
IDDS2
32kHz crystal oscillation (C1=C2=47pF)
VDD
VDD=3V ± 0.3V
SLEEP mode
VDD = 3V ± 0.3V
IDDS3
STOP mode
(EXTAL and TEX pins oscillation stop)
VDD = 5V ± 0.5V
Input capacity
CIN
Other than VDD,
Clock 1MHz
Vss, AVDD, and
0V other than the measured pins
AVss
10
∗1) RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗2) When entire output pins are open.
∗3) When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
– 14 –
CXP80732A/80740A
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
Condition
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
16000/fc
ns
SCK0
high and low level widths
tKH
tKL
tsys + 100
ns
SCK0
8000/fc – 50
ns
SI0 input setup time
(against SCK0 ↑)
SCK0 input mode
100
ns
tSIK
SI0
SCK0 output mode
200
ns
SI0 input hold time
(against SCK0 ↑)
SI0
tsys + 200
ns
tKSI
100
ns
SCK0 ↓ → SO0 delay time
tKSO
SO0
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = “00”), 4000/fc (Upper 2-bit = “01”), 16000/fc (Upper 2-bit = “11”)
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 16 –
CXP80732A/80740A
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tS K
tKSI
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output
data
0.2VDD
– 17 –
CXP80732A/80740A
Serial transfer (CH1)
Item
(Ta=–20 to +75°C, VDD=4.5 to 5.5V, Vss=0V)
Symbol
Pins
Conditions
Min.
Input mode
SCK1 cycle time
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Unit
1000
ns
16000/fc
ns
400
ns
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Output mode
Input mode
Output mode
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
SI1
Max.
Input data
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 18 –
CXP80732A/80740A
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pins
Conditions
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
NMI
PJ0 to PJ7
Reset input low level width
tRSL
RST
Min.
Max.
Unit
1
µs
32/fc
µs
Fig. 7. Interruption input timing
INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)
tIH
tIL
0.8VDD
0.2VDD
Fig. 8. Reset input timing
tRSL
RST
0.2VDD
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
(5) Others
Item
Symbol
tCFH
tCFL
tDFH
DFG input
tDFL
high and low level widths
DPG minimum pulse width tDPW
CFG input
high and low level widths
DPG minimum
removal time
trem
PBCTL input
high and low level widths
tCTH
tCTL
tEIH
tEIL
EXI input
high and low level widths
Pins
Conditions
Min.
Max.
Unit
CFG
tFRC × 24 + 200
ns
DFG
tFRC × 8 + 200
ns
DPG
50
ns
DPG
50
ns
PBCTL
tsys = 2000/fc
tFRC × 8 + 200 + tsys
ns
EXI0
EXI1
tsys = 2000/fc
tFRC × 8 + 200 + tsys
ns
Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = “00”), 4000/fc (Upper 2-bit = “01”), 16000/fc (Upper 2-bit = “11”)
tFRC [ns] = 1000/fc
– 20 –
CXP80732A/80740A
Fig. 9. Other timings
tCFH
tCFL
0.8VDD
CFG
0.2VDD
tDFH
tDFL
0.8VDD
DFG
0.2VDD
trem
tDPW
trem
0.8VDD
DPG
tCTH
tCTL
0.8VDD
PBCTL
0.2VDD
tEIH
EXI0
EXI1
tE L
0.8VDD
0.2VDD
– 21 –