Download Heterostructure Design and Demonstration of InGaSb Channel III

ISDRS 2011, December 7-9, 2011, College Park, MD, USA
Student Paper
Heterostructure Design and Demonstration of InGaSb Channel III-V CMOS Transistors
Ze Yuana, Aneesh Nainania, Brian R. Bennettb, J. Brad Boosb, Mario G. Anconab, Krishna C. Saraswata
a
Department of Electrical Engineering, Stanford University, USA, [email protected]
b
Naval Research Laboratory, USA.
Introduction: Despite burgeoning interest in III-V’s for realizing high performance transistors at
low power, III-V MOSFEts have been plagued by poor PMOS performance. Realizing high mobility
InGaAs PMOS [1] and Ge NMOS [2] has proven to be difficult. To avoid complications in CMOS circuit
design and manufacturing [3], it is favorable to employ a single material system that enables both good
NMOS and PMOS transistors. We chose to work on the 6.1-6.2Å lattice constant system with InGaSb as
the channel material because of its advantages in terms of band engineering and high mobility/offsets for
both electrons and holes [4-5].
Heterostructure design for CMOS: AlGaSb/InGaSb provides both a type-I band lineup that can
confine both electrons and holes, and high electron and hole mobilities (Fig.1) [5]. XPS allows the
valence-band offset (VBO) to be determined by comparing the VB spectrum of InGaSb and AlGaSb
using the Ga peak as a reference (Fig. 2). Bandgaps extracted from PL measurements (Fig. 3) allow the
conduction-band offset (CBO) to also be calculated (Fig. 1). With sufficient VBO and CBO, the
heterostructure design can thus confine both electrons/holes. Fig. 4 shows a TB simulation of the
accumulation of electrons and holes within the stack. At relevant sheet charge density (N S) for MOSFET
operation, 80/90% of the electron/hole can be confined in the channel. Gated Hall measurements on this
heterostructure (Fig. 5) show 7X/2.5X higher µe and 7X/4X higher µh at an NS of 1×1012/6×1012cm-2 for
electrons and holes respectively, compared with Si universal mobilities.
Metal S/D transistor design: S/D designs with low extrinsic resistance are challenging for IIIVs, because of low solubility and poor activation of dopants and also because of the “source starvation”
effect due to low DOS in III-Vs [6]. Use of metal S/D (Fig. 6) overcomes these problems; a slight overlap
is introduced between the gate and S/D to reduce access resistance. Both PMOS and NMOS are
fabricated on the same heterostructure stack except with the top layer being intrinsically p-/n-doped,
respectively. Well-behaved Cgc-V characteristics are obtained on both p-/n-type samples (Fig. 7). Transfer
and output characteristics of the transistors are shown in Fig. 8 & Fig. 9 respectively. For the NMOS the
current levels do not scale linearly with drain voltage (Fig. 8), and appear limited by extrinsic resistance
(Fig. 9) due to high contact resistance, which is clearly the main challenge for InGaSb NMOS.
MIS S/D contact: At metal/GaSb interface, the Fermi-level is pinned near the valence band edge
[7]. While helpful for achieving good PMOS, this severely limits the ION of the NMOS. To improve the ntype contact, a TiO2 interfacial layer was inserted to lower the barrier height for electron injection. In
contrast with other MIS schemes for Fermi-level unpinning, TiO2 lowers the barrier height without
introducing tunneling resistance due to the low CBO of TiO2/GaSb [8]. More than 5X improvement in ION
is obtained for NMOS with the introduction of TiO2 (Fig. 10). The NMOS on-state current remains
limited by RC due to thinness of the surface channel and consequent depletion of electrons in the contact
regions. This leaves room for further improvement in device performance of NMOS with MIS S/D
contact.
Summary: Electron/hole mobility > 4000/900cm2/Vs is achieved in this single channel material.
Contact resistance is identified as the main challenge for InGaSb NMOS and we show that this can be
much improved with a TiO2 interfacial layer.
References
[1] I. Ok, et al., IEDM, 2006. [2] D. Kuzum, et al., IEDM, 2009. [3] D. Lin, et al., IEDM, 2009. [4] H.
Kroemer, Physica E, vol. 20, pp. 196, 2004. [5] B. R. Bennett et al., Journal of Crystal Growth, vol. 312,
pp. 37, 2009. [6] M. V. Fischetti et al., IEDM 2007. [7] Z. Yuan et al., DRC 2011. [8] Z. Yuan et al.,
Applied Physics Letters, vol. 98, no. 172106, 2011.
ISDRS 2011 – http://www.ece.umd.edu/ISDRS2011
ISDRS 2011, December 7-9, 2011, College Park, MD, USA
Fig. 1: InGaSb/AlGaSb
forms type-I hetero-structure
with sufficient CBO/VBO to
confine both electrons and
holes.
Fig. 2: VBO is measured by
taking the difference between
XPS measured VB spectrum
from the channel and the
buffer.
Fig. 3: Bandgaps of AlGaSb, InGaSb
and GaAs are measured from PL at
80K.
Fig. 5: (a) Electron and
(b)
hole
mobility
measured in InxGa1-xSb
channel
vs.
sheet
charge using gated Hall
measurement.
Electron/hole mobility
is > 2.5X/4X higher
compared
to
Si
universal
mobilities
even at high Ns.
Fig. 4: Results from TB
calculation
show
(a)
heterostrcture design can provide
high NS at given overdrive
voltage (Vov) (b) most of the
charge is confined in the high μ
channel.
Fig. 6: Metal S/D
structure
where
Top surface layer is
n/p-type
for
N/PMOS
respectively.
Fig. 7: Well behaved Cgc vs VG characteristics are
obtained on both (a) p (b) n- type InGaSb.
Fig. 8: Transfer characteristics for (a) PMOS and
(b) NMOS with metal S/D. NMOS ID-VG scales non
linearly with voltage due to high contact resistance.
Fig. 10: 5X increase in ION for
NMOS is achieved with the
insertion of TiO2 in S/D.
Fig. 9: Output characteristics for (a) PMOS and (b)
NMOS with metal S/D. NMOS characteristics are
largely limited by the high contact resistance.
ISDRS 2011 – http://www.ece.umd.edu/ISDRS2011