Download Introduction to CMOS Design

ECE 520 Class Notes
Introduction to CMOS Design
Dr. Paul D. Franzon
Outline
1. CMOS Transistors
2. CMOS cell design
3. Transistor Sizing
4. Low Power Design
References
z Smith and Franzon, Chapter 11
z Weste and Eshraghian, Principles of CMOS VLSI Design,
A Systems Perspective
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
CMOS Transistors
Gate
1. nMOS Transistor
Polysilicon Conductor
Silicon Oxide Gate
Drain
Source
n
n
W
p substrate
Gate
Drain
Gate
L
Source
Drain
Source
substrate
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Transistors
Gate
2. pMOS transistor:
Silicon Oxide Gate
Drain
Source
p
p
W
n substrate
Gate
Drain
Gate
L
Source
Drain
Source
substrate
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
MOS Transistor Theory
Transistor States:
1. Cutoff Region
Ids = 0 when Vgs < Vt
Vt = Threshold Voltage (typically 1 V for nMOS, - 1V for pMOS)
2. Linear Region
Ids = Β ((Vgs - Vt)Vds - Vds2/2)
when 0 < Vds < Vgs - Vt
Β=(µε/tox)(W/L)
W = channel width
L = channel length
µ = electron (n) / hole (p) mobility
ε = permittivity of gate insulator
tox = gate insulator (oxide) thickness
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
... nMOS Transistor Theory
.... Transistor States
3. Saturatation Region
Ids = Β (Vgs - Vt)2
when 0 < Vgs - Vt < Vds
Q: Draw a large signal equivalent model for transistor in Linear and
Saturation States for falling output:
t=0
Vo<VDD-Vtn
Transistor Characteristics:
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Transistor Characteristics
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
CMOS Inverter
Static CMOS Inverter:
5V
p1
Vin
n1
Vout
0V
What are the transistor states when:
Vin = 0 V
n1 : VGS < Vt : Off
p1 : |VGS| > |Vt|, Vds=0 : Linear
Vin = 5 V
n1 : VGS > Vt, VDS=0 : Linear
p1 : |VGS| < |Vt| : Off
given |Vt| = 1 V
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Transistor Speed is determined by SIZE
CMOS circuit speeds can be modeled to a first approximation as RC delays:
1. What does the input of a CMOS gate `look like’?
Capacitor, C ∝ W x L
2. What does the `output’ of a CMOS gate `look like’ during switching?
Resistor, R ∝ L/W
3. Usually hole mobility is half of electron mobility. So what must you do to
make the pull up and pull down delays about the same?
Equalize RC constants, Wp/Wn = µn/µp
4. If a gate is heavilly loaded what must you do to speed up the delay?
Decrease RC, Make gate wider
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Other Gate Designs
Refer to data sheets in CMOSX library:
z NOR gate
Analyze the circuits to determine `how
these gates work’.
A0 A1 : N0 N1 P0 P1 : Y
0
0
:
Off Off On On : 1
0
1
: On Off Off On : 0
1
0
: Off On On Off : 0
1
1
: On On Off Off : 0
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
DFF
Master
Slave
Clock buffer (guarantees clock edge rate and thus tsu, thold)
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
DFF
Function:
D Ck : Output
0
0 :
1
0
1 :
z
1
0 :
0
1
1 :
0
D
Ck’
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
Ck
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ECE 520 Class Notes
DFF
Function:
Regenerative Latch
- Feedbacks MQ when Ck high
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
DFF
Master
Propagates D
when Ck low
Slave
Regenerates
Propagates D
D when Ck high when Ck high
Regenerates
D when Ck low
Positive Edge Flip-Flip
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Power Consumption
Why is power consumption important?
z Battery powered devices
z
z
Minimize cost of wall-powered systems
z
Plastic packaging is 10x cheaper than ceramic packaging but can only
dissipate 1 - 2 W
‹ What happens if the chip gets too hot?
Failure rate gets too high
z
Need a fan to cool somewhere above 10 W
Difficult to air cool at all somewhere above 50 W
Cost of power supply
z
z
z
Maximize battery life
`Green’ systems
z
Minimize pollution by reducing demand from power stations
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Power Consumption in Digital Electronics
Bipolar Circuits:
z
z
z
Always draw DC current
Average current per gate high
Gate layout area larger than CMOS
CMOS Circuits:
z
z
Static CMOS draws current only when it changes state
‹ When input = Vcc, nMOS transistor off
‹ When input = GND, pMOS transistor off
‹ Gate load = capacitor, no current load
‹ Reverse current through backbiased pn junction to substrate is small
unless Vcc is very small
‹ `through’ current small during switching
Derive power consumption for CMOS:
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
CMOS Circuit
Circuit during switching event
• E.g. Inverter driving a load:
• When Vout 0Æ1: E =
Vdd
Vdd
0
0
∫ (Vdd − Vout ) Idt = ∫ (Vdd − Vout )CdVout =
CVdd
2
2
• Complete 010 toggle : E = CVdd2
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Minimizing Power Consumption
Power consumption in a CMOS module:
Power = Σ Nswitch f Vcc2 Cload
z
z
z
z
Sum over all nodes in circuit
f = clock frequency
Nswitch = average % of clock periods in which node toggles (I.e. 010 or 101)
Cload = capacitance of node
Approaches to minimizing power consumption
z
z
z
Reduce Supply Voltage
Reduce clock frequency
‹ Only useful when performance can be satisfied with slower clock
‹ Can induce `sleep’ mode by turning off clock, or `idle’ mode by slowing
clock down a lot
Reduce Nswitch through clever design
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Reducing Power Consumption Through Design
Example:
reg [31:0] A, B, D;
always@(posedge clock)
begin
if (C) D <= A+B;
else D <= A;
end
A
B
D
+
C
Wasted power when C low
Possible ways to reduce power:
0
A
B
D
+
0
C
C
C
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Power Reduction
If C is low a lot…
0
A
B
D
+
0
C
C
C
assign E=C?A:0;
assign F=C?B:0;
always@(posedge clock)
if (C) D <= E+F;
else D <= A;
Only useful if C is low more than 50% of the time.
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
Power Reduction
Other Alternatives:
z
Gate the clock to register D
‹ Smallest overhead
‹ Complicates clock design and timing
‹ Usually gated clockes only done at “block level” (.e.g an FPU)
z
Store previous value of A and B in a register
‹ Used instead of 0 input to mux
‹ Must consider power overhead of register (including extra Cload on
clock)
‹ Not likely to be beneficial here
‹ Might be beneficial for a larger design (e.g. multiplier)
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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ECE 520 Class Notes
z
Summary
Complementary MOS transistors gives dense circuits and
lower power than other circuit families
z
z
z
z
Standard Cell designs use Static CMOS
Transistor speed approximated using `on resistance’
Ron proportional to electron/hole mobility and W/L
‹ Hole mobility = half electron mobility
Î Inverter Wp = 2 Wn to make trise = tfall
‹ To drive larger loads, increase transistor width proportionally
Power consumption important in many designs
Power = Σ Nswitch f Vcc2 Cload
z
z
z
Lower ing voltage by one-half, quarters the power but halves the
speed
Turn clock frequency down when performance not needed
Reduce Nswitch through good design
© 2003, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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