Download Intelligent Energy Management (IEM)

HOT Chips 2003
Intelligent Energy Management:
An SoC design based on ARM926EJ-S
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Need for Energy Management
„
Today’s mobile consumers want:
„
longer battery life and
„ smaller, lighter products
„
Manufacturers are adding new
features and applications to add
product appeal:
„
media players (audio, video)
„ gaming
„ video capture
¾
„
Increasing processing power requirements and
longer battery life are conflicting requirements
Battery technology alone offers only incremental
improvement over the next several years
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Intelligent Energy Management (IEM)
„
„
„
Conserving power whilst running = saving energy
Running only fast enough to do the work just in time
Adapting to changing software workloads
Processor
Utilization
100%
Conventional
On/Off Power
Management
Energy Used
0%
t
100%
Dynamic
Voltage
Scaling
Energy Used
0%
t
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Dynamic Voltage Scaling (DVS)
Voltage is the only parameter that
affects all types of power consumption:
„
Dynamic
„ Static leakage
„ Gate oxide leakage
„
2.20
2.00
Vcore (V)
1.80
10
1.40
350
8
1.20
Measured Vcc
Vcc + safety margin
250
6
200
150
4
Voltage^3
Power (mW)
300
1.60
1.00
0
20
40
60
80
100
120
140
160
180
Frequency (MHz)
100
Power
50
2
v^3
0
0
50
100
150
„
0
200
Frequency (MHz)
THE ARCHITECTURE FOR THE DIGITAL WORLD
Intelligent control of
DVS designs will bring
energy savings
TM
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200
Energy Management System
System-on-Chip (SoC)
ARM Core
Vdd
Apps
PMU
OS
Power
Management
Unit
IEM
Intelligent
Energy
Manager
IEC
Perform ance
PC
Intelligent
Energy
Controller
Comms
Power
Controller
DCG
CPU Clk
„
„
Dynamic
Clock
Generator
IEM and IEC components work together to predict
lowest acceptable processor performance level
Power Controller, PMU and Clock Generator work
together to deliver that lowest performance level
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IEM: prediction software
User processes
•Monitored through kernel hooks
•System calls
•Task switch / create / exit
•May specify application specific hints
Performance policy modules
Kernel
System calls
Scheduler
Hooks
„
„
„
Conventional
Power Manager
(Sleep / awake)
IEM module
•Multiple policies
•Best chosen dynamically
•Coordinates policies
•Controls performance setting
•Event tracing
•/proc interface
IEM software uses custom hooks in OS kernel to
instrument application software activity
Multiple algorithms determine performance level
requirement for different classes of activity
Best global performance determined dynamically
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IEC: control and monitoring hardware
„
„
Delivers an abstracted view of the power control
and delivery components of the device
Supplies a 0-100% performance level request to
the
Power Controller and
„ Dynamic Clock Generator
„
„
„
Plugs into SoC design as a using a standard
ARM AMBA compliant interface (APB)
Provides hardware assist to IEM software
Dynamic performance counters
„ Reduces the monitoring software overhead
„
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Adaptive Voltage Scaling (AVS)
„
AVS is a closed loop control mechanism
Feedback from the PMU indicates the earliest
opportunity to change processor frequency based on
the voltage levels being output to the SoC
„ APC monitors the difference between the requested
performance level and the actual level achieved
„
„
„
„
Taking into account variations due to differences in
process technology and ambient temperature the
system dynamically changes the voltage applied
The lowest energy consumption is achieved OR
A specified performance level can be met
THE ARCHITECTURE FOR THE DIGITAL WORLD
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AVS Energy Management System
System-on-Chip (SoC)
ARM Core
Hardware
Performance
Monitor
Vdd
EMU
Apps
"PowerWise"
Energy
Management
Unit
OS
IEM
Intelligent
Energy
Manager
Performance
IEC
APC
Intelligent
Energy
Controller
Adaptive
Power
Controller
PowerWise
Interface
Dynamic Clock
Generator
„
„
APC operates in closed loop control mode using
HPM to adapt to actual process and temperature
PowerWise™ Interface provides fast control of
EMU and feedback of status for optimum control
THE ARCHITECTURE FOR THE DIGITAL WORLD
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PowerWise™ technology
„
Adaptive Power Controller (APC)
Manages performance level requests
„ Uses hardware monitor to reduce safety margins
„
„
PowerWise Interface (PWI)
High-peed, low-power 2-wire comms. interface
between APC and SoC-wide power supplies
„ To be published as open standard (9/03)
„
„
Power Management Unit (PMU)
High-performance, off-chip power supply
„ Interfaces using PWI
„ Supports open and closed loop control
„
THE ARCHITECTURE FOR THE DIGITAL WORLD
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DVS Control Sub-system
IEC
DPC
Config.
Configuration Interface
APB
DPM
Dynamic Performance
Monitor
cpuclk
CPU
CLKGEN
Perf.
Index
CLK
Target
Current
Target
Current
Max
Perf
DPC
Dynamic Performance
Controller
Perf.
Index
Dynamic
Power
Controller
Voltage vs.
Frequency
Lookup table
DPC
CLKGEN
V_Ready
DCG
Dynamic Clock Generator
(SoC specific)
THE ARCHITECTURE FOR THE DIGITAL WORLD
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DATA
Integration challenges
„
Multiple voltage domains (and interfaces)
„
Commercial voltage scaling exploited at chip not SOC level
„ Level-shifter technology abstraction required
„ Builds on power-down and state-retention ‘islands’
„
Multiple (asynchronous) clock domains
„
Real-time domains typically require fixed clocks
„ Variable voltage domains quantize frequency
„ External memory clock rates often fixed
„
External power-control interface handshakes
„
„
Efficient management of voltage/frequency (PLL) settling times
Design verification and test
„
Gap between RTL (ideal clocks, implicit power) and layout
„ Static timing analysis and clock distribution in particular
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Collaborative SoC Design
Complete Energy Management solution requires:
„ (Off-chip) Power switcher technology
„
„
Semiconductor cell/RAM library technology
„
„
„
„
„
Characterization across voltage/process
Level-shifter technology
On-chip power control technology
System level design methodology/EDA tools
Software/API support for OS
„
¾
Responsive and controllable
Predictive performance setting algorithms
Partnership approach to implementation
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Prototype IEM test chip
„
„
„
„
„
„
„
ARM926EJ-S core
Multiple power domains
Voltage and frequency scaling
of CPU, caches and TCMs
First full DVS silicon with
National Semiconductor
PowerWise™ technology
NSC Adaptive Power Controller
(APC) implemented in FPGA
Delivered from TSMC 0.13µm fab. in July 2003
Developed by ARM and National Semiconductor
using Synopsis EDA tools
THE ARCHITECTURE FOR THE DIGITAL WORLD
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IEM test chip power domains
CPU
domain
16kByte
I-CACHE
16kByte
Peripheral bus
domain
Multi-ICE
JTAG
TAP
D-CACHE
16kByte
PLL1
Async.
domain
INSTR-SRAM
ARM926EJS
16kByte
Power,
Test,
Reset
& Clock
control
POWER
MANAGER
DATA SRAM
AHB BIU
DW_INTC
System bus domain
PLL2
APB
AHB_D
AHB_I
DW_TIMER x2
AHB/APB
Bridge
DW_GPIO x 4
DMA
2-port
AHB_S
DW_UART x 2
Matrix
DW_RTC
3-port Matrix
Sound
Async.
domain
SDRAM/
FLASH
Memory Controller
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Test chip : CPU subsystem
CPURESET_N
L-SHIFT / CLAMP
CPUCLK
Tightly Coupled
TCM
Memories
(TCMs)
CLAMP
Dynamic Voltage
RAM with state
retention
VDDRAM
Dynamic Voltage
CPU with
power-down
VDDCPU
CLAMP
ARM926EJ
CACHE
CACHE
RAMS
RAMS
L-SHIFT L-SHIFT
„
Dynamically scale voltage to both CPU and RAMs
„
„
But support state save to RAM and power-down of CPU
Level-shifter cells interface to always-powered SOC logic
„
Clamps hold signals low when domain voltage “unsafe”
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Testchip : board-level testbench
VBAT
Dynamic Voltage
RAM with state
retention
TCM
TCMS
L-SHIFT / CLAMP
CPUCLK
CPURESET_N
CLAMP
CLAMP
Dynamic Voltage
CPU with
power-down
CACHE
CACHE
RAMS
RAMS
ARM926EJ
PSU_VDD
CPU
(0v7-1v2)
Performance
Monitor
L-SHIFT L-SHIFT
HCLK
PSU_VDD
RAM
(0v7-1v2)
PWI
PowerWise Interface
L-SHIFT
TARGETCLK
phi2LAT phi1LAT
NSC
APC
DBG /
Multi-ICE
Synch
IEC
APB
AMBA AHB/APB subsystem
Dynamic
Performance
Controller
INIT [N]
NSC
APC
PERF
FPGA
serializer
Adaptive
Power
Controller
FPGA
prototype
Dynamic
Performance
Monitor
PSU_VDD
SOC (1v2)
CPU_PERF
PCLK
HCLK
CPURESET_N
CPUCLK
DCG
Clock/
Reset
TARGETCLK
SOC
V_READY[N]
PSU_VDD
PADS
(3v3)
PLL(s)
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Benchmarking
„
Clear requirement to develop benchmarks
Standby time taken care of by conventional
power management schemes (run/idle/sleep)
„ Focusing on applications processors and
smartphone functionality (more “running” time)
„
„ MP3
players – sound recording
„ MPEG4 video clip players/capture
„ Games – graphics accelerators
„ E-mail and web access (WAP), messaging
„
„
Need to measure energy saving and quality
No established benchmarking standards exist
today that show quality at low performance
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Energy Management in Action
Performance
100%
83%
66%
50%
Playing
Play ►
2 seconds
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Wrap Up
„
Dynamic performance control is an attractive
way of achieving energy management in
battery–powered embedded devices BUT
1.
There are many challenges at the SoC design
level in implementing multiple power domains:
„
„
2.
Interfacing between power domains
EDA tools support
Maximising the benefits of techniques like
Dynamic Voltage Scaling requires:
„
„
„
SoC designs that include appropriate controls
Advanced software to manage performance
Standard s/w and h/w interfaces to allow reuse
THE ARCHITECTURE FOR THE DIGITAL WORLD
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Intelligent Energy Management
Thank you for listening.
Any Questions?
ARM contacts:
„
David Flynn, Engineering Fellow
„ [email protected]
„
Clive Watts, Program Manager
„ [email protected]
THE ARCHITECTURE FOR THE DIGITAL WORLD
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