Download Electronics Devices and Circuits

Vidyalankar
S.Y. Diploma : Sem. III
[EJ/EN/ET/EX/EV/ED/IU/DE/IS/IC/IE/MU]
Electronics Devices and Circuits
Prelim Question Paper Solution
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1. (a) (i) A circuit used for establishing Quiscent operating point (Q) in the centre of
active region to avoid distortion is defined as transistor biasing circuit. For this
purpose, normally circuit uses one external d.c. supply, few resistors and may
be 1 capacitor. By choosing their values properly, B  E junction is forward
biased and B  C junction is reverse biased.
1. (a) (ii)
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Some of the transistor biasing circuits used are
1) Fixed Biased circuit
2) Base biased with collector feedback
3) Base biased with emitter feedback
4) Voltage (or potential) divider
5) Emitter biased
ID (mA)
ID (mA)
5
4
2
IDSS
A
D
ã
C1
VGS = 0V
2V
3V
4V
dy
1
1V
B
â
al
3
ä
VGS = 0V
5
10
15
208
250
VDS
O
VP
VDS
Vi
The regions of operation are shown in characteristics drawn for VGS = OV.
1) Ohmic region OA : ID v/s VDS and obeys ohm’s law.
2) Pinchoff or saturation region BC : ID remain constant at maximum value
even though VDS is increased. Current ID in this region is given by
schockly’s equation
2
 V 
ID IDSS  1  GS 
VP 

3) Breakdown region CD : ID starts increasing very rapidly due to
breakdown of gate to source junction due to avalanche effect. This
region of operation should be avoided to reduce damage to JFET.
1. (a) (iii) Multi-Stage Amplifier
A circuit in which number of single stage amplifiers are connected in cascade
(in series) such that output of the previous amplifier is connected to the input
of the next amplifier is defined as multi-stage amplifier.
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1013/SY/Pre_Pap/Elec/EDC_Soln
Prelim Question Paper Solution
A single stage voltage amplifier is not capable of giving too large voltage gain.
Sometimes input signals are very weak, in such cases they are required to be
amplified more. For this purpose multi-stage amplifiers are used.
1. (a) (iv) Intrinsic stand-off ratio () is one of the important characteristics of UJT
and given by
rB
 = 1
rBB I  0
E
rB1  rB2
r
=
rB1
IE  0
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It is defined as the ratio of internal resistance between B1 and E to the total
internal resistance between 2 base terminals provided emitter current IE = 0.
The value of is given by 0.5 <  < 0.8 and typically  = 0.65 or o.7.
B2 (Base 2)
E
(Emitter)
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1. (a) (v) UJT
i) From the construction it is clear that the
device has one (uni) P  N junction.
ii) Like transistor it is 3 terminal device.
The terminals are known as Base 1,
Base 2, Emitter.
Due to the above 2 reasons it to called unijunction transistor.
B1(Base 1)
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1. (a) (vi) Barkhausen Criterion
For an oscillator the input voltage Vs is absent i.e. Vs = 0 and the feedback
signal Vf is supposed to maintain the oscillations. Therefore substitute Vs = 0
into Equation (5) to get,
Vi(1  A ) = 0
or
A=1
Vi



This condition must be satisfied in order to obtain sustained oscilations.
With an inverting amplifier introducing a 180 phase shift between Vi and
Vo, the feedback network must introduce another 180 phase shift to
ensure that Vi and Vf are in phase.
These two conditions which are required to be satisfied to operate the
circuit as an oscillator are called as the "Barkhausen criterion" for
sustained oscillations.
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Vidyalankar : S.Y. Diploma  EDC
1. (a) (vii) Depending upon the type of 3 semiconductor regions used, transistor is
classified into following 2 types. Their symbols are also given.
Transistor
1) NPN
2) PNP
P
(a) Structure
E
P
C
N
B
B
(b) Symbol
Collector
Emitter
Base
C
P
r
(b) Symbol
N
Emitter
Collector
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(a) Structure
E
N
Base
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1. (b) (i) Comparison between ve feedback and +ve feedback
+ve feedback
ve feedback
1) VIN and Vf are in
VIN and Vf are 180
Veff
phase hence
VIN out of phase hence
effective input
Vf effective input
voltage increases
voltage decreases.
Vf
Voltage gain decreases
Av
Afb =
1  A v
Distortion decreases.
Noise in the output signal
decreases.
Stability of amplifier improves since
Afb remains constant because it
becomes independent of transistor
parameter.
It is used in amplifiers.
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2) Voltage gain increases
Av
Afb =
1  A v
3) Distortion increases.
4) Noise in the output signal
increases.
5) Circuit becomes unstable, starts
oscillating and produces new
output signal of different frequency.
VIN
Veff.
6) It is used in all oscillators.
+VDD
Vi
1. (b) (ii) Voltage at the gate terminal VG =  IGRG but IG = 0
 RIN of JFET very high.
 VG = 0
Now Vs = VG  VGS =  VGS
V
V
By Ohm’s law ID = S  GS
IG = 0
RS
Rs
 VGS = IDRs
Thus voltage drop across Rs reverse biases
gate to source PN junction.
V
 IDQ  GS
… (i)
RS
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1013/SY/Pre_Pap/Elec/EDC_Soln
ID
VD
VG
VDS
VGS
RG
RD
VS
RS
ID
Prelim Question Paper Solution
A graph can be plotted (straight line) between ID and VGS. On the same
graph, transfer characteristics is plotted and as shown Q point can be
selected in the centre by selecting proper value for Rs.
ID
Similarly applying K.V.L. to the output we get
 Allvoltages0
 + VDD  IDRD  VDS  IDRs = 0
 VDD  IDQ (RD + RS) = VDSQ
IDSS
Q
… (ii)
VGS
VGS (OFF)
Equations (i) & (ii) establish Q point.
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This is one of the best biasing network for JFET and is used because of the
following reasons.
(1) Uses only one d.c. supply + VDD
(2) Requires few component
(3) Q point is stable because of following two reasons.
(i) Q point independent of FET parameter.
(ii) Due to negative feedback introduced by voltage drop IDRS. Assume
that due to temperature variation, ID increases. This increase voltage
drop IDRs. Now VGS =  IDRs & hence reverse bias on gatesource
junction increases. This reduces ID and is brought back to original
value. Exactly reverse action takes place if ID decreases. Hence due
to this negative feedback ID and Q point remains stable.
1. (b) (iii) Input characteristics : IE v/s VEE
V
CB  constant
IE (mA)
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VCB = +2 V
10
VCB = 0V
8
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6
4
Scale :
Xaxis : 1 cm = 0.1 V
Yaxis : 1 cm = 2 mA
2
0.1
0.3
0.5
0.7
0.9
VEB (Volts)
Vi
1) Transistor is working in active region hence its input PN (BE) junction
is forward biased. Hence the input characteristics is exactly identical to
forward characteristics of PN junction.
2) By convention, VEB and IE are negative but the curve is plotted in 1st
quadrant.
3) characteristics are plotted by keeping output voltage VCB constant.
Hence 2 curves are plotted by keeping VCB = 0 & then VCB = 2V as
constant.
4) As VCB increases in positive direction then the curve shifts slightly
towards left since less input voltage is now required for sending same
input current.
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Vidyalankar : S.Y. Diploma  EDC
+VCC
2. (a) Voltage Amplifier
RS
+
VS
i/p

VIN
Voltage
Amplifier
AV
VO o/p
RL
Wave form :
VIN
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RIN
RO
AV = voltage gain of the amplifier
RIN = input resistance of the amplifier
RO = output resistance of the amplifier
VS = A.C. signal from function (or signal) generator VO > VIN without distortion
t
an
VO
t
Vi
dy
al
Requirements of good voltage amplifier :
i) Voltage gain (AV) : It should be as high as possible or It must be sufficient
which depends upon the application.
ii) Input resistance (RIN) : It is measured in ohms. Ideally it must be infinite,
practically it must be as high as possible. This avoids the loading
(decreasing) of input signal.
iii) Output resistance (RO) : It is measured in ohms. Ideally it must be zero,
practically it must be as low as possible. This avoids the loading (decreasing)
of the voltage signal present at the output terminals.
iv) Frequency response (or Band  width) : It is measured in Hz or KHz or MHz.
Ideally it must be infinite, practically it must be sufficient for the required
application. Basically Band  width represents the range (group) of
frequencies which are amplified properly by the amplifier.
v) Distortion : It must be as low as possible. If the shape of the amplified output
voltage V0 is different from the shape of input voltage then we say distortion
is present. This must be avoided in any amplifier.
vi) Stability : This must be good so that Q point remains stable in the centre of
active region under D.C. conditions.
2. (b) Comparison between 3 configurations of transistor
Parameter
Common Base
Common Emitter Common collector
1) Input
Lowest  25
Medium  1k
Highest = D.C  RE
impedance
2) Output
Highest  1M
Medium  50k to
Lowest = RE/D.C.
Impedance
100k
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1013/SY/Pre_Pap/Elec/EDC_Soln
Prelim Question Paper Solution
100 < D.C. < 500
(D.C. + 1) Highest
high
4) Voltage gain High
Highest
Less than 1 lowest
5) Power gain Moderate
Highest
Medium
6) Leakage
ICBO = ICO lowest 5 A ICEO = D.C.ICBO High ICEO High 500A for
current
500A for Ge, 20A Ge, 20A for Si
for Ge, 1A for Si
for Si
7) Phase shift 0 (In phase)
180
0 (In phase)
(out of phase)
8) Cut-off
High
Lower than CB
Depends upon load
frequency
9) Thermal
High
Low
High
stability
10) Applications For high frequency
For audio frequency For impedance
matching as a
buffer.
2. (c) Controlled Series Voltage Regulator
+
VS

an
+
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3) Current gain D.C  1 lowest
Control Element
Error Amplifier
Comparator
Sampeling
Network
V0
(Regulated)
RL
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VIN
(D.C.)
unregulated
Reference voltage

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Important blocks and their functions are :
i) Reference voltage : Properly reverse biased zener diode is used as
constant D.C. reference voltage.
ii) Sampeling network : Two resistors are connected as potential divider
across the output terminals for sampeling the output voltage.
Vi
iii) Comparator : Opamp or transistor compares the actual sampled output
voltage with constant reference voltage. The difference between them
known as error voltage is present at its output.
iv) Error Amplifier : It amplifies the error voltage given to it. This is now used as
control voltage to adjust the voltage drop across control element. Normally in
most of the circuit same transistor or same opamp is used as both comparator
and error amplifier.
v) Control element : A transistor in active region is working as emitter follower.
This transistor is working as a variable resistance. The voltage drop VS
across it is automatically adjusted by control signal till error voltage becomes
zero. Due to this V0 is kept constant under all conditions.
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Vidyalankar : S.Y. Diploma  EDC
2. (d) There are 4 types of ve feedback amplifier :
1) Voltage series
2) Voltage shunt
3) Current series
4) Current shunt
1) Voltage series ve feedback amplifiers
+
Vf
+

Vf
+
Amplifier
Av
+ Feedback network


RL
V0

(a) RIN 
(b) R0 
r

Vid
+
V0
ka
+
VIN


Fig. (a)
2) Voltage shunt

Vf
+
Amplifier
Av
an
+
VIN
RL
V0
+

(a) RIN 
(b) R0 
+
+ Feedback network
V0

Vf
al
Fig. (b)
3) Current Series
Vid

+

dy
+
VIN

Vf
Vf
+ Feedback network


Vi
4) Current Shunt
+
VIN


Vf
+
+

v0

(a) RIN 
(b) R0 
+

Fig. (c)
Feedback
Network 
Fig. (d)
1013/SY/Pre_Pap/Elec/EDC_Soln
RL
+
Amplifier
Av
Vf
60
+
Amplifier
Av
RL
+

V0

(a) RIN 
(b) R0 
Prelim Question Paper Solution
Note :
(i) An ammeter is connected in series while voltmeter is connected in parallel.
(ii) Hence at the output if it is parallel connection then it is voltage feedback and
if it is series connection then it is current feedback.
(iii) Similarly at the input if it is series connection then it is series feedback and if
it is parallel connection then it is shunt feedback.
(iv) If 2 resistors are connected in series then RS increases.
(v) If 2 resistors are connected in parallel then RP decreases.
2. (e) (a) UJT relaxation oscillator
Circuit diagram
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+VBB
R
R2 = 150
VB2
B2
VE = VC
UJT = 2N246 or 2N2647
+

VE = VC
R1 = 47
A
al
(b) Waveforms
VB1
B1
an
C
VBB + 0.7= Vp
B
Vv
dy
0
VB1
Vi
Ts > > Tr
Ts
Tr
t
t
VB2
+VBB
t
VB1 positive pulses are used for triggering S.C.R.
Working : At the start (t = 0) when d.c. supply of VBB volts is given to the circuit,
there is no charge on capacitor and hence VC = VE = 0. This is anode of internal
P – N junction which is at 0 volts. Due to internal potential divider of UJT, the
cathode voltage VK of P-N junction is given by Vk = VBB where  = Intrinsic
stand-off ration = 0.7. Since VA < Vk, internal P-N junction is reverse biased and
hence UJT remains off.
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Vidyalankar : S.Y. Diploma  EDC
2. (f) D.C. amplifier
RC
VIN
VO
(or AV)
RC'
Q1
R2
Frequency response
+VCC
Vmax
Q2
VO
0.707 Vmax
an
R1
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OFF UJT acts like open switch and allows capacitor C to charge towards +VBB
through variable resistor R. VC = VE now starts increasing exponentially and
when VE = (VBB + 0.7) = VP then internal P-N junction is forward biased and
starts conducting. UJT is now switched on and the charged capacitor starts
discharging through ON UJT and resistor R1. VC = VE starts decreasing
exponentially and when VE = Vv valley voltage, UJT goes automatically off.
OFF UJT once again acts like open switch and allows capacitor to charge. The
entire waveform (O-A-B) respects itself thus producing continuous periodic
sweep voltage oscillations.
In the above circuit charging time constant = R  C
While discharging time constant = R1 C
Since R > > R1, we get Ts > > Tr which is the condition required for sweep voltage.
Bandwidth
RE
RE
fH
f
al
To improve the low frequency response, all the capacitors in the circuit are
removed. Hence output of 1st stage (i.e., collector of TR1) is directly connected to
the base of TR2. No coupling network is used and hence it is known as direct
coupled amplifier.
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This is the only amplifier capable of amplifying very low f A.C. signal as well as
D.C. signal of zero frequency and hence it is called A.C. amplifier. Though it is
mainly used for amplifying D.C. signal of zero frequency, it is also used for
amplifying A.C. signal upto fH which is sufficiently high compared to audio
frequency of 20 kHz.
Vi
3. (a) Comparison between voltage amplifier and power amplifier
Voltage Amplifier
Power Amplifier
Amplifies power & power gain.
1) Amplifies voltage & voltage gain.
V
P
Av = O
Ap  0
VIN
PIN
2) Small signal amplifier. VIN in mV.
Large signal amplifier. VIN in volts.
3) Class A amplifier.
Class B or Class C amplifier.
4) Distortion low.
Distortion high.
5) Physical size of transistor used is
Physical size of transistor used is
small and has plastic package.
large and has metal package.
6) D.C. > 100
20  D.C  50
7) Collector current 1 to 5 mA.
IC > 100 mA
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1013/SY/Pre_Pap/Elec/EDC_Soln
Prelim Question Paper Solution
11) Heat sinks not required.
3. (b) Thermal run-away
Normally transformer coupled or
direct coupled.
Heat sinks must be used with power
transistor.
Excellent impedance matching.
Power transistor used SL100SK100,
AC187AC188, 2N3055.
It has thick base to handle large
current.
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12) Impedance matching poor.
13) Transistor used BC 147, 148, 547,
548. 549.
14) Transistors have thin base since it
handles low current.
PAC > 1 watt
Output impedance low  200
r
8) A.C. output power is low in mW.
9) Output impedance is high 10 k to
12k
10) Normally RC coupled.
Thermal runaway
Temp. 
ICBO 
an
PDC = VCE  IC 
ICEO 
IC 
i)
PD.C.  VCE  IC
Temp.  PD.C.
iv) ICEO  100 ICBO
al
iii) ICBO  Temp.
v) IC = IB + ICEO
ii)
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When D.C. voltage is applied to transistor, collector current IC starts flowing. This
produces voltage drop VCE on the transistor.
IC
VCE
PDC = VCE Ic
Vi
Due to this D.C. power is dissipated in Transistor and its temperature increases.
This increases ICBO and since ICEO = 100 ICBO and IC= D.C. IB + ICEO, both ICEO and
IC increase. This again increases PD.C. and temperature of transistor. This is a
closed cycle due to which temperature of transistor continuously goes on
increasing.
“The damaging of a transistor due to continuous rise in its temperature is defined
as the thermal runaway”.
It can be avoided by
(i) Selecting proper transistor biasing circuit.
(ii) By using transistor biasing stabilization circuits.
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Vidyalankar : S.Y. Diploma  EDC
3. (c) Multi-stage amplifier
st
+
VS
nd
1
Amplifier
V1

th
2
Amplifier
V2
A V1
n
Amplifier
V3
A V2
Vn
Vn + 1 = V0
RL
A Vn
Let A V1, A V2 , ........ ,A Vn be the voltage gains of each amplifier connected in
V
V2
V
V
V
; A V2  3 ; A V3  4 ; ...... ; A Vn1  n ; A Vn  n1 and over-all
V1
V2
V3
Vn1
Vn
voltage gain A V 
VO
. Multiplying individual voltage gains of each amplifier, we get
VS
an
Hence, A V1 
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cascade. A.C. input voltage VS to be amplified is given to the input terminals of
1st amplifier. The output voltage VO is taken across RL connected to the output
terminals of nth amplifier. By definition of voltage gain, we have
output voltage
AV =
input voltage
A V1  A V2  A V3  .....  A Vn1  A Vn =
Vn1
But Vn + 1 = VO and V1 = VS
V1
al
=
V2 V3 V4
V
V
V


 .....  n1  n  n1
V1 V2 V3
Vn1 Vn
=
VO
= AV
VS
Hence AV = A V1  A V2  A V3  .....  A Vn .
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Hence overall voltage gain AV of multi-stage amplifier is obtained by multiplying
the voltage gains of individual amplifiers connected in cascade.
Vi
3. (d) (i) Voltage regulation or Load regulation
Let VNL = output D.C. voltage at no load (open circuit)
VFL = output D.C. voltage when full rated load current is flowing
 V  VF.L. 
Then % of V.R. = % of L.R. =  N.L.
  100
VF.L.


It is defined as the ratio of change in D.C. output voltage when load current
changes from 0 to full rated load, to the D.C. output voltage at full load.
Ideally its value should be zero and practically it must be as low as possible.
(Note : Since the change in V0 is produced due to change in load current, it
is known as voltage regulation or load regulation).
(ii) Line (source) regulation
Let VHL = Load (output) D.C. voltage with high line (A.C.) voltage
VLL = Load (output) D.C. voltage with low line voltage
VN = Normal D.C. output voltage.
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1013/SY/Pre_Pap/Elec/EDC_Soln
Prelim Question Paper Solution
 V  VN.L. 
Then, % of S.R. =  H.L.
  100
VN


It is defined as the change in output D.C. voltage to the change in A.C. input
voltage and is expressed in mV or percentage of output voltage.
Ideally it should be zero and practically as low as possible.
It is
r
(iii) Ripple Rejection
It denotes the regulators ability to reject unwanted ripple voltage.
normally expressed in dB.
 Vripple(output) 
Ripple rejection in dB = 20log10 
 Vripple(input) 


an
(iv) Output impedance (Z0)
V0
Z0 =
IL
ka
It is defined as 20 times the common logarithm of voltage ratio obtained by
dividing A.C. ripple voltage at the output of regulator to the A.C. ripple
voltage at the input of regulator.
Ideally it should be zero and practically as small as possible.
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It is defined as the ratio of incremental change in output D.C. voltage V0, to
the incremental change in output load current IL. It is measured in ohms.
Z0 should be as small as possible. Since when IL flows through it a voltage
drop IL Z0 is produced on it. The final D.C. output voltage reduces by this
amount which should be ideally zero (i.e., Z0 = 0)
Z0 can be reduced by
1) Using transistor as emitter follower.
2) Using ve feedback in the circuit
dv c
i.e. it is defined as the rate of change of sweep voltage
dt
w.r.t. time. For sweep voltage to be linear then sweep speed must be constant.
For this constant current charging of capacitor is used
1
I
where
vc =
i dt =
dt
C 
C 
It

vc =
C
dv c
I

=
= constant
C
dt
There are 3 types of errors which can be present in a sweep voltage.
1) Slope or sweep speed error (es)
2) Displacement error (ed)
3) Transmission error (et)
Vi
dy
3. (e) Sweep speed =
1) The slope or sweep speed error (es)
Difference in slope at beginning and end of sweep
es =
Initial value of slope
1013/SY/Pre_Pap/Elec/EDC_Soln
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Vidyalankar : S.Y. Diploma  EDC
For ideal linear sweep, the slope remains same because it is a straight line
and hence es = 0 for ideal sweep.
Voltage
2) The displacement error (ed)
Vs  Vs
Instantaneous value of actual
vs
sweep voltage
v s
v s = Instantaneous value of linear sweep
voltage
Vs = Maximum value of actual sweep
t
TS
voltage
(v s  v s )max
. Thus it is defined as the ratio of maximum
Then ed =
Vs
difference between the actual sweep voltage and the linear sweep voltage to
the maximum value of actual sweep voltage.
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vs =
3) The transmission error (et)
VS = Actual sweep voltage
Vs = Linear sweep voltage
an
Without RC network
VS
VS
al
Normally RC coupling network is
used at the output due to which
transmission error is introduced.
Vs  Vs
Transmission error et =
Vs
t
TS
dy
It is defined as the ratio of difference between uncompensated output and
compensated output to the uncompensated output.
3. (f)
A
8mV
2V
RL = 1K
+
Vin
8K
Vi

Vf
2K
(a) By potential divider formula
 R1 
Vf = 
  V0 =
 R1  R2 
66
 Vf =
0.2 V0
=
 Vf =
0.2  2
0.4 volts
1013/SY/Pre_Pap/Elec/EDC_Soln
8k
+
 2 

  V0
28
Vf
…(1)
=
0.4 volts
[  V0 = 2V]
2k
R
V0

Prelim Question Paper Solution
(b) From equation (1) Vf = 0.2 V0
Hence feedback factor  = 0.2
V0
where V0 = 2  103 mV and Vid = 8 mV
Vid
(d) Afb
=
A
1  A
=
2  103
8
250
1  250  0.2
4. (a) Class B push-pull amplifier
Circuit Diagram
V1 =
+
= 250
=
=A
250
51
= 4.902
r
 Open loop gain, A =
ka
(c) A =
But Vf =  V0
Q1
iC1
ICQ
N1
VCC
+
 C.T.
+
+ C.T.
an
VIN


Output transformer
N2
Speaker
8
output
N1

Q2 iC2
ICQ
al
V2 =
Vi
dy
Working : The two NPN power transistors are connected in push-pull, i.e., when
one transistor is ON the other is OFF and vice-versa. Emitters of both transistors
are connected to ground while base of both transistors is connected to ground
through centre tap secondary of driver transformer. A.C. input voltage VIN to be
amplified is given to the primary of driver transformer. Its centre-tapped
secondary is used for producing two equal and opposite signals V1 and V2 which
are given to the base of both transistors. Similarly, collectors of both transsitor
are connected to the primary of output transformer. A +VCC D.C. supply is given
to the centre top of primary. Speaker of 8 is connected to the secondary of
output transformer. The turns ratio N1 : N2 is adjusted for proper impedance
matching.
2
N 
RL   1   RL [RL  8]
 N2 
When A.C. input signal VIN is not given then both Q1 and Q2 are in cut-off because
base and emitter of transistors is at O D.C. volts. As shown above V1 is in phase
with and V2 is output of phase with A.C. input signal VIN. For the first +ve half cycle
of VIN, the ve half cycle of V2 drives Q2 more into cut-off while +ve half cycle of V1
drives Q1 into conduction when V1 becomes + 0.7 volts. Similarly for the next half
cycle Q2 conducts and Q1 is driven into cut-off.
1013/SY/Pre_Pap/Elec/EDC_Soln
67
Vidyalankar : S.Y. Diploma  EDC
Q1 thus produces 1st half cycle while Q2 produces 2nd half cycle. These are
transferred to speaker by output transformer and hence both the half cycles are
produced at the output, thus reducing distortion.
4. (b) Comparison between BJT and JFET
2)
Device type
3)
Input junction
4)
Input resistance
5)
Thermal stability
Thermal Noise
GainBandwidth
product
8) Switching speeds
9) Cutoff frequency
10) Size
FET
Voltage controlled device.
Input voltage VGS controls
output current ID.
Unipolar : Current flow
due to majority carriers
only
GS junction is reverse
biased.
Very high of the order of
several M.
More hence thermal
runaway not present
Less noisy
Low
High
Low
Bigger than JFET less
suitable for I.C. fabrication
Low
High
Smaller and hence more
suitable for I.C.
fabrication.
(a)
al
an
6)
7)
BJT
Current controlled device
input current IB controls
output current IC
Bipolar : Current flow due to
both majority and minority
carriers
BE junction is forward
biased
Very low compared to JFET
of the order of few K.
Less hence thermal runaway possible.
More noisy
High
r
Parameter
Control Element
ka
1)
(a)
dy
NPN
11) Type and symbols
Vi
B
E
(b)
PNP
12) Application
C
D
N  Channel
G
S
(b)
C
D
P Channel
B
E
Low frequency amplifiers
and oscillators
G
N
(1) High f application
(2) Impedance matching to
avoid loading effect
4. (c) CROSSOVER DISTORTION
For class B operation base and emitter of power transistors are kept at 0 volt
D.C. Hence when A.C. input signal are not given both the transistors are in cut
off region.
68
1013/SY/Pre_Pap/Elec/EDC_Soln
Prelim Question Paper Solution
VIN
+0.7 V
t
0.7 V
VO
r
t
crossover distortion
ka
A silicon transistor requires + 0.7 V (for NPN transistor) and 0.7 V (PNP
transistor) w.r.t. emitter to conduct. Due to this only when a.c. input signal
reaches  0.7 V, then only the two transistors start conducting. As shown above,
when VIN   0.7V, then two transistors do not conduct resulting in the distortion
of output signal. This distortion occurs whenever A.C. signal is crossing from +ve
to ve or ve to +ve cycle and hence it is known as crossover distortion.
an
This can be avoided by using class AB power amplifier. Q point is selected
slightly in active region due to which transistor conducts for slightly more than
half cycle thus avoiding crossover distortion.
al
4. (d) Since  < 1. Normally  = 0.7
and
C = 0.1  106 F
R = 10 k = 10  103 
 1 
By formula
T = RCloge 

 1  
1
1 
Hence loge (3.33)
1
1 0.7
= 1.203
=
=
1
0.3
dy
Now


= 3.33
T
= 10   0.1 10 6  1.203
f
=
f
1
1
=
T
1.203  10 3
= 831.95 Hz
= 1.203  10 3 sec
=
Vi
Now put IE = IC + IB
 IC = D.C. (IC + IB) + ICO
= D.C.IC D.C.IB  ICO
=
1000
1.202
C
4. (e) For common emitter configuration
The exact relation between output current IC
and input current IB is given by
…(i)
IC = DC IB + ICEO
Similarly for common base configuration
The exact relation between output current IC
and input current IE is given by
[ICO or ICBO]
IC = D.C. IE + ICO
103
1.202
IC
B
IB
E
E
IE
C
IC
B
1013/SY/Pre_Pap/Elec/EDC_Soln
69
Vidyalankar : S.Y. Diploma  EDC

IC  D.C.IC  D.C.IB  ICO

(1  D.C. )IC  D.C.IB  ICO
I
  
…(ii)
IC 
IB  CO

1 
 1  
Companies equations (i) & (ii) we get

 1 
=
and ICEO  
 ICO
1 
 1  

Now by formula  =
 1
1 
1



 ICEO  
I =
I   1 ICO
  CO    1    CO
 1



   1
  1 
But normally 100 <  < 500. Also neglecting 1 we can write  + 1  100
 ICEO = 100 ICO
Hence reverse leakage current in common emitter is 100 times greater than
the reverse leakage current in common base configuration.
an
ka
r

al
4. (f) RC Phase Shift Oscillator using Transistor
 A typical RC phase shift oscillator using transistor as an active device is
shown in figure 1.
 The Circuit consists of a single stage amplifier in C.E. configuration and the
RC phase shifting network.
 The resistors R1, R2 and RE are connected for transistor biasing CE is the
emitter bypass capacitor.
Vi
dy
Operation :
 As shown in figure 1 the output
Vo of the single stage CE
amplifier has been connected as
an input to the RC phase
shifting network.
 The output of the phase shifting
network is connected at the
input of the amplifier.
 As the amplifier is C.E. type, it
introduces a phase shift of 180
between its input and output.
The phase shifting network will
introduce an additional 180
phase shift to make the phase
shift around the loop equal to
zero.

70
Fig. 1 : RC phase shift oscillator
using transistor
The phase shift around the loop will be precisely equal to 0 only at one
frequency "f" which is the frequency of operation. If the gain of the amplifier
1013/SY/Pre_Pap/Elec/EDC_Soln
Prelim Question Paper Solution


r

ka

and feedback factor  are adjusted properly to have a loop gain |A|  1 the
sustained sinusoidal oscillations will be obtained at the oscillator output.
Note that the RC feedback network of figure 1 is slightly different from the
one we have discussed in section 6. The resistance R3 of Figure 1 is
selected in such a way that,
R3 + Zi = R
... (1)
where,
Zi = Input impedance of the CE amplifier. It is given by,
Zi = hie || (R1 || R2)
But as R1 and R2 are large enough. We can neglect them. Hence,
Zi  hie
Substituting this value into Equation (1) we get,
R3 + hie = R or
R3 = R  hie
... (2)
And if we do not neglect the resistors R1 and R2 then the value of R3 is given by,
R3 = R  [R1 || R2 || hie]
... (3)
5. (a) Av = open loop voltage gain;
Afb = Closed loop voltage gain;
Av
1 A v
an
 = feedback factor then by formula Afb =
al
Now   1 i.e. normally  is always less than 1 and its maximum value can be
only one. But the open loop voltage gain Av is very high and hence Av >> 1.
Neglecting 1 in the denominator we get
A
1
Afb = v =
A v 
dy
Thus closed loop gain Afb is equal to the reciprocal of feedback factor .
In ve feedback amplifiers only resistors are used whose values are fixed once
R1 

they are selected.  = Ratio of these resistors   
 which is constant.
R
1  Rf 

Thus Afb remains constant and is independent of the parameter of the transistor
(a.c or hfe). Because of this reason, stability of voltage amplifier improves when
ve feedback is used.
5. (b) Comparison between series and parallel resonant circuit
Parameter
Circuit
Vi
1)
Series Resonant Circuit
R
L
Parallel Resonant Circuit
R
C
L
i.e. R, L and C are in series.
C
i.e. coil and C are in parallel.
2)
f0
f0 =
1
2 LC
1
1
R2
1
 2 
2 LC 4L
2 LC
where R  0 and can be
neglected.
f0 =
1013/SY/Pre_Pap/Elec/EDC_Soln
71
Vidyalankar : S.Y. Diploma  EDC
Zeff
7)
I0
8)
Q0
Zeff = R and is minimum
max. at f0 and I0 =
0L
1
1 L


0RC R C
R
and is known as voltage
magnification factor
At f0, VL = VC = Q0 VIN i.e. i.e.
VL and VC are more than VIN.
Q0 =
9)
10) Resonance
Curve
VIN
R
p.f. = cos  = 1
BL = BC at f0
B = Susceptance
L
Zeff =
and is maximum
RC
VIN
RCVIN
=
I0 =
L / RC
L
and is minimum
r
6)
Parallel Resonant Circuit
Phase angle  = 0 at f0.
0L
1
1 L


0RC R C
R
and is known as current
magnification factor.
At f0, IC = Q0 IT i.e. IC is more
than IT.
I
Q0 =
ka
4)
5)
Parameter
Series Resonant Circuit
Phase angle  = 0 i.e. ‘I’ and

Vin are in phase at f0.
p.f.
p.f. = cos  = 1
Reactance XL = XC at f0
X = reactance
V0
an
3)
Vmax
0.7 Vmax
al
B.W.
f1
B.W. =
f0
Q0
dy
11)
Vi
5. (c) Circuit diagram :
VIN
2V
p to p
f
f0 f2
f0
B.W. =
N1
f0
Q0
Speaker
+VCC
R1
f
N2
RL = 8
CIN
Output transformer
+
R2

RE
CE
2
N 
RL   1   RL
 N2 
72
1013/SY/Pre_Pap/Elec/EDC_Soln
where RL is the impedance transferred to primary side.
Prelim Question Paper Solution
Working : The resistors R1 and R2 are voltage divider biasing network which
establishes Q point in the centre of a active region. RE stabilizes the Q point.
By-pass capacitor CE by-passes A.C. output signal from the emitter. This
removes ve feedback which improves the gain of the amplifier. Input capacitor
CIN blocks D.C. voltage and allows A.C. input voltage VIN to pass to the base of
transistor.
r
The collector resistor RC is replaced by the primary winding of output transformer.
Its resistance is very small which reduces power losses in it thus improving
power efficiency. The maximum  improves from 25% (for RC) to 50% (for
transformer coupled).
2
ka
The transformer gives good D.C. isolation as well as impedance matching.
Speaker impedance of 8 (RL) on secondary side is transferred to RL on primary
an
N 
side, where RL   1   RL . Hence by using step-down (N2 < N1) transformers,
 N2 
impedance of speaker is matched to the output impedance of amplifier. Due to
this maximum power is transferred to the loud-speaker.
dy
al
5. (d) Advantages :
(i) Bandwidth of the amplifier increases (B.W.)new = (1 + Av)(B.W.)old
(ii) (Amplitude, frequency, phase harmonic) distortion of the amplifier reduces.
Dold
D0 (new) =
(1  A v)
(iii) Noise signal in the output reduces.
N0(old)
N0(new) 
1  A v
(iv) Stability of the amplifier improves due to which voltage gain becomes
independent of transistor parameters and hence it remains almost constant.
(v) (a) RIN for voltage amplifier should be high.
(b) R0 of voltage amplifier should be low.
By using voltage series ve feedback amplifier, RIN increases and R0 decreases.
RIN(new) = (1 + Av) RIN(old)
R0(old)
Vi
RO(new) =
1  A v
Disadvantages :
The only disadvantage is that voltage gain of the amplifier decreases
Av
Afb =
1  A v
But if more voltage gain is required then multistage amplifiers with ve feedback
can be used.
1013/SY/Pre_Pap/Elec/EDC_Soln
73
Vidyalankar : S.Y. Diploma  EDC
VIN
+


Vf
+
Vid
+

Vf
+
Voltage Amp.
Av
Feedback network

RL

ka
By definition of feedback factor  
Vf
hence Vf   v 0 .
V0
Putting this value in
an
above equation we get
VIN   v0 = vid

+
V0
Applying K.V.L. at the input of the amplifier
We get
 All voltages = 0

+VIN  vid  vf = 0

VIN  Vf = vid.
V0
r
5. (e)
…(1)
v
By definition of open loop voltage gain AV = 0
v id


from equation (1)
dy

v0 = AV vid
v0 = AV (vIN  v0)
= AV vIN  AVv0
V0 + AV  v0 = Av vIN
V0 (1+ Av ) = Av vIN
v0
AV
=
VIN 1  A V
al

But by definition
v0
 A fb  closed loop voltage gain.
VIN
Av
1 A v
In the above expression denominator > 1.
Hence Afb < Av i.e. voltage gain of the amplifier reduces when ve feedback is
used.
Afb =
Vi
Hence
5. (f) I.C. 723 is basically a series voltage regulator. Its important blocks and their brief
description is given below :
i) Voltage Reference Amplifier : A temperature compensated 6.2 V zener is
biased with a constant current source. An op-amp A1 is used as a buffer
amplifier which provides reference output voltage of 7.15 V which is capable of
supplying current upto 15 mA.
ii) Comparator and error amplifier : Op-amp A2 is working both as
comparator and error amplifier. The reference output (or fraction of it) is
given to the non-inverting input terminal. Similarly the output voltage V0 (or
74
1013/SY/Pre_Pap/Elec/EDC_Soln
Prelim Question Paper Solution
fraction of it) is given to the inverting input terminal of op-amp A2. These two
voltages are compared with each other and the difference between them
known as error voltage is produced. This error voltage is amplified by opamp A2 and is available at its output as control voltage.
Frequency
compensation
V+
A1
Q2
A2
+
V0
Q1
VZ
ka
Constant
current
source
Vref.
Non-inverting
input

r
Inverting
input
Temperature
Compensate
d zener
Booster
terminal
VC
I
C.L.
C.S.
(Current (Current
limit) sense)
V
A2 : Comparator and
Error Amplifier
Current protection
circuit
Output Stage
an
A1 : voltage reference
amplifier
dy
al
iii) Output Stage : It consists of series pass control transistor Q2. The control
voltage at the output of op-amp. A2 is given to the base of Q2. This control
voltage adjusts the voltage drop VCE of Q2 till error voltage becomes zero and
V0 remains constant.
iv) Over-Current protection circuit : Transistor Q1 connected at the output
works as current protection circuit. An external resistor RCL connected
between its base (current limit) and emitter (current sense) fixes the
maximum value of the load current. Under short circuit condition also the
load current does not exceed this value.
v) How to vary the output voltage : A potentiometer R2 is varied to change
the output voltage to the required value. This R2 is connected in potential
divider circuit across output terminals or it is connected to reference output
terminal.
6. (a) Zener Diode in Parallel to RL
Circuit Diagram :
R
A
Vi
S
VIN
IT
IL
IZ
VZ = V0
RL
Equations :
(i) V0 = VZ hence if VZ is constant then V0 is constant.
(ii) By K.C.L. at A , IT = IZ + IL
(iii) By K.V.L.,
 All voltages = 0
 VIN  ITRS  V0  0
1013/SY/Pre_Pap/Elec/EDC_Soln
75
Vidyalankar : S.Y. Diploma  EDC
 V0 = VZ = VIN  IT RS
and
VIN  VZ
VIN  VZ
 RS =
=
IT
IZ  IL
ITRS = VIN  VZ
(iv) Thus by selecting the value of RS properly the condition IZ(knee)  IZ  IZ(max) is
satisfied for all conditions due to which VZ = V0 remains constant.
ka
r
Working :
VIN varying IL constant : It is assumed that RS is so selected that V0 = VZ =
constant.
A
B
1. Assume VIN increases.
Assume VIN decreases.
2. This increases VIN  V0
This decreases VIN  V0
3. IT increases and IT = IZ + IL. But IL is IT decreases and IT = IZ + IL. But IL is
constant since V0 is constant
constant since V0 is constant.
4. IZ increases but IZ < IZ
hence
V
is
IZ decreases but IZ > IZ(knee) hence V0
0
max .
constant
is constant.
an
Conditions necessary for this circuit to work properly are
(i) VIN > VZ, so that zener diode is properly reverse biased.
(ii) Value of RS is so selected that under all conditions; IZ(knee)  IZ  IZ(max .) is
satisfied. Hence zener diode operates in proper breakdown condition and
VZ = V0 remains constant.
al
6. (b) 2 stage transformer coupled amplifier
dy
+VCC
R1
TR3
+
RL
R1'

TR2
TR1
Vi
VS
RE
R2
TR1 : Input transformer
TR2 : Driver transformer
TR3 : Output transformer
76
1013/SY/Pre_Pap/Elec/EDC_Soln
VO
A.C. ground
CE
C1
R2'
RE'
CE'
Prelim Question Paper Solution
Frequency response
Resonant
size
Flat
Low
frequency regio
High
frequency
f0
f
r
V0
(or AV)
ka
A transformer is used for coupling the A.C. signal from previous stage to next
stage. The main advantages of transformer are :
(i) very good D.C. isolation, (ii) very good impedance matching, (iii) resistance of
primary is less hence D.C. losses are less which increases efficiency.
In the above circuit, if A V1 and A V2 are the voltage gains of individual stage then
an
overall voltage gain A V  A V1  A V2 . The functions of each component are given
Vi
dy
al
below.
(i) R1 and R2 are voltage divider biasing network which establishes Q point in
the centre of active region.
(ii) RE stabilizes Q point.
(iii) CE by-passes A.C. signal at the emitter. This removes ve feedback and
improves voltage gain.
(iv) Transformer : (a) Gives D.C. isolation, (b) Provides very good impedance
matching by selecting number of turns of primary and secondary.
(v) C1 : This capacitor provides A.C. ground due to which maximum A.C. voltage
is applied to the 2nd stage.
As shown in frequency response, this amplifier is capable of amplifying one
particular resonant frequency f0. Hence they are used as tuned voltage
amplifiers by connecting capacitors across primary and secondary winding.
These are used for amplifying one particular intermediate frequency in
communication circuits like Radio, TV, etc.
6. (c) The gain of an amplifier is denoted by "A" and A =
output signal
.
input signal
V 

(i) Voltage gain  A V  O  : It is defined as the ratio of output voltage VO to the
V
IN 

input voltage VIN. It is a pure number and has no unit of measurement AV > 1
since VO > VIN.
I 

(ii) Current gain  AI  O  : It is defined as the ratio of output current IO to the
IIN 

input current IIN. It is a pure number and has no unit of measurement AI > 1
since IO > IIN.
1013/SY/Pre_Pap/Elec/EDC_Soln
77
Vidyalankar : S.Y. Diploma  EDC
P 

(iii) Power gain  AP  O  : It is defined as the ratio of output power PO to the
Pin 

input power PIN. It is a pure number and it has no unit of measurement.
Since VO IO = output power PO and VIN IIN = input power
Thus AP = AV  AI
ka
6. (d) (a) Circuit diagram :
(i) Capacitively coupled
(ii) Inductively coupled
+ VCC
C
CIN
VIN
VIN
LP
LS
RL V0
CIN
RL
V0
VIN
+
R2

R
C
al

R2
CP
R1
L
CC
+
+ VCC
an
R1
r
Relation between AV, AI and AP 
Multiplying the values of AV and AI, we get
V
I
V I
P
AV  AI = O  O = O O = O = AP
VIN IIN
VIN IIN
PIN
= Modulated high frequency
(radio frequency) carrier signal
dy
(b) Frequency Response :
Av = voltage gain
(i)
AV = Voltage gain
AV(max.)
Vi
0.7 AV(max.)
B.W.
f1 f0 f2
f
f0
(ii) B.W.
=
=
=
=
Resonant frequency
fIN
carrier frequency
f2  f1
f0
Q0
(iii) B.W.
=
(iv)
Av
=
 AC  rL
Ri
(v)
rL
=
Z eff
=
L
(max.)
RC
Working :
Resistors R1 and R2 are voltage divider biasing network which establishes ‘Q’
point in the centre of active region. RE stabilizes the ‘Q’ point. CE bypasses A.C.
signal at the emitter to the ground. This removes ve feedback due to which Av
increases. Cin and Cc block d.c. voltage and allows A.C. voltage to pass.
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1013/SY/Pre_Pap/Elec/EDC_Soln
Prelim Question Paper Solution
r
In the above circuit Rc is replaced by single tuned (parallel resonant) circuit. Either
L or C or both are variable. Their values are so adjusted (tuned) that resonant
1
frequency f0 
of the tuned circuit becomes exactly equal to incoming
2 LC
signal frequency. At f0, Zeff of parallel circuit becomes maximum and is given by
L
where R = resistance of inductor. As shown above Av  Zeff and hence
Zeff =
RC
voltage gain becomes maximum at f0 as shown in the frequency response.
f
B.W. = 0 and hence as Q0 increases, frequency response becomes more
Q0
narrower and bandwidth decreases. Hence circuit becomes more selective.
ka
Thus the circuit is capable of amplifying one particular high frequency (f0) or a
very narrow band of high frequencies (f2  f1). Since only 1 tuned circuit is used.
It is known as singletuned voltage amplifier. The output voltage can be either
capacitively coupled or inductively coupled.
al
an
6. (e) Advantages :
(i) Maximum power,  = 78.4% which is higher than Class A amplifier.
(ii) Even harmonic components are eliminated.
(iii) More A.C. power output per transistor than Class A.
(iv) D.C. current of both transistor flow in opposite direction in the primary
winding of output transformer. Hence magnetic fluxes produced by them
cancel each other due to which core of transformer does not saturate.
(v) It is possible to eliminate both the transformers which reduces the cost and
improves the frequency response.
Vi
dy
Disadvantages :
(i) Two power transistors are required when increases the cost.
(ii) The two transistors must be a matched pair, i.e., their parameters must be
identical to avoid distortion. This also increases the cost of power transistor.
(iii) Driver stage required for producing two equal and opposite A.C. input
signals.
(iv) Distortion is more than Class A amplifier.
(v) Because of Class B operation, cross-over distortion present.
(vi) Transformers are bulky and occupy more space.
(vii) Cost increases because of 2 transformers.
Note : Since two transformers can be eliminated and A.C. power output is more,
Class B push-pull power amplifier are used maximum.
6. (f) Comparison of class A, B and C power amplifier
Parameter
Class A
Class B
Class C
1) Diagram of A.C. Refer fig. 1(a).
Refer fig. 1(b).
Refer fig. 1(c).
load line.
2) Q-point
Centre of active
On the border of cut In the cut-off region.
region
off and active region
3) A.C. collector Flows for complete Flows for half cycle Flows for less than
half cycle.
current, iC
(0 to 180)
cycle (0 to 360)
1013/SY/Pre_Pap/Elec/EDC_Soln
79
Vidyalankar : S.Y. Diploma  EDC
5)
6)
7)
8)
Flows even if A.C.
input signal is not
given.
25% for RC
Maximum
50% for TX
power, 
(Lowest)
Distortion
Lowest
Output power to Lowest
load.
Cross-over
Not present
distortion
Hum (Noise
Absent
signal)
Does not flow if A.C. Does not flow if A.C.
input signal absent. input signal absent.
78.4%
(Medium)
> 80%
(Highest)
Medium
High
Highest
Highest
Present
Not present
Low
High
ka
9)
D.C. collector
current, IC
r
4)
Vi
dy
al
an

80
1013/SY/Pre_Pap/Elec/EDC_Soln