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MONASH UNIVERSITY
THESIS ACCEPTED IN SATISFACTION OF THE
REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
ON
24 February 2004
Sec. Research Graduate School Committee
Under the Copyright Act 1968, this thesis must be used only under the
normal conditions of scholarly fair dealing for the purposes of
research, criticism or review. In particular no results or conclusion?
should be extracted from it, nor should it be copied or clo:e!y
paraphrased in whole or in part without the written consent of >he
author. Proper written acknowledgement should be made for any
assistance obtained from this thesis.
it
A VSI-BASED POWER QUALITY
CONDITIONER FOR 25KV ELECTRIFIED
I
RAILWAY SYSTEMS
I
By
I
Pee-Chin TAN
B.Sc, Monash University, 1996
B.E. (Horn), Monash University, 1998
Submitted for the degree of Doctor of Philosophy
I
Department of Electrical and Computer Systems Engineering
Monash University
Australia
August 2003
ii
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Ei"^S
TABLE OF CONTENTS
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Table of Contents
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i
List of Figures
vi
List of Tables
xiii
Abstract
xiv
Declaration
xvi
o
Acknowledgements
,
xvii
w
List of Publications
xviii
m
Glossary of Terms
List of Symbols Used
xx
xxii
CHAPTER 1: Introduction
m
II
1.1 Background
1
;
1
v
1.2
Aim of the Research
1.3
Contents of the Thesis
5
'•'•
1.4
Identification of Original Contributions
7
f.
9
f
9
|
11
I
13
j;
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
2.1
25 kV Power Supply Layout
2.2
Thyristor Locomotives
2.2.1
Thyristor Locomotive Control
4
2.3
Power Quality Issuesfor25kV Railway Systems
14
\
2.4
Low System RMS Voltage
16
J
f
2.4.1
Cause and Significance
16
2.4.2
Solutions to Voltage Regulation
17
|;
2.5
Low Average Voltage
20
f'.
2.6
Harmonic Overvoltage
23
;;
2.6.1
Cause and Significance
23
!
2.6.2
Solutions to Harmonic Overvoltage
25
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25
jv
27
|
2.7
Summary
CHAPTER 3:
S T A T C O M s and Active Power Filters
3.1
S T A T C O M Operating Principle
28
I
3.2
STATCOM Topologies and Modulation Strategies
29
I
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0.
3.2.1
Square-Wave Switching
31
M
3.2.2
PWM Switching
34
3.3
STATCOM Control Strategies
36
3.3.1
Outer Control Loop
36
3.3.2
Inner Current Loop
40
3.4
Active Power Filter Overview
41
3.5
Active Power Filter Topologies
43
3.5.1
Shunt Active Power Filter
44
3.5.2
Series Active Power Filter
46
3.5.3
Hybrid Active Power Filter Systems
47
3.6
Active Power Filter Control Detection Methods
52
3.6.1
Load Current Detection Method
53
3.6.2
Source Current Detection Method
56
3.6.3
Voltage Detection Method
57
3.6.4
DC Bus Voltage Detection Method
59
3.7
Active Power Filter Harmonic Extraction Algorithms
63
3.7.1
Instantaneous Reactive Power Method
64
3.7.2
Synchronous Reference Frame Method
67
3.7.3
Various Single-Phase Algorithms
70
3.8
VSI Current Regulation Strategies
74
3.8.1
Linear Current Regulation
75
3.8.2
Predictive Current Regulation
76
3.8.3
Hysteresis Current Regulation
78
3.9
Summary
CHAPTER 4:
80
A New Traction Power Quality Conditioner for 25kV Railway
Systems
82
4.1
Proposed Traction Power Quality Conditioner
83
4.2
Low Order Harmonic Compensation
87
4.2.1
Control Detection Method
87
4.2.2
Harmonic Extraction Algorithm
88
4.2.3
Compensation Performance
95
4.2.4
Gain Considerations
101
4.3
Reactive Power Compensation
109
4.4
DC Bus Voltage Control
109
i
4.5
Summary
CHAPTER 5:
:•-$
#>
|
112
A Robust Multilevel Hybrid Power Quality Conditioner for
25kV Railway Systems
114
5.1
Motivations for Multilevel Hybrid Topology
115
5.2
Review of Multilevel Inverter Topologies
116
|
5.2.1
Diode-Clamped Multilevel Topology
117
m
MI
™
5.2.2
Flying-Capacitor Multilevel Topology
118
5.2.3
Cascaded Multilevel Topology
119
jM
5.2.4
Hybrid (Reduced) Multilevel Topology
119
I
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5.3
Proposed Multilevel Hybrid Traction Power Quality Conditioner
120
5.3.1
Hybrid T-PQC Topology
120
5.3.2
Hybrid T-PQC Control
121
Hysteresis Current Regulation
124
5.4
jl
H
5.4.1
Conventional H-Bridge
125
5.4.2
Reduced Five-Level Inverter
126
5.4.3
Cascaded Five-Level Inverter
128
^
5.5
DC Capacitor Voltage Balancing Issues
130
l|
5.6
Summary
132
CHAPTER 6:
Description of Simulation Systems
133
II
6.1
Description of the PSCAD/EMTDC Simulation Approach
134
1
6.2
Overview of Simulation Systems
135
6.3
Modelling of 25kV Power Supply System
136
6.4
Modelling of Thyristor Locomotives
138
6.5
Modelling of Power Inverters for T-PQC
139
6.6
Modelling of T-PQC Control System
140
6.6.1
Hysteresis Current Regulator
141
6.6.2
DSP Controller
142
6.7
Other Custom Models
144
6.8
Summary
147
CHAPTER 7: Description of Experimental Systems
149
7.1
Overview of Experimental Systems
149
7.2
Modelling of 25kV Power Supply System
151
7.3
Modelling of Thyristor Locomotives
152
7.4
Experimental Power Inverters for T-PQC
154
m
p
m
7.4.1
Single-Phase Two-Level VSI
154
i
7.4.2
Single-Phase Cascaded Five-Level VSI
155
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1
7.5
Experimental T-PQC Control System
157
7.5.1
Hysteresis Current Regulator
157
7.5.2
DSP Controller
159
DSP Software Overview
163
7.6
7.6.1
Interrupt Code
163
7.6.2
Background Code
171
7.7
Summary
172
CHAPTER 8: Simulation and Experimental Results
1
i
174
8.1
Laboratory Instrumentation
174
8.2
Steady State Performance
175
8.2.1
Simulation Results
176
8.2.2
Comparison of Simulation and Experimental Results
184
8.2.3
Comparison of Multilevel and Two-level VSI Compensations
191
8.3
Dynamic Performance
195
8.4
Transient Performance
198
8.5
System Sensitivity Studies
199
8.6
Summary
200
CHAPTER 9: Conclusions
202
9.1
Summary of the Work
202
9.2
Conclusions
204
9.3
Suggestions for Further Research
205
9.4
Closure
206
APPENDIX A: Derivations of Important Results
>
207
A.I
Transformation from Synchronous to Stationary Frame
207
A.2
Voltage Profile on A Lossless Transmission Line
210
A.3
Derivative of |V(x)| with Respect to RL
212
APPENDIX B: MATLAB M-Files
214
B.I
Listing of 'MP6.M'
214
B.2
Listing of 'GAIN2.M'
215
B.3
Listing of'STANDWAVE.M'
217
B.4
Listing of 'HARPROP.M'
217
APPENDIX C: PSCAD Custom Model FORTRAN Source Codes
219
IV
i"5
C.I
Listing of'RMSAVG.F'
219
C.2
Listing of'DIGCTRL5.F'
222
APPENDIX D: DSP Source Codes
229
D.I
Listing of 'HYS.H'
229
D.2
Listing of 'HYSMAIN.C
232
D.3
Listing of'HYSINT.C
248
Bibliography
264
1
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LIST OF FIGURES
Figure 2.1: Typical power feeding arrangement for 25kV electrified
railway systems
10
Figure 2.2: Magnitude of railway system impedance at the end of a 30km
feeder section
11
Figure 2.3: Main power circuit of a Bo-Bo thyristor locomotive
12
Figure 2.4: Simulated waveforms for two 2.5MW locomotives at the end
of a 30km feeder showing (a) Pantograph voltage and (b)
Load current
14
Figure 2.5: Harmonic spectrums for two 2.5MW locomotives at the end of
a 30km feeder, (a) Pantograph voltage (b) Load current
15
Figure 2.6: Locomotive load fed through inductive and resistive
impedances, (a) Simplified circuit diagram (b) Phasor
diagram
17
Figure 2.7: Shunt reactive power compensation
19
Figure 2.8: Main building blocks for conventional SVCs: (a) Thyristorcontrolled reactor (TCR) (b) Thyristor-switched capacitor
(TSC) (c) Fixed Capacitor/Harmonic Filter (FC/HF)
19
Figure 2.9: Effect of harmonic components on the average value of a
waveform
21
Figure 3.1: VSI based STATCOM. (a) Schematic diagram (b) Single-line
equivalent circuit
28
Figure 3.2: Basic two-level VSI topologies, (a) Single-phase H-bridge (b)
Three-phase Graetz bridge
30
Figure 3.3: Principle of sine-triangle PWM generation
35
Figure 3.4: Transmission system STATCOM. (a) Circuit arrangement (b)
Typical outer control loop structure
Figure 3.5: Distribution level, load specific STATCOM. (a) Circuit
37
arrangement (b) Typical outer control loop structure
39
Figure 3.6: Inner current loop for square-wave modulation VSI
40
Figure 3.7: Active power filter compensation scenario
44
Figure 3.8: Shunt active power filter, (a) System configuration (b) Per
phase equivalent circuit
Figure 3.9: Series active power filter, (a) System configuration (b) Per
phase equivalent circuit
Figure 3.10: Shunt hybrid parallel topology with shunt active and shunt
passive elements
45
46
48
VI
i
m
Figure 3.11: Series hybrid parallel topology with series connection of
active and passive elements, (a) System configuration (b)
Per-phase harmonic equivalent circuit as seen by the load
current when vAPF* =K-iSh
49
Figure 3.12: Hybrid series topology with series active and shunt passive
elements, (a) System configuration (b) Per-phase harmonic
equivalent circuit as seen by the load current when
V
M
$
APF'
=K-iSh
52
Figure 3.13: Load current detection, (a) Control schematic (b) Control
system block diagram
54
m
Figure 3.14: Source current detection, (a) Control schematic (b) Control
system block diagram
56
m
Figure 3.15: Voltage detection, (a) Control schematic (b) Control system
block diagram
58
Figure 3.16: DC bus voltage detection method control schematics, (a)
Source current regulation (b) Conventional VSI current
regulation
61
Figure 3.17: Instantaneous reactive power method for generating
compensation current reference
66
Figure 3.18: Synchronous reference frame for generating compensation
current reference
68
Figure 3.19: Different approaches to Ip estimation, (a) No explicit
estimation (b) Rough estimation (c) Estimation using
sample and hold
72
si
m
m
1
61
i
i
Figure
3.20:
Estimation
of
Ip
by
modulation,
(a)
Open-loop
implementation (b) Closed-loop implementation
73
Figure 3.21: Stationary reference frame linear current regulation
75
Figure 3.22: Hysteresis current regulation, (a) Single-phase VSI (b)
Current controller (c) Switching rules
Figure 3.23: Current and voltage waveforms for hysteresis current
78
regulation
79
Figure 4.1: 25kV railway system with proposed power quality conditioner
85
Figure 4.2: Controller block diagram of proposed Traction Power Quality
Conditioner (T-PQC)
Figure 4.3: Single-phase equivalent synchronous reference frame filter
86
90
Figure 4.4: 3 r d , 5th and 7th synchronous frame selective harmonic filter (cos
= system line frequency) suitable for traction applications
92
Figure 4.5: Frequency response of equation (4.10) for coc = 1 rad/s and 10
rad/s
95
Figure 4.6: Distributed parameter line model of railway feeder
96
Vll
II
Figure 4.7: Impedance as seen by locomotive load at (a) Okm, (b) 10km,
(c) 20km and (d) 30km from feeder substation of a 30km
feeder section
98
Figure 4.8: 3 ro harmonic impedance as seen by a locomotive load at
different positions along feeder section, before and after
compensation (K=-0.2, a>c= 5rad/s)
99
Figure 4.9: 5th harmonic impedance as seen by a locomotive load at
different positions along feeder section, before and after
compensation (K=-0.2, (oc= 5rad/s)
99
i
Figure 4.10: 7th harmonic impedance as seen by a locomotive load at
different positions along feeder section, before and after
compensation (K=-0.2, ©c= 5rad/s)
100
3
Figure 4.11: Feeder voltage distortion gain for the third, fifth and seventh
harmonic frequencies as a function of locomotive load
position along the contact feeder length (K=-0.2, coc= 5rad/s)
100
Figure 4.12: Voltage profile on lossless line with different resistive
terminations
102
Figure 4.13: Harmonic voltage profiles for 30km feeder section due to a
single harmonic current source of ikA at 10km from
substation (a) 3rd harmonic (b) 5th harmonic (c) 7th harmonic
104
Figure 4.14: Harmonic voltage profiles for 30km feeder section due to a
single harmonic current source of IkA at 20km from
substation (a) 3rd harmonic (b) 5th harmonic (c) 7th harmonic
105
Figure 4.15: Harmonic voltage profiles for 300km feeder section due to a
single harmonic current source of IkA at 100km from
substation (a) 3rd harmonic (b) 5th harmonic (c) 7th harmonic
106
Figure 4.16: Small-signal control system block diagram for DC bus
voltage loop
111
Figure 5.1: Five-level inverter topologies, (a) Diode-clamped (b) Flyingcapacitor (c) Cascaded (d) Hybrid (reduced). (Ideally Vdci =
Vdc2 = Vdc)
117
Figure 5.2: 25kV railway system with proposed multilevel hybrid power
quality conditioner
120
Figure 5.3: Controller block diagram of proposed multilevel hybrid power
quality conditioner
122
Figure 5.4: Impedance seen by locomotive load at (a) Okm, (b) 10km, (c)
20km and (d) 30km from feeder substation of a 30km feeder
section
123
Figure 5.5: Band placements for three-level hysteresis current regulator
126
Figure 5.6: Band placements for reduced five-level hysteresis current
regulator
127
Figure 5.7: Band placements for cascaded five-level hysteresis current
regulator
128
I
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Pi
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p
1
Figure 6.1: Overall system schematic layout assumed in this thesis
136
Figure 6.2: PSCAD model of25kV power supply system
138
m
®
I1
Figure 6.3: PSCAD model of a 2.5MW locomotive
139
Figure 6.4: PSCAD model of single-phase two-level VSI
140
i
i
Figure 6.5: PSCAD model of single-phase reduced switch-count five-level
VSI
140
Figure 6.6: PSCAD model of three-level hysteresis current regulator for
controlling conventional single-phase two-level VSI
141
Figure 6.7: PSCAD model of hysteresis current regulator for reduced fivelevel VSI
142
Figure 6.8: PSCAD custom models of the DSP controller
143
Figure 6.9: PSCAD flow chart showing custom model routines
145
Figure 6.10: PSCAD built-in RMS meter blocks, (a) Single-phase (b)
Three-phase
146
Figure 6.11: PSCAD custom model for rms, average, and form factor
measurements
,
146
Figure 7.1: Schematic of experimental system with TPQC implemented
using either a two-level VSI or a cascaded five-level VSI
m
150
Figure 7.2: Schematic of experimental locomotive load
152
Figure 7.3: Digitally rendered image of CS-IIB Integrated Inverter Board
154
Figure 7.4: Structure of experimental single-phase H-bridge (two-level
VSI)
155
Figure 7.5: Structure of experimental cascaded five-level VSI
156
Figure 7.6: Functional diagram of three-level hysteresis current regulator board
158
Figure 7.7: Simplified functional diagram of CS-MiniDSP/CS-HB board
160
Figure 7.8: Flow chart illustrating the structure of the main interrupt
service routine
Figure 7.9: Direct form II transpose (DFIIt) structure for second-order
digital filter
Figure 7.10: State transition diagram for the background code
164
170
172
Figure 8.1: Simulated waveforms for case 1, before compensation - Vd:
voltage at the end of feeder section. Is: feeder substation
transformer current. ILB, ILD: various traction load currents
177
Figure 8.2: Simulated waveforms for case 8, before comepnsation - Vd:
voltage at the end of feeder section. Is: feeder substation
transformer current. ILC, ILD: various traction load currents.
177
II:
Figure 8.3: Simulated waveforms for case 1, after compensation with
basic two-level VSI - Vd: voltage at the end of feeder section.
Vjnv: T-PQC inverter switched voltage. Is: feeder substation
I
IX
'&••"
I:
1:1
1
I
transformer current. ILB, ILD: various traction load
currents. Iinv: T-PQC inverter current
178
Figure 8.4: Simulated waveforms for case 6, after compensation with
basic two-level VSI - Vd: voltage at the end of feeder section.
Vjnv: T-PQC inverter switched voltage. Is: feeder substation
transformer current. ILA, ILB, ILC, ILD: various traction
load currents. Ijnv: T-PQC inverter current
179
Figure 8.5: Simulated waveforms for case 8, after compensation with
basic tvo-level VSI - Vd: voltage at the end of feeder section.
Vinv: T-PQC inverter switched voltage. Is: feeder substation
transformer current. ILC, ILD: various traction load
currents. Ijnv: T-PQC inverter current
179
Figure 8.6: Voltage form factor as a function of distance along feeder
section for cases 1-5, before compensation
180
Figure 8.7: Voltage form factor as a function of distance along feeder
section for cases 1-5, after compensation
180
Figure 8.8: Voltage form factor as a function of distance along feeder
section for cases 6-9, before compensation
181
Figure 8.9: Voltage form factor as a function of distance along feeder
section for cases 6-9, after compensation
181
Figure 8.10: Feeder voitage as a function of distance along feeder section
for cases 1-5, before compensation
182
Figure 8.11: Feeder voltage as a function of distance along feeder section
for cases 1-5, after compensation
182
Figure 8.12: Feeder voltage as a function of distance along feeder section
for cases 6-9, before compensation
183
Figure 8.13: Feeder voltage as a function of distance along feeder section
for cases 6-9, after compensation
183
Figure 8.14: Experimental waveforms for case 1, before compensation VD: voltage at the end of feeder section. vA: voltage at node
A. JLD: traction load current at node D. is: feeder substation
transformer current
184
Figure 8.15: Simulated waveforms for case 1 after compensation with
hybrid two-level VSI - Vd: voltage at the end of feeder
section. Vjnv: T-PQC inverter switched voltage. Is: feeder
substation transformer current. ILB, ILD: various traction
load currents. Ijnv: T-PQC inverter current
186
Figure 8.16: Simulated waveforms for case 5, after compensation with
hybrid two-level VSI - Vd: voltage at the end of feeder
section. Vjnv: T-PQC inverter switched voltage. Is: feeder
substation transformer current. ILD: traction load current at
nodeD. Iinv: T-PQC inverter current
186
Figure 8.17: Experimental waveforms for case 1, after compensation with
hybrid two-level VSI - VD: voltage at the end of feeder
section. Vjnv: T-PQC inverter switched voltage. iLD: traction
load current at node D. ijnv: T-PQC inverter current
187
Figure 8.18: Experimental waveforms for case 5, after compensation with
hybrid two-level VSI - v^: voltage at the end of feeder
section. Vjnv: T-PQC inverter switched voltage. iLD: traction
load current at node D. ijnv: T-PQC inverter current
187
Figure 8.19: (a) Simulated and (b) Experimental VD harmonic spectra for
case 1 before compensation
188
Figure 8.20: (a) Simulated and (b) Experimental vD harmonic spectra for
case 1 after compensation
189
Fi^; ire 8.21: Simulated waveforms for case 1, after compensation with
reduced five-level VSI, favg ~ 2kHz - vd: voltage at the end
of feeder section. Vjnv: T-PQC inverter switched voltage. Is:
feeder substation transformer current. ILB, ILD: various
traction load currents. Ijnv: T-PQC inverter current
192
Figure 8.22: Experimental waveforms for case 1, after compensation with
reduced five-level VSI, faVg ~ 2kHz - vD: voltage at the end
of feeder section. Vjnv: T-PQC inverter switched voltage, iw:
traction load current at node D. ijnv: T-PQC inverter current
192
I
Figure 8.23: Experimental VD harmonic spectrum for (a) Five-level
inverter (b) Two-level inverter (conventional H-bridge)
193
i
Figure 8.24: Experimental waveforms for case 1, after compensation with
reduced five-level VSI, favg ~ 2.7kHz - VD: voltage at the
end of feeder section. Vjnv: T-PQC inverter switched voltage.
iLD: traction load current at node D. ijnv: T-PQC inverter
current
194
Figure 8.25: Experimental waveforms for case 5, after compensation with
reduced five-level VSI, favg ~ 2kHz - vD: voltage at the end
of feeder section. Vinv: T-PQC inverter switched voltage. ILD:
traction load current at node D. iinv: T-PQC inverter current
194
Figure 8.26: Experimental vD RMS values for case 1 over 22 fundamental
cycles, resonant filters implemented using delta operator
196
Figure 8.27: Experimental vD RMS values lor case 1 over 22 fundamental
cycles, resonant filters implemented using conventional shift
operator
196
Figure 8.28: Experimental waveforms for case 1, resonant filters
implemented using delta operator
197
Figure 8.29: Experimental waveforms for case 1, resonant filters
implemented using conventional shift operator
197
Figure 8.30: Sudden loss of iLD when T-PQC is operating, experimental
waveforms - VB: voltage at 10km point of feeder section. vD:
voltage at end of feeder secrtion. ijj> traction load current at
node D. iinv: T-PQC inverter current
198
Figure A.I: Single-phase equivalent synchronous reference frame filter
207
ij
K1
1
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1
Figure A.2: Lossless transmission line terminated in a resistive load RL
210
Figure A.3: Graph of cos2 9
213
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LIST OF TABLES
Table 2.1: Important statistics for waveforms in Figure 2.4
15
Table 4.1: Wavelengths of a typical railway system
108
Table 5.1: Switching states of cascaded five-level inverter (ideally Vdd =
Vdc2 = Vdc)
I:
1
m
Table 5.2: Switching states for reduced five-level inverter (ideally Vdd
130
=
Vdc2 = Vdc)
131
Table 7.1: Scaling factors adopted for the experimental system
151
Table 7.2: Real and experimental system parameters
152
Table 7.3: Real and experimental 2.5MW locomotive parameters
153
Table 7.4: Real and experimental 5MW locomotive parameters
153
Table 7.5: Real and experimental 10MW locomotive parameters
153
Table 7.6: Conversion formulae from second-order shift to delta
coefficients
Table 8.1: Loading conditions for the 30km feeder section (units of
2.5MW locomotives at full load current unless indicated
otherwise)
175
Table 8.2: Comparison of simulation and experimental results for cases 1
and 5 before compensation
190
169
Table 8.3: Comparison of simulation and experimental results for cases 1
and 5 after compensation
190
Table 8.4: Case definitions for sensitivity studies
199
Table 8.5: RMS Voltage (kV) before and after compensation for
sensitivity studies
Table 8.6: Voltage form factor before and after compensation for
sensitivity studies
200
200
Xlll
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ABSTRACT
Many electrified railway systems around the world today use single-phase 25kV
50/60Hz supplies. Although the latest generation of locomotives uses AC traction
Ii
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y
motors powered through sophisticated PWM AC drive control systems, many of the
locomotives still in service today are based on DC traction motors. These older types
of locomotive, which are expected to still be in service for many years to come, use
thyristor-based rectifier converters for speed control and hence the current drawn has
a low displacement power factor and is also rich in harmonic content. As a
consequence, such systems typically suffer from low system voltage, loss of average
voltage and harmonic overvoltage. The first two effects reduce the power and hence
limit the performance of locomotives, whilst the third problem tends to promote premature equipment failure.
El
This thesis presents a VSI-based Traction Power Quality Conditioner (T-PQC) which
integrates aspects of traditional STATCOM and active power filter to simultaneously
address the low system voltage and low average voltage problems in 25kV railway
systems. The proposed power quality conditioner comprises two main outer control
loops. The first loop generates a harmonic current reference proportional to the
measured harmonic voltage, thus presenting the T-PQC as low impedance at selected
harmonic frequencies. This has the effect of mitigating low order harmonics
throughout the feeder section, which in turn means an improved average voltage. The
second control loop generates fundamental reactive current reference, thus providing
reactive power to boost the rms voltage throughout the feeder section.
A refinement of the basic T-PQC adds an additional passive damping filter in parallel
to form a hybrid topology. This not only extends the capability of the T-PQC to damp
harmonic overvoltages, but also suppresses T-PQC switching noise producing a much
cleaner pantograph voltage even at lower switching frequencies.
To allow for greater capacity and better harmonic performance, use of multilevel
inverter topologies for the T-PQC are also explored. Two new and improved
XIV
hysteresis current regulation strategies based on multiple hysteresis bands have been
proposed to control the reduced switch-count and cascaded inverter topologies
respectively. These hysteresis strategies are more robust and easier to implement than
existing techniques.
The proposed T-PQC has been applied to a realistic 30km railway system, both in
computer simulation and in the laboratory on a physical scale model. Steady-state,
dynamic and transient results all show that the T-PQC significantly increases traction
system power transfer capacity with only a relatively minor capital investment,
allowing older thyristor based locomotives and increased traffic levels to be supported
without requiring a complete system upgrade. Sensitivity studies were also carried
out, further confirming the proposed T-PQC as a practical, robust and general solution
to 25kV railway systems.
XV
DECLARATION
This thesis contains no material which has been accepted for the award of any other
degree or diploma in any university or other institution, and to the best of the author's
knowledge, contains no material previously published or written by another person,
except where due reference is made in the text of the thesis.
Pee-Chin TAN
XVI
ACKNOWLEDGEMENTS
It has been five long years since I began the foray into PhD. First of all, I would like
to give honours to Lord Jesus Christ, for it is Him who has given me this wonderful
opportunity to undertake the research, and the confidence and ability to finish it. I also
thank the Lord for teaching and challenging me, not just in power system/electronics,
but also in many other areas of my life in the past five years. Praise be to the Lord!
•pi
Secondly I wish to thank my supervisors A/Professor Grahame Holmes and Professor
Bob Morrison. I thank Grahame for his valuable guidance and practical advice, and
fi
also for his suggestions in preparing this thesis. I thank Bob for introducing me to the
research topic and for offering to read my thesis even in his illness. Both of them have
'&
been extremely patient and supportive throughout my candidature, something that I
am always grateful of.
\m
Next, I would like to express my gratitude towards Mr. Andrew Mclver for patiently
fielding my long list of questions on DSP programming in the early stages of
programming, and towards Mr. Patrick McGoldrick for answering various hardwarerelated queries. The experimental work would have taken much longer without these
two people. Also, Mr. Gerwich Bode deserves special thanks for kindly lending me
his three-level hysteresis current regulator board to carry out the experiments.
I would also like to acknowledge the strong friendships developed with Dr. Charles
Chang, Dr. Poh Chiang Loh and Mr. Michael Newman. The laughter and
encouragement coming from these friendships have made life as a research student a
lot more enjoyable. In addition, Poh Chiang's assistance in getting me started in
hysteresis control for multilevel topologies has been most helpful and will always be
remembered, so is Michael's generosity in sharing various DSP programming tricks.
Last but not least, I want to take the opportunity to express the heartiest thanks to my
dad, brother and sister. Their love, patience and support over the past five years are
always a source of motivation and are greatly appreciated.
XVll
LIST OF PUBLICATIONS
During the course of research, various aspects of the work and ideas presented in this
thesis have been published in international conference proceedings and journals. The
complete list of publications is listed as follows:
1. P. C. Tan, D. G. Holmes, and R. E. Morrison, "Control of Harmonic Distortion
and Form Factor in 25kV AC Traction Systems Using an Active Filter", in Conf.
Rec. Australasian Universities Power Engineering Conference, pp. 146-151,
1999.
Republished as journal paper, Journal of Electrical and Electronics Engineering
Australia, Vol. 20, No. 1, pp. 65-70, 2000.
I
I
2. P. C. Tan, D. G. Holmes, and R. E. Morrison, "Control of Active Filter in 25kV
Traction Systems", in Conf. Rec. Australasian Universities Power Engineering
Conference, pp. 63-68, 2000.
i
3. P. C. Tan, R. E. Morrison, and D. G. Holmes, "Voltage Form Factor Control and
Reactive Power Compensation in a 25kV Electrified Railway System Using a
Shunt Active Filter Based on Voltage Detection", in Conf. Rec. IEEE Power
Electronics and Drives Systems Conference, pp. 605-610,2001.
»
4S
4
Republished as Transactions paper, IEEE Transactions on Industry Applications,
i
Vol. 39, No. 2, pp. 575-581, Mar/Apr 2003.
4. P. C. Tan, P. C. Loh, D. G. Holmes, and R. E. Morrison, "Application of
Multilevel Active Power Filtering to a 25kV Traction System", in Conf. Rec.
i
Australasian Universities Power Engineering Conference, 2002.
xvm
5. P. C. Tan, P. C. Loh, and D. G. Holmes, "A Robust Multilevel Hybrid
Compensation System For 25kV Electrified Railway Applications", in Conf. Rec.
IEEE Power Electronics Specialists Conference, pp. 1020-1025,2003.
Accepted for publication as Transactions paper, IEEE Transactions on Power
Electronics.
6. P. C. Tan, P. C. Loh, and D. G. Holmes, "Optimal Impedance Termination of
25kV Electrified Railway Systems for Improved Power Quality"
Provisionally accepted for publication as Transactions paper, IEEE Transactions
on Power Delivery.
K1
T
I
\5
t
S
i
XIX
GLOSSARY OF TERMS
i
ADC
Analog-to-Digital Converter
APF
Active Power Filter
BJT
Bipolar Junction Transistor
CPU
Central Processing Unit
CRPWM
Current Regulated Pulse Width Modulation
CSI
Current Source Inverter
CT
Current Transformer
DAC
Digital-to-Analog Converter
D-STATCOM
Distribution STATCOM
DSP
Digital Signal Processor
DVR
Dynamic Voltage Restorer
FACTS
Flexible AC Transmission System
FF
Form Factor
FFT
Fast Fourier Tra' --afOiTn
FORTRAN
Formula Translation (prt'^raraming language)
GTO
Gate Turn-off Thyristor
HV
High Voltage
IGBT
Insulated Gate Bipolar Transistor
IGCT
Integrated Gate Commutated Thyristor
ISR
Interrupt Service Routine
IRP
Instantaneous Reactive Power
LEM
Hall effect current transducer
MATLAB
A numerical analysis program
PCR
Predictive Current Regulation
PFC
Power Factor Correction
PI
Proportional plus Integral
PSCAD/EMTDC
A numerical analysis program
PWM
Pulse Width Modulation
RAM
Random Access Memory
-*
F
RMS
Root Mean Square
XX
SRF
Synchronous Reference Frame
sssc
Static Synchronous Series Compensator
STATCOM
Static Compensator
SVC
Static VAR Compensator
TCR
Thyristor Controlled Reactor
TSC
Thyristor Switched Capacitor
THD
Total Harmonic Distortion
T-PQC
Traction Power Quality Conditioner
UPS
Uninterruptible Power Supply
UPFC
Unified Power Flow Controller
UPQC
Unified Power Quality Conditioner
VSI
Voltage Source Inverter
I*
M
XXI
I,
LIST OF SYMBOLS USED
a
Phase angle by which Vj leads Vs
P
Wave number
Y
Propagation constant of transmission line
X
Wavelength
en
Phase angle of nth harmonic component
COl
Bilinear transform prewarped frequency
Cut-off (angular) frequency
Synchronous frame (angular) rotating frequency
System (angular) frequency
Speed of electromagnetic wave
2, B3, B 4
Widths of displaced hysteresis bands
CP
Capacitance of RLC passive damping filter
Gcs(s)
Current sensor transfer function
GHE(S)
Harmonic extraction circuit transfer function
G,c(s)
Inner current loop transfer function
lAPF
Instantaneous (time-vaiying) active power filter current
ic
Instantaneous compensation current reference
.*
Id
Instantaneous current reference for DC bus control
lhar
Instantaneous current reference for harmonic compensation
Instantaneous load current
Instantaneous load currents at nodes A, B, C and D respectively
Instantaneous real component of load current
Instantaneous reactive component of load current
. *
In
Instantaneous current reference for reactive power compensation
is
Instantaneous source current
II
Magnitude of load current
J
Magnitude of real component of load current
P
Magnitude of reactive component of load current
K
Proportional constant m T-PQC harmonic compensation loop
XXll
K,
Integral constant of PI controller
KP
Proportional constant of PI controller
h
Position of locomotive
L
Total length of transmission line or feeder section
Lc
Equivalent series inductance of T-PQC coupling transformer and
external filter inductor
LP
Inductance of RLC passive damping filter
Rp
Resistance of RLC passive damping filter
T
Sampling period
Tcs
Current sensor time constant
vD
Instantaneous voltage at the point of common coupling
v.avg
v
(Rectified) average value of voltage
m
Peak value or magnitude of sinusoidal voltage
Root mean square value of voltage
Vs
System/source voltage
Vl, V inv
Inverter terminal voltage
vdc
v dc *
Inverter DC bus voltage
Inverter DC bus voltage reference
V/-/
Line-to-line voltage
X
Position along transmission line
Zo
Characteristic impedance of transmission line
XXlll
CHAPTER 1: INTRODUCTION
1.1
BACKGROUND
In electrified railway systems, power is supplied to the locomotives along the track by
means of an overhead contact wire or if at ground level, using an extra third rail laid
close to the running rails. The power can be transmitted as either DC or AC. In the
early 20 century, when railway electrification was in its infancy, electrification
i
';
schemes were predominantly based on DC supply systems. This was because,
combined with DC traction motors on the locomotives, speed control can be simply
achieved by switching in and out different amounts of series resistances.
Whilst the advantages of using industrial frequency AC transmission were well
recognised, it wasn't until the 1950s when mercury arc rectifiers of sufficient power
I
ratings became available that AC railway electrification schemes based on 25kV
50/60Hz supply networks started to receive widespread adoption. Compared to DC
systems, AC electrification can be easily transmitted at higher voltages and hence can
handle higher power and requires fewer substations. Thus it is particularly suitable for
high-speed, heavy-haul and longer distance railways. Nowadays, 25kV 50/60Hz
electrification has become the standard for new main line and suburban railway
systems [1-4].
Over the past 50 years, a range of locomotives has been utilised on AC railway
systems, using either DC drive motors or (more recently) AC drive motors. The
earliest drive systems first used mercury arc and then diode rectifiers. With these
rectifiers, armature voltage and hence speed control was achieved through the use of
voltage tappings on the traction transformer winding. In the mid 1970s, this approach
was later superseded by phase-controlled thyristor converters, since such converters
can create a smoothly varying (average) DC voltage without the need for bulky
transformers with complicated tapping arrangements. DC motor driven locomotives
with thyristor converters were the main type of unit produced for the next 15 years or
CHAPTER 1:
Introduction
so, until the early 1990s when variable voltage variable frequency (VWF) AC drive
technology became mature enough to be used on locomotives.
Today, there are many of the older types of locomotives still operating. With the
present trends of plant operation for finding methods of maintaining the older plant in
operational order for prolonged periods, it has now been recognised that the longer the
delay in replacing plant the greater is the cost saving. Therefore it is expected that the
older rectifier and thyristor converter type locomotives will be operating for many
years to come.
These older types of locomotive can cause significant traction system problems due to
the lagging load current at the fundamental frequency and severe levels of harmonic
current that they produce. The lagging load current causes a significant amount of
reactive voltage drop along the feeder line. On the other hand, problems associated
with the harmonic distortion are trackside over-voltages, increased voltage form
factor and excessive low order harmonic currents fed back into the HV supply.
IEC specification 349 stipulates that the minimum pantograph voltage must be above
19kV continuously and 17.5kV for short periods. For new electrification schemes, this
places a limit on the distances between substations; for existing railway systems, this
limits the amount of locomotive loads that the system can support. Thus there is a
need to find ways of improving voltage regulation to allow longer substation spacing
for new electrification schemes and to allow load growth for existing schemes.
There are many options for improving voltage regulation, as reported by Griffin [4].
Some of the conventional methods include installing an additional parallel feeder wire
to reduce the effective feeder impedance, upgrading to an auto-transformer feeder
arrangement, or using a higher 25kV fault level at each 25kV supply point. These
options are generally costly and require extensive disruption to traffic flows [5].
Series compensation is also considered a viable solution [4-6]. Here a capacitor is
inserted in series with the feeder line to cancel the inductive reactance at fundamental
frequency. However, series capacitor compensation can only provide limited capacity
increase and often also requires phase-breaks to handle the voltage discontinuities
created.
CHAPTER 1:
Introduction
Another generic means of effective compensation is shunt compensation, which
involves connecting a source of reactive power between the overhead wire and earth.
They work by providing a local source of reactive power to the locomotive loads,
eliminating the need to transport reactive power down the feeder line and hence
minimising the associated reactive power voltage drop. The reactive power source can
be as simple as a bank of fixed capacitors that can be mechanically switched in and
out of the circuit. More sophisticated power electronic circuits can also be used, such
as thyristor controlled reactors (TCR) which can provide continuously varying
amounts of reactive power by means of thyristor firing angle adjustment. Whilst
studies have been carried out to show that static var compensators based on
conventional TCR are able to provide satisfactory voltage support in 25kV railway
systems, under certain circumstances two difficulties remain:
1. Voltage excursions following the sudden switch off of load could be up to 130%
for 1 cycle. Although this level of overvoltage is unlikely to lead to technical
difficulties, some manufacturers of the older types of locomotive might not give
assurance that this level of overvoltage is acceptable.
2. The reactive power limit of the compensator may be determined by the maximum
capacitor switching current of a 25kV circuit breaker.
On the other hand, the problem of low order harmonic voltage distortion on railway
systems has also never been seriously addressed, especially in light of the newer
technology based on switching devices. Traditionally passive filters are the main
solution to harmonic problems, but they come with many caveats and are not
particularly suitable for use on railway systems.
In the past decade, the availability of high power self-commutated semiconductor
switches has sparked intense research effort and industrial deployment in advanced
FACTS (Flexible AC Transmission System) controllers and custom power
technology, in an effort to achieve better active and reactive power control and power
quality improvement. In particular the Static Compensator (STATCOM) and the
Active Power Filter (APF) are devices based usually on the Voltage Source Inverter
CHAPTER 1:
I
Introduction
(VSI), and have the respective potentials to generate or absorb reactive power as well
as active harmonic mitigation. It has been shown that a number of benefits can be
gained from the use of this class of compensators in general 3-phase power supplies,
and it is reasonable to expect similar benefits from their application to 25kV singlephase railway systems. In fact, compared to a conventional TCR based reactive
compensator, a STATCOM/APF has the following advantages:
1. A VSI switches faster than a TCR, and hence the voltage overshoot following load
disconnection should be significantly reduced.
2. The VSI topology is able to supply full rated capacitive output current
independent of system voltage, whereas the TCR based compensator maximum
output current drops off with decreasing system voltage, since it is essentially an
impedance device. Hence the former is more robust in supporting system voltage.
i
3. The VSI allows for increased transient rating in both capacitive and inductive
regions, whereas the TCR compensator cannot provide increased capacitive output
current.
4. The VSI topology does not require a separately switched 25kV capacitor, and
hence there is no need for a circuit breaker with high capacitor current switching
duty.
5. The VSI could also act as a harmonic filter and control the system form factor.
This is an important factor when a STATCOM/APF is applied to a system on
which conventional thyristor locomotives operate.
6. The VSI is likely to be physically small and could be constructed as a relocatable
unit.
1.2
AIM OF THE RESEARCH
Despite the general perception that STATCOM and APF now represent a reasonably
mature technology and are becoming serious contenders to conventional power
CHAPTER 1:
Introduction
quality solutions, there still remain a number of technical challenges that need to be
resolved before they can be safely and confidently installed on a railway system with
reliable performance.
Railway systems have compensation requirements that are rather different from that
of a general power system. Despite the vast array of STATCOM/APF topologies
along with the confusingly large variety of control strategies that exist in the
literature, there is currently no one single topology and control strategy that is directly
applicable to railway systems. Furthermore, a typical railway system is a rather weak
system and therefore is more susceptible to control stability problems. A robust
control strategy will need to be found to ensure system stability even under extreme
conditions. Thirdly, the great majority of research literatures on APF assume a threephase public distribution system, but some of the important control concepts are not
directly applicable to a single-phase system. Fourthly, railway systems are known to
have a resonance frequency around 1kHz and thus it must be ensured that the
operation of the active compensator does not trigger this resonance.
A VSI-based compensator suitable for 25kV electrified railway applications with
capabilities for fundamental voltage support, low order harmonic mitigation and
harmonic overvoltage damping has so far remained unexplored. Thus the
development and evaluation of such a compensator constitute the principal aim of this
thesis.
1.3
CONTENTS OF THE THESIS
The work in this thesis proposes a shunt hybrid compensator made up of active
compensator / high pass passive filter combination as a complete solution to the three
most important power quality issues in railway systems, namely, low system voltage,
harmonic overvoltage and loss of average voltage. The thesis consists of two major
themes, the first of which deals with the design of a suitable controller for a basic
shunt active compensator to simultaneously control form factor and provide voltage
support. The second theme seeks to improve on the basic compensator by combining
with high pass passive filter to form a hybrid topology which is also able to damp any
system harmonic overvoltages and at the same time achieve better control of
CHAPTER 1:
Introduction
switching harmonics. For additional capacity and harmonic performance, multilevel
inverter topologies are also adopted. Improved hysteresis current regulation strategies
are also developed for the selected multilevel topologies.
The material in this thesis is organised in the following manner:
Chapter 1 presents the context and the aim of research, and identifies the structure and
original contributions of this thesis.
Chapter ^ ^escribes the 25kV single-phase railway system, identifies the nature of
existing problems in such systems, and then briefly reviews the various traditional
solutions to these problems that have been reported in the literature. The material in
this chapter highlights the uniqueness of the railway system and will assist in
understanding the choice of compensator topology and control strategy developed in
Chapters 4 and 5.
Chapter 3 presents a systematic and critical review of STATCOM and APF, focusing
on the topology and associated control strategy. This allows appropriate state-of-theart compensation methodologies to be quickly identified, modified and integrated for
use in a composite compensator that addresses the needs of railway systems.
Chapter 4 presents a traction power quality conditioner to simultaneously control
voltage form factor and provide rms voltage regulation. The control strategy is
developed and analysed, addressing issues such as a single-phase harmonic extraction
algorithm and termination of transmission lines. The effective system harmonic
impedances as seen by locomotives loads are examined to confirm the effectiveness
of harmonic mitigation throughout the entire traction feeder.
Chapter 5 extends the basic power quality conditioner in the previous chapter to a
hybrid topology with an additional parallel passive filter for better control of
harmonic overvoltages and switching noise. Use of multilevel inverters is also
discussed and presented along with two improved hysteresis current regulation
strategies for the reduced switch-count and cascaded multilevel topologies.
CHAPTER 1:
Introduction
Chapter 6 summarises the approach used for simulating the performance of the shunt
active compensator in a 25kV railway system, identifying in particular the
assumptions made in relation to the models developed in PSCAD/EMTDC. Outlines
of the custom models created within PSCAD are also presented.
Chapter 7 describes the design and construction of a scaled railway system model and
also the experimental inverter used to confirm the theoretical and simulation analyses
presented in the thesis. Particular challenges in implementing the continuous time
concepts on the low-cost fixed-point DSP that was used to control the inverters are
also highlighted.
Chapter 8 presents and compares the results of simulation and experimental studies to
confirm the validity and practicality of the proposed active compensation strategy. A
30km railway system is used for these studies, with steady-state, dynamic and
transient results shown and discussed. Sensitivity studies are also included.
Chapter 9 summarises the work presented, reviewing important contributions that
have been made and identifying areas where further research may be useful to
continue the investigations.
1.4
IDENTIFICATION OF ORIGINAL CONTRIBUTIONS
The work presented in this thesis covers the actively researched fields of STATCOM
and APF which have seen rapid developments in recent years. To assist in assessing
the thesis, the original contributions presented in this thesis are summarised as
follows:
•
Recognition that the pantograph voltage distortions in 25kV AC railway supply
networks can be separated into low frequency and high frequency components and
should be separately compensated for maximum cost-effectiveness.
•
Integration of control features from STATCOM and APF to arrive at a novel
shunt power quality conditioner for traction applications, with simultaneous
J! 4
capabilities of restoring the form factor of the pantograph vcliage as well as
providing fundamental rms voltage support.
•
Implementation of selective harmonic extraction in a single-phase active
compensation system.
•
Extension to a hybrid power quality conditioner as a complete and robust solution
to combat all the three main issues simultaneously in 25kV railway systems.
•
Development of two improved hysteresis current regulation strategies for
controlling the reduced switch-count and cascaded multilevel inverter topologies
respectively.
These contributions have been published in five conference papers, one IEAust
journal article and one IEEE transactions journal.
CHAPTER 2: THE 25KV 50HZ
ELECTRIFIED RAILWAY SYSTEM
The 25kV 50/60Hz single-phase supply system is now widely regarded as one of a
number of standard railway electrification schemes. Due to the high voltage it uses for
transmission, it is particularly attractive for high-speed, heavy haul and long distance
routes. There are currently many such railway systems installed around the world. In
such a system, power is delivered to the locomotives through dedicated overhead
transmission wires that span tens and hundreds of kilometres. In this respect, it is not
unlike a public power transmission/distribution system. However, because railway
systems are private systems that have been designed to serve a very restricted range of
loads, they possess many unique characteristics that are normally not found or at least
not pronounced on a public three-phase power system. For the same reason, the power
quality requirements on railway systems are also significantly different to those on a
general public system.
This chapter describes the salient features found in 25kV 50Hz railway systems and
also the power quality requirements of locomotive loads. These establish a set of
compensation objectives that will assist in understanding the choice of topology and
control strategy of the power quality conditioner used in later chapters.
2.1
25 KV POWER SUPPLY LAYOUT
A typical power feeding arrangement for a conventional single-track 25kV electrified
railway system is shown in Figure 2.1. Each feeder substation consists of two singlephase feeding transformers in this single-end feeding configuration. Incoming power
from the HV utility supply is stepped down to 25kV by the feeding transformer and
delivered along the overhead contact wire so that locomotives can be fed at any point
along the electrified network.
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
HV Supply
HV Supply
Section length
Section length
LESENE
y
'•»
Feeding transformers
N/C Circuit
Breaker
N/O Circuit
Breaker
Neutral
section
25KV contact feeder
Feeder Substation
Track-Sectioning
Cabin
Feed sr Substation
Figure 2.1: Typical power feeding arrangement for 25kV electrified railway systems
When trains are running, current is drawn along the contact feeder, resulting in
voltage drops across the impedances of the feeding transformer and contact wire.
Most 25kV railway systems are designed to comply with the IEC specification 349
which requires the locomotive pantograph voltage to be between 19.0kV and 27.5kV,
with a minimum of 17.5kV allowed for short duration [7]. To avoid the feeder voltage
sagging below the specified minimum, the contact network is divided into electrical
sections that are typically 15km to 30km in lengths [8]. Thus, as shown in Figure 2.1,
an electrical section consists of a contact network fed at 25kV by a feeding
I'M
transformer at a substation and terminating at a track-sectioning cabin which is
located at an intermediate location between two neighbouring substations. Beyond the
track-sectioning cabin, power is delivered from the neighbouring substation via a
J
feeder running in the opposite direction. As the substation spacing is simply twice the
section length, it is seen that voltage regulation has a direct influence on substation
spacing and hence the number of substations in a particular electrification scheme.
A rather unusual aspect of railway systems is that the feeding arrangement may
change according to circumstances [9]. For example, when one of the substation
transformers is lost, the system can be switched into a first emergency feeding
arrangement whereby the normally opened circuit breaker at the substation will close
so that one transformer is used to feed the two electrical sections on either side. When
an entire substation is lost, it will be necessary to operate in second emergency
feeding whereby the circuit-breaker at the track-sectioning cabin is closed so that one
transformer is used to feed a contact network of twice the normal length. Obviously
under these circumstances the system loading needs to be reduced to maintain the
10
CHAPTER 2:
The 25kV50Hz Electrified Railway System
9000
8000
7000
•g 6000
•e
S 5000
I
4000
1
1,2000
1000
0
A \\ - A
E 3000
1
1000
\\
2000
-^
3000
4000
Frequency (Hz)
5000
6000
Figure 2.2: 1 Magnitude of railway system impedance at the end of a 30km feeder
section
same minimum voltage limits. Thus for any compensating equipment to be installed
on a railway system, provisions must be given to ensure its satisfactory performance
under a range of potential feeding conditions.
Figure 2.2 shows the impedance up to 6kHz cf a typical 25kV railway system as seen
from the end of a 30km feeder section. It contains a characteristic resonant peak at
about 1350Hz. The implication of this is explored further in Section 2.6 of this
chaptei
2.2
THYRISTOR LOCOMOTIVES
Locomotives based on power thyristor rectifier circuits have been the mainstays of
25kV systems since the 1970s, and have only gradually been superseded by
locomotives employing PWM AC drives in the last decade. Nevertheless, with
lifetime of vehicles of the order of 30 years, there are still many thyristor locomotives
operating throughout the world. It is this type of locomotives that are the source of
problematic interactions with the railway system, and therefore will be the focus of
this research. The power circuit of a typical thyristor locomotive is shown in Figure
2.3.
11
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
25kV 50Hz Overhead Contact Wire
Locomotive!
Main
Transformer
Figure 2.3: Main power circuit of a Bo-Bo thyristor locomotive
Incoming voltage at 25kV from the overhead contact wire is picked up by the
pantograph and stepped down by the locomotive main transformer to more
manageable voltage levels to be used on board. The main transformer typically
consists of four secondary windings, each feeding a half-controlled thyristor bridge
rectifier [10-13]. Two rectifier bridges are connected in series and fed to a group of
DC motors on the same bogie. The use of bridges in series allows higher power factor
and lower current harmonic distortion to be obtained at the transformer primary
[13,14].
To ensure that realistic locomotive operating conditions are properly modelled in the
studies to be carried out, a basic understanding of how the DC traction motors are
controlled is in order. This is described in the next subsection.
12
CHAPTER 2:
2.2.1
The 25kV 50Hz Electrified Railway System
Thyristor Locomotive Control
There are two types of DC traction motors in use, namely the separately excited motor
and the series motor [15,16]. Only the start-up sequence of the more robust and
widely used [10-12,17,18] separately excited motor is described here, although it is
I
quite similar for the series motor.
From the locomotive AC input current harmonic point of view, there are basically 4
U
distinct regions of operation that can be identified:
1. Initially at standstill, maximum field current is applied and the first thyristor
bridge is advanced to maintain the motor armature current at the rated maximum,
whilst the second bridge is free-wheeling through the diodes. This allows
maximum torque and hence acceleration to be obtained. For this period the system
sees the locomotive as a single thyristor bridge in partial conduction, with
constant maximum DC current.
2. When the first bridge is fully advanced so that maximum DC voltage is obtained
from the first bridge, the second bridge is advanced, again to maintain the
maximum constant armature current and hence acceleration. For this period the
system sees the locomotive as a diode bridge in cascade with a thyristor bridge in
partial conduction, with constant maximum DC current.
3. When the second bridge is also fully advanced so that maximum DC voltage is
obtained across the traction motor, the field current is gradually reduced to
maintain the same maximum armature current. This corresponds to maximum
power operation and allows a higher speed to be obtained than without field
weakening. For this period the system sees the locomotive as only a diode bridge
but with twice the voltage of individual secondary windings, with fixed constant
DC current.
4. Finally when the field current is reduced to a minimum, it is held at that value and
the train will eventually coast at constant, balancing velocity. This corresponds to
13
I
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
weak-field operation. For this period the system sees the locomotive as only a
diode bridge as in mode 3 above, but with reduced armature (DC) current.
The above information is needed for modelling the locomotives, as described in
Chapters 6 and 7.
2.3
POWER QUALITY ISSUES FOR 25KV RAILWAY SYSTEMS
Power quality problems arise when the thyristor locomotives described in the last
section are operated on typical 25kV railway systems. To illustrate the problems,
simulation waveforms of the 30km feeder section shown in Figure 2.2 are obtained
for a train hauled by two 2.5MW locomotives operating at the end of the section. The
two locomotives are assumed to be drawing full current at some delayed firing angle.
Figure 2.4(a) shows the pantograph voltage (ie. voltage of the overhead feeder at the
train location) and Figure 2.4(b) shows the total current drawn by the two locomotives
(a) Pantograph voltage
0.06
0.065
0.07
0.075
0.08
0.085
0.09
0.095
0.1
(b) Load current
0.4
1
— —
....
"••••1
0.2 -
/—
c
I
0
1
/
J.
1
/
-0.4
0.06
,.
0.065
0.07 0.075
0.08 0.085
Time (s)
0.09 0.095
0.1
Figure 2.4: Simulated waveforms for two 2.5MW locomotives at the end of a 30km
feeder showing (a) Pantograph voltage and (b) Load current
14
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
at the pantograph. The corresponding harmonic spectrums are shown in Figure 2.5.
Summary statistics relating to these waveforms are provided in Table 2.1. Note that
the pantograph waveform in Figure 2.4(a) is comparable to the field measurements
published in [19-21].
(a) Pantograph voltage
[
H
(D
> i
1000
2000
3000
4000
5000
4000
5000
-s
J
I
(b) Load current
1000
I 1
2000
3000
Frequency (Hz)
Figure 2.5: Harmonic spectrums for two 2.5MW locomotives at the end of a 30km
feeder, (a) Pantograph voltage (b) Load current
Pantograph
Voltage
Load Current
THD
44.4%
15.4%
Form Factor
1.25
Not relevant
Rectified Average
17.8kV
Not relevant
RMS
22.3kV
0.24kA
Crest Value
58kV
Not relevant
Displacement
Power Factor
0.68
Table 2.1: Important statistics for waveforms in Figure 2.4
15
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
Compared to the 25kV sinusoidal voltage waveform supplied at the feeder substation,
the pantograph voltage quality is certainly very poor in many ways. In particular, it is
observed that the pantograph voltage has:
[4
A
•
a low rms value (22.3kV compared to 25kV);
•
a low rectified average value (17.8kV compared to 4l x 22.3&F x — = 20. ikV);
K
•
•i
an enhanced crest value (58kV compared to -v/2 x 25kV - 35.5&F).
These non-perfections are typical in a railway system and have adverse effects on the
performance of locomotives, and therefore need to be mitigated. They are brought
about by different mechanisms and each entails a different solution approach. The
i
remainder of this chapter will discuss the significance, causes and remedies of the
three individual problems.
2.4
Low SYSTEM RMS VOLTAGE
2.4.1 Cause and Significance
Voltage drop occurs when the load current flows through the system impedance,
consisting of the substation transformer impedance and the overhead line impedance.
In railway systems, the load current represents a significant fraction of the system
short-circuit current, and this results in significant voltage drops along the line. A
drop in the system voltage means less power to the locomotives, and this in turn
implies less speed.
To ensure consistent and reasonable performance of locomotives, EEC specification
requires that the system voltage to be maintained between 27.5kV and 19kV for a
nominal 25kV system. Although this wide variation is unacceptable in a general
distribution system due to the presence of sensitive loads, it is considered normal for a
railway system, without which many traction systems would not be economically
viable.
16
The 25kV 50Hz Electrified Railway System
The implication of imposing the IEC voltage limits is that, for an existing system,
traffic growths are often restricted by system voltage regulation. In new electrification
schemes, a principal design objective is to minimise the number of feeder substations,
since they are arguably the single most expensive item in the system. However,
substation spacings are constrained by the need to maintain acceptable overhead
feeder voltage at expected load levels. Thus for new and existing systems there is a
need to find ways of improving the voltage regulation of conventional 25kV systems.
2.4.2
Solutions to Voltage Regulation
Griffin has documented a range of options for improving voltage regulation
applicable to 25kV railway systems [4]. Most of these options are trivial and not
likely to be cost-effective, including reducing the distance between the feeder
substations, increasing the 25kV fault level at each 25kV supply point, installing
parallel feeder circuits or using twin contact overhead wiring system, etc.
Other useful methods of achieving improved voltage regulation are series and shunt
compensation. The effectiveness of these compensation methods can be appreciated
by first considering a simple power transmission system where a load is fed from a
voltage source through resistive and inductive impedances. The situation is depicted
i L =i P -J" q
(b)
Figure 2.6: Locomotive load fed through inductive and resistive impedances, (a)
Simplified circuit diagram (b) Phaser diagram
17
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
in Figure 2.6.
Phasor analysis shows that
-IpR-IqX
(2.1)
From (2.1), it is clear that there are four components contributing to the voltage drop:
IPX, IqR, IPR and IqX. However, because IPX and IqR are orthogonal to V2, their
effects on V2 will be significantly smaller compared to those of IpR and IqX. Further,
it should also be noted from (2.1) that although a lagging displacement factor (ie. Iq *
0) is not the only cause of voltage drop, the presence of Iq does significantly
exacerbate the situation. In a typical railway system, the feeding transformer
impedance has X/R « 10 [4] at 50Hz and the transmission line impedance has X/R « 3
[4,5,22], giving a total feeding X/R « 4. This means that either lowering Iq or X is
effective in reducing the voltage drop.
Series compensation involves placing a series capacitor somewhere in the mid-point
of an overhead transmission line, thereby allowing its capacitive reactance to partially
cancel the inductive reactance of the transmission line. This reduces the effective
impedance of the line and hence the same load current will result in a lower voltage
drop. This type of compensation has been extensively used in three-phase power
systems [4] and has also been implemented in a single-phase 50kV railway system
[6]. The disadvantage with series compensation is that a voltage discontinuity
invariably exists at the series installation point. This is not a problem on a public
three-phase power system, since the load locations are stationary with respect to the
transmission feeder. On a railway feeder, however, the locomotive moves along the
overhead transmission line and will need to traverse the voltage discontinuity. This
usually necessitates a phase-break arrangement at the capacitor, resulting in a
complicated overall design.
Shunt compensation for voltage regulation works by providing a local source of
controllable reactive power, thereby reducing the amount of reactive current supplied
from the feeder substation and thus boosting the receiving end voltage. This method
18
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
of compensation is more commonly referred as reactive power compensation. If a
purely capacitive compensation current Ic is drawn as shown in Figure 2.7, the load
voltage is given by
(2.2)
Equation (2.2) shows that Ic can be used not only to cancel Iq and the associated
reactive voltage drop, but also to boost V2 to any reasonable level.
Reactive pov/er compensation is now usually realised with Static VAR Compensators
(SVC) which utilise switching semiconductor devices. The first generation of SVCs
uses naturaliy coynmutated thyristor devices and is based on the three main building
blocks shown in Figure 2.8.
The TCR is able to absorb a continuously variable amount of lagging reactive power
by virtue of thyristor delayed firing, whereas the TSC functions as an on-off device
that switches in a fixed amount of leading reactive power. The FC/HF is capacitive at
Load
v
z ( t ) Compensator
Figure 2.7: Shunt reactive power compensation
(a)
(b)
(c)
Figure 2.8: Main building blocks for conventional SVCs: (a) Thyristor-controlled
reactor (TCR) (b) Thyristor-switched capacitor (TSC) (c) Fixed Capacitor/Harmonic
Filter (FC/HF)
19
CHAPTER 2:
The 25kV SOHz Electrified Railway System
the fundamental frequency and therefore provides a fixed amount of fundamental
reactive power, and at the same time it is also tuned to absorb harmonic currents.
Conventional SVCs employing TCR/FC and TCR/TSC combinations have been used
extensively in general three-phase power distribution systems for transient stability
improvement, power oscillation damping and voltage support [23], but not used on
railway systems. Hu et al. proposed the use of a single-phase TCR/FC type SVC for
voltage regulation in a 25kV railway system [24-27], showing that with SVCs
installed the traction feeding substation spacing can be substantially increased.
Because of the relatively slow response of a SVC, transient overvoltages of up to 30%
following sudden loss of load are possible. Also the capacity of a conventional SVC
to supply reactive power diminishes at low system voltage, which is when reactive
power is needed most.
These drawbacks can oe solved by the latest generation of compensators employing
self-commutated semiconductor switches, namely the STATCOM. This is discussed
further in the next chapter together with active power filters.
2.5
Low AVERAGE VOLTAGE
Having a low rms voltage is undesirable enough, because that means reduced
locomotive performance. However, for the same rms voltage, if the voltage waveform
2
is distorted so that its (rectified) average value is reduced from —Vm (where Vm is the
peak of the undistorted sinusoid), the performance of the locomotive will be further
impaired. The output power of a rectifier locomotive is determined by the product of
the rectifier DC-side average voltage and average current. Therefore a reduction in the
pantograph voltage's average value translates into a lower maximum power available
to the locomotive.
It has been shown that the reduction of average value of a waveform can be primarily
attributed to the presence of low order harmonic components (ie, 3rd, 5th, etc as
opposed to higher order ones) [24]. The effect of harmonic components on the
average value of a waveform is illustrated in Figure 2.9.
20
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
(b)
Resultant
Fundamental
Figure 2.9: Effect of harmonic components on the average value of a waveform
Figure 2.9(a) shows one half cycle of an undistorted sinusoidal waveform at the
fundamental frequency. The (rectified) average value is simply proportional to the
area under the curve. Figure 2.9(b) shows a distorted waveform which is represented
by its &mdamental and 3rd harmonic components. In this case, integration is again
performed ever one haif of the fundamental period. The average value of the distorted
waveform is proportional to the algebraic sum of the areas of the two curves. As
shown, the first two positive and negative half cycles of the 3rd harmonic component
cancel each other out, leaving only the shaded area to contribute to the final average
value.
A similar situation is shown in Figure 2.9(c) for a waveform with 5th harmonic
distortion. Only the last shaded area contributes to the final average value. It is
obvious that, for the same harmonic amplitudes, the contribution by die 5th harmonic
component is smaller than that of the 3rd harmonic shown in Figure. 2.9(b).
Indeed it can be verified mathematically that a signal containing a fundamental
frequency component and an nth harmonic component:
21
, "*...
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
v(t) = Ax sin(<y/) + An sm.{ncot + 9n)
(2.3)
has an average value given by
A} +—cos0 n
n
0
if n is odd
(2.4)
if n is even
which shows that the contribution to the average value by the nth harmonic component
is only — that of the fundamental component, ie. low order harmonics have the
n
strongest influence on the average value. Note that this has nothing to do with the fact
that the magnitude of a lower harmonic component in the system is usually higher
than that of a higher order harmonic component, although this does make the
contribution of the lower harmonic components in practice even greater.
In Figure 2.9 the fundamental and harmonic components are 180° out of phase, which
achieves maximum average value reduction. Alternatively, if the fundamental and the
harmonic components are in phase, the average value will increase to a maximum
above nominal, as indicated by (2.4). In general, the harmonic phase relationships on
a traction system are such that reductions in the average voltage values are the norm,
because rectifier locomotive loads are fed through an inductive transmission line,
which contributes 90° of phase lag to the harmonic voltages. Hence cos#n in (2.4) is
negative for most firing angles. Since the maximum impact a harmonic component
can have on the average value gets progressively smaller f?: • UN; : :. aarmonic orders,
it can be seen that a means of mitigating only the fink >J,"- "ow-order voltage
harmonics need be provided to improve the average value of the pantograph voltage.
A convenient way of measuring the average voltage is to use the form factor, defined
as
CHAPTER 2:
-1
The 25kV 50Hz Electrified Railway System
E'E'
(2.5)
avg
\
T
JM*
t
which measures the squareness of the waveform. An undistorted sine wave has a form
factor of 1.1107. The higher the form factor of a waveform, the lower the average
value for a given rms value, and therefore the more low order harmonics are included
in the wavefonn. In the example shown in Figure 2.4, the pantograph voltage has a
-j
form factor of 1.25, representing a loss of about 13% of available power due to low
order harmonic distortion alone.
i
Note also that in the example shown in Figure 2.4, the voltage waveform has a total
harmonic distortion (THD) of 44% which is not uncommon in traction systems.
However, since there are no sensitive loads connected directly to the system, the high
,. I
THD itself is usually not a cause for concern and definitely not a useful indicator of
traction performance. Rather, as discussed above, the low order harmonic voltages,
such as measured by the form factor, need to be minimised.
To date, only passive filters have been employed to improve the voltage form factor
[6,25], wifo the usual problems associated with passive filters unanswered. This will
be discussed further in Chapter 3 along with active power filters.
2.6
HARMONIC OVERVOLTAGE
2.6.1
Cause and Significance
It is seen in Figure 2.4(a) that the pantograph voltage contains a 1.3kHz high
frequency ring superimposed on the 50Hz fundamental waveform. This is in fact very
typical of many railway systems when excited by thyristor converter loads [8]. Since
they are transmission lines, traction overhead feeders have theoretically an infinite
number of resonant frequencies. In Figure 2.2, it is shown that at the parallel resonant
frequencies, the system impedance can be as high as a few kilo-ohms. Furthermore,
thyristor converter loads are notorious for the rich harmonic content in the AC current
23
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
that they draw, as shown in Figure 2.5(b). Although only a relatively small amount of
current is present in Figure 2.5(b) at 1.3kHz, the large system impedance at that
freqeuncy results in an appreciable harmonic voltage at the pantograph. When this
voltage is added (vectorially) to the fundamental voltage, it can produce a voltage at
the pantograph with crest values significantly above nominal (58kV in this case,
which represents an overvoltage of 64%). This phenomenon, known as harmonic
overvoltage, is present in all electric systems where converter loads are connected, but
is a lot more serious in railway systems because the load rating is typically a large
fraction of the short circuit MVA of the system (a 10MW load through a 40MVA
system is common) [9].
The presence of overvoltages either requires costly 72kV class equipment to be used
[28], or the railway operator risks voiding the warranty of standard 52kV class
equipment. Furthermore, even if the equipment does not fail immediately, regular
overvoltages are likely to result in shortened life spans of the equipment due to
gradual degradation of equipment insulation [8]. Whilst new generation 'clean'
locomotives with four quadrant PWM drives are not likely to create an overvoltage
problem themselves, any thyristor-based locomotives on the system have the potential
to cause such harmonic overvoltages and the effect will be felt by all locomotives
running on the same system. Thus there are strong economic incentives to limit the
overvoltages in railway systems to lower levels.
Harmonic overvoltage is a complex process affected by a range of different
parameters. Over the years, harmonic overvoltage has been studied and reported by
different groups of researchers [9,13,19-21,28-30]. Some of the important general
conclusions are:
1. Although the transmission line consists of an infinite number of parallel resonant
frequencies, in reality only the lowest resonant frequency is ever excited because
circuit resistance provides a high damping factor at higher frequencies. Typically
resonance is likely to occur between l-2kHz.
2. The substation transformer leakage inductance and resistance, overhead
transmission line capacitance, transmission line length, and locomotive main
24
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
power transformer inductance all have significant effects on the resonant
frequencies and hence overvoltage values obtained.
3. Longer feeder sections have lower resonant frequencies and therefore higher
overvoltages.
4. The parallel resonant frequencies of the system do not change with locomotive
position, although the magnitudes of the resonance generally do [31].
2.6.2
Solutions to Harmonic Overvoltage
The standard approach of suppressing harmonic overvoltages is to install a track-side
passive damping filter, which works by effectively modifying the impedance
characteristics of the original system. A properly designed damping filter should
achieve a much reduced impedance peak at a slightly different and new resonant
frequency. It is generally recognised that the open end of the feeder section at the
track-sectioning cabin is the optimum location for the damping filter, as it is able to
provide acceptable performance under different feeding configurations (eg, even
during second emergency feeding) [9,20]. Although simple first order RC filters have
been reported in usage with satisfactory results [19,29,32,33], second order passive
filters based on a RLC high-pass arrangement tend to provide superior performance,
namely lower filter losses, lower component ratings and better elimination of
harmonic overvoltages [9,21].
2.7
SUMMARY
In this chapter the layouts of typical 25kV 50Hz railway systems and the main power
circuit of thyristor locomotives have been described. It has been shown that when
thyristor locomotives operate on a 25kV railway system, the pantograph voltage
becomes severely distorted. Three main power quality issues have been identified:
low rms value, low rectified average value, and harmonic overvoltages. The rms
voltage is depressed due to voltage drop along the feeding system. Although the X/R
ratio in. typical railway systems is relatively low, reactive power compensation is still
a promising and effective means of improving the rms voltage regulation. The loss of
25
CHAPTER 2:
The 25kV 50Hz Electrified Railway System
average voltage, indicated by a raised form factor above 1.11, is a low order harmonic
problem that can be mitigated by providing some filtering mechanism at the 3rd, 5th
and 7th harmonic frequencies. Finally harmonic overvoltages caused by the excitation
of system resonar
ad to result in prematare failure of connected equipment. There
are good economical incentives to have these three effects under control.
The next chapter will review the myriad of control strategies for STATCOM and
active power filters available in the literature, with the aim of identifying suitable
strategies for providing reactive power control and harmonic control.
26
CHAPTER 3: STATCOMs AND A CTIVE
POWER FILTERS
With the advent of self-commutated semiconductor switches of ever increasing
ratings, the development of high power electronic equipment has been occurring in
the last two decades under two broad categories, namely Flexible AC Transmission
Systems (FACTS) and Custom Power. At the high voltage transmission level,
deregulation of power industries around the world has prompted better utilisation of
existing power transmission infrastmctures closer to their thermal limits. This requires
more precise and rapid control over real and reactive power flow as well as the ability
to improve transient stability and damp power system oscillations. FACTS
controllers, the most well known of which include the Static Compensator
(STATCOM), Static Synchronous Series Compensator (SSSC) and Unified Power
Flow Controller (UPFC), have been developed to deal with these issues [34].
On the other hand, at the lower voltage distribution side of the power network, the use
of increasingly sensitive and sophisticated loads is forcing the end-users to become
more concerned with better power quality and reliability of supply. Thus harmonic
compensation, power factor correction, three-phase balancing and voltage regulation
are the functions sought after. Custom power solutions, or power conditioners as they
are sometimes referred to, such as Active Power Filter (APF), Distribution Static
Compensator (DSTATCOM), Dynamic Voltage Restorer (DVR) and Unified Power
Quality Conditioner (UPQC), have been proposed as a result [35].
The previous chapter has shown that the locomotive performance on 25kV systems
can be substantially improved by providing reactive power compensation as well as
mitigating the level of low order harmonics in the pantograph voltage. Whilst each of
the above controllers typically consists of multiple functions and many of these
functions do overlap, the STATCOM and APF have been chosen for a closer
examination in this chapter for their reactive power compensation [36-38] and
harmonic filtering properties respectively. This chapter first summarises the various
27
i vA
CHAPTER 3:
STATCOMs and Active Power Filters
topologies and control strategies proposed for a STATCOM. The chapter then surveys
the various control strategies available to an APF. The aim of the chapter is to identify
suitable control strategies for reactive power compensation and harmonic
compensation to be used for the development of a composite compensator suitable for
traction applications.
3.1
STATCOM OPERATING PRINCIPLE
The Static Compensator (STATCOM), also known in some of the earlier literatures as
the Static Condenser (STATCON) and Advanced Static VAR Compensator (ASVG),
represents the latest generation of shunt connected reactive compensation devices that
is capable of generating and/or absorbing a continuously variable amount of reactive
power. Fundamentally, what distinguishes the STATCOM from the previous
generation of TCR/TSC based reactive power compensators is that instead of using
large AC capacitors and reactors to generate and/or absorb reactive power, the
STATCOM employs a solid-state converter as a fundamental frequency voltage or
current source to directly generate the required reactive current and power.
The STATCOM typically consists of a voltage source inverter (VSI) coupled to the
AC power system via a coupling transformer, as shown in Figure 3.1 (a). The VSI is
essentially a controllable voltage source and can be controlled to generate a line
frequency voltage of any magnitude and phase angle (w.r.t. the system voltage). Thus
at the fundamental frequency the equivalent circuit of the STATCOM and AC system
can be shown as Figure 3.1(b), where the coupling transformer has been modelled by
its leakage inductance.
Power
Inverter
/YYY\
X
c
Transformer
AC busbar
(a)
(b)
Figure 3.1: VSI based STATCOM. (a) Schematic diagram (b) Single-line equivalent
circuit
28
CHAPTER 3:
STATCOMs and Active Power Filters
The real and reactive power flowing into the AC system are given by
(3.1)
(3-2)
where P = real power into AC system
Q = reactive power into AC system
X = reactance of coupling transformer
a = phase angle by which Vi leads Vs.
From (3.1), it is seen that the real power exchange between the STATCOM and AC
system can be controlled by a. Thus if Vi leads Vs (a positive), real power flows into
¥1
the AC system. Conversely if Vi lags Vs (a negative), real power flows into the
STATCOM inverter.
It is also apparent from (3.2) that reactive power flow is governed by the relative
i
magnitudes of Vs and Vj. Assuming a is small and hence c o s a « l , when Vj is
greater than Vs, reactive power is supplied into the system, ie. the STATCOM now
appears capacitive to the AC system. Conversely, when Vt is smaller than Vs, reactive
power is absorbed from the system, ie. the STATCOM now appears inductive to the
AC system. In practice, a is maintained at a small negative angle so that real power
flows into the STATCOM to replenish power losses in the STATCOM.
3.2
STATCOM TOPOLOGIES AND MODULATION STRATEGDXS
Figure 3.2(a) shows the basic two-level single-phase H-bridge suitable for singlephase STATCOM applications. For three-phase application, a separate single-phase
H-bridge can be used in each phase, although more commonly the three-phase Graetz
bridge shown in Figure 3.2(b) is used. The single-phase and three-phase VSIs consist
29
.>•?.'.
CHAPTER 3:
STATCOMs and Active Power Filters
SW4
SVV2
(a)
(b)
Figure 3.2: Basic two-level VSI topologies, (a) Single-phase H-bridge (b) Threephase Graetz bridge
of 2 and 3 parallel phase-legs respectively feeding off a DC bus, with each phase-leg
comprising of an upper and a lower solid-state power switch. An anti-parallel power
diode is also associated with each switch to allow for bi-directional current flow in
each phase-leg.
Although many other types of power electronic converters (eg. Current Source
Inverter (CSI)) are in principle suitable, the overwhelming majority of FACTS
devices proposed seem to favour the voltage source inverter (VSI) topology. Indeed,
the handful of high power STATCOMs (> 80MVAR) designed and installed to date
are all based on the VSI [39-42]. This is understandable, since the fixed DC supply of
the VSI can be economically achieved by batteries and capacitors and the requirement
of uni-directional switches in conjunction with their anti-parallel diodes in a VSI is
readily satisfied by the current generation of semiconductor switches such as GTOs,
IGBTs and BJTs.
The switches used in VSIs are self-commutated switches, meaning that they can be
turned ON and turned OFF at any time by asserting their corresponding gating
signals. When the upper switch in a phase-leg is turned ON, the output voltage of the
phase-leg attains VdC/2 (w.r.t. a fictitious midpoint of the DC bus). When the lower
switch in a phase-leg is turned ON, the output voltage of the phase-leg attains -Vdc/2.
Obviously any attempt to simultaneously turn ON both switches in the same phase-leg
would result in a short-circuit of the DC bus, a catastrophic situation to be avoided, hi
addition, if both switches in a phase-leg are simultaneously turned OFF, the phase
30
CHAPTER 3:
STATCOMs and Active Power Filters
output voltage will be determined by the direction of current flow, which is
undesirable for full control of the VSI output voltage. Therefore the two switches in a
phase-leg are switched in a complementary manner. By appropriately gating the
switches in a VSI under the above restrictions, approximations to a sinusoidal voltage
between the various phase-legs can be synthesised for any magnitude, phase and
frequency.
In STATCOM applications, the ultimate aim is to control the reactive power supplied
by the VSI, and this is directly dictated by the output voltage magnitude as shown in
the previous section. Therefore, the ability to control and vary the output voltage
magnitude, which is related to how the VSI switches are modulated, is a crucial issue.
There are two main ways of controlling or modulating the switches in a VSI to
produce sinusoidal voltage output, namely square-wave switching and pulse-widthmodulation (PWM) switching.
3.2.1
Square-Wave Switching
The great majority of the STATCOMs proposed and installed are based on the
fundamental frequency square-wave modulation strategy, rather than the PWM
alternative. The reason is that most STATCOMs are targeted at applications from a
few tens to over a hundred MVAR, and at these power levels the switching frequency
of currently available semiconductor switches is severely limited.
With square-wave switching, each of the phase-legs of the VSI is toggled between the
upper and the lower supply rails at the 50Hz fundamental frequency, to produce
output square waves that are displaced by 180° for the single-phase VSI or displaced
by 120° for the three-phase VSI. For the single-phase VSI, the resultant line-to-line
voltage is a 50Hz square wave switching between ±VdC, which can be expressed as the
Fourier series:
dc
-sin(5a>t)
(3.3)
71
31
CHAPTER 3:
STATCOMs and Active Power Filters
whereas the resultant line-to-neutral voltage waveform for the three-phase VSI is a
six-step waveform and can be expressed as:
2V [
11
von =
= —— \{sin(a)t) +-5s-i
1
-sin(7 cot)
7
(3.4>
where a> = fundamental frequency in rad/s.
There are two basic shortcomings associated with square-wave switching of VSIs.
Firstly, as indicated by (3.3) and (3.4), in addition to the desired fundamental
frequency component, the output voltage also contains a significant amount of low
order harmonic components. Direct usage of the basic two-level VSIs shown in
Figure 3.2 would thus result in an unacceptable level of harmonic current into the
system.
To achieve adequate harmonic performance and also to obtain the voltage and current
ratings required in high-power transmission applications, multiple units of the basic 6pulse bridge shown in Figure 3.2(b) are in practice combined magnetically using a
special phase-shifting transformer to cancel selected harmonics and thereby arriving
at topologies with a higher pulse number. In general N numbers of 6-pulse bridges
can be combined to obtain a 6N-pulse unit where only harmonics of order 6Nk±l,
k=l,2,3... are present. At least a pulse number of 24 is required for transmission line
applications to achieve a satisfactory harmonic performance without an additional
passive filter [43]. 12-pulse converters can be easily constructed using star and delta
windings [44-47]. While uses of up to a 48-pulse converter have been reported for a
±80MVAR and a ±100MVAR STATCOM [40,41], phase-shifting transformers for a
pulse number higher than 12 are generally complicated with no standard design
information readily available.
An alternative to using multi-pulse circuits for better harmonic performance and
higher power rating is to use multi-level inverter topologies. Multi-level inverters are
usually used in combination with pulse-width-modulation in industrial drive
applications, but they have recently been proposed to operate with square-wave
32
CHAPTER 3:
STATCOMs and Active Power Filters
modulation for STATCOM applications [39,48,49]. Multi-level inverters avoid the
design of complicated phase-shifting transformer, but have been shown to give a
slightly inferior harmonic performance for a given number of active switches
compared to the more established multi-pulse configurations [47] for STATCOM
applications.
The second inherent drawback associated with square-wave switching is that the
magnitude of the fundamental output voltage is fixed for a given DC bus voltage, as:
2V2
rmsV-l)
Vdc
for single - phase VSI
n
(3.5)
Vdc
for three - phase VSI
n
where
i) = line-to-line rms value of fundamental component of output voltage
= DC bus voltage
With this kind of modulation strategy, output voltage magnitude control is achieved
by raising or lowering the DC bus voltage, which in turn is accomplished by varying
the phase angle a of Vi with respect to Vs. In the steady state, a has a small negative
value, so that a small amount real of power flows into the STATCOM to replenish
power losses in the system. When the output voltage magnitude needs to be increased,
a is made more negative to increase the real power into the STATCOM. The extra
real power will charge the DC capacitor and thus raise its voltage. On the other hand,
if a lower output voltage is required, a is made leading so that real power is forced
out of the STATCOM, thus discharging the DC capacitor.
The implication of this modulation strategy is that because the charging and
discharging of the DC capacitor is involved, the transient response of the STATCOM
is rather limited [50,51]. The size of the DC capacitor in this kind of converter is
therefore often a careful compromise between transient response speed and harmonic
ripple performance.
33
CHAPTER 3:
STATCOMs and Active Power Filters
i
Direct control of the fundamental output voltage magnitude is actually possible at a
constant DC bus voltage. This is achieved by pulse-width-modulating the square wave
at the fundamental frequency to produce quasi square waves. This effectively removes
the dynamics of the capacitor from the reactive power control loop and improvement
in the dynamic response can be achieved. This method has in fact been used in a
couple of instances [41,52]. However, for similar level of harmonic performance,
these quasi square wave generation methods require twice the number of active
switches [47], and thus have never been able to enjoy wide popularity.
3.2.2
PWM Switching
Pulse Width Modulation (PWM) is the process of using rapid semiconductor switch
transitions to convert electrical energy from an electrical supply into a series of high
frequency output pulses that represent a target average low frequency waveform.
The simplest and most widely used PWM strategy is the carrier-based sine-triangle
comparison technique. Here, a target sinusoidal fundamental reference is compared
against a high frequency triangular carrier. When the reference value is more positive
than the carrier value, the phase-leg is switched to the positive rail creating a positive
output pulse. When the reference value is less than the carrier value, the phase-leg is
switched to the negative rail creating a negative output pulse. The result is a train of
pulses with (near) sinusoidally varying widths, as shown in Figure 3.3. It can be
shown analytically that the output waveform contains the required low frequency
target fundamental component, plus high frequency components centred around
multiples of the carrier frequency [53,54].
With PWM, the magnitude of the output fundamental voltage magnitude is directly
proportional to the magnitude of the reference waveform, and thus can be directly
controlled. In fact the output voltage magnitude can be controlled from zero up to a
maximum value of:
34
CHAPTER 3:
STATCOMs and Active Power Filters
Fundamental
Target
Triangular
Carrier
* • Time
i,
i
•• Time
High Frequency Switched Equivalent of Fundamental Target
Figure 3.3: Principle of sine-triangle PWM generation
Vdc
for single - phase VSI
(3.6)
max V.rms(l-l)
Vdc
for three - phase VSI
Note that for a given DC bus voltage, the maximum achievable fundamental output
voltage is significantly lower than if square wave modulation is used.
PWM is able to provide direct, independent control of output voltage magnitude and
phase angle. This not only greatly simplifies the controller design, but also has
potentially better dynamic performance since control dynamics are not affected by the
DC capacitance. In addition, there are no low order harmonics generated in the output
waveform, but instead only switching harmonics at multiples of the carrier frequency
are present. These can be more economically filtered since they are at much higher
frequencies. As with square-wave modulation, the use of multi-level inverters allows
greater power ratings to be achieved and also further improves on the harmonic
performance.
35
CHAPTER 3:
STATCOMs and Active Power Filters
Despite its many advantages, it is generally considered uneconomical and technically
challenging to build PWM converters with currently available power semiconductor
switches for transmissi^' i level applications where power ratings upwards of tens of
MVAR are required. High power PWM converters have thus been mainly restricted to
large industrial drive applications. However, in the last few years, advancements in
ratings of Insulated Gate Bipolar Transistor (IGBT) and Integrated Gate Commutated
Thyristor (IGCT) have renewed interests for PWM based STATCOMs to be used at
the distribution level [50,51,55-65] to solve a range of power quality problems.
3.3
STATCOM CONTROL STRATEGIES
The control strategy adopted forms an important part of a power conversion system as
it directly determines the functionality and performance of the system. The controller
for most STATCOMs adopts a two-level structure, consisting of a fast inner current
loop and a (relatively) slow outer control loop. An inner current loop is not mandatory
but it tends to give better dynamic performance [66] and also allows current limits to
be easily incorporated into the controller.
3.3.1
Outer Control Loop
The structure of the outer control loop is very much determined by the intended
functionality of the particular STATCOM. By controlling reactive power flow into
and out of the connecting system, a STATCOM becomes a versatile equipment
capable of many functions. These include voltage regulation, VAR compensation,
power oscillation damping, transient stability improvement, 3-phase load balancing,
!
load compensation, flicker control and even harmonic compensation (if high
frequency PWM is used) [36]. Generally two types of outer control loop structure can
be identified.
The first type of control loop is mainly adopted by transmission system STATCOMs,
whose main function is usually voltage regulation [23,37,38,40,44,45] but also often
has supplementary functions of power oscillation damping and transient stability
improvement. Figure 3.4 shows such a STATCOM with its typical outer control loop
structure.
36
CHAPTER 3:
STATCOMs and Active Power Filters
The 3-phase set of instantaneous AC bus voltages voa, vob, VDC to which the
STATCOM is connected is measured and transformed into a synchronously rotating
frame. A Magnitude Calculator then calculates the AC bus voltage magnitude, which
is subtracted from a set voltage reference VR* to generate the voltage error Verr. As
shown, the demanded bus voltage VR* is usually modified by a droop factor K^oop to
Transmission Feeder 2
'L2
STATCOM
(a)
droop
Voltage Controller
G(s)
Afor jPdt
Frequency
Variation or Power
Flow Measuring
Magnitude
Calculator
Circuit
V
"Dd
Vn
*U
(b)
Figure 3.4: Transmission system STATCOM. (a) Circuit arrangement (b) Typical
outer control loop structure
37
CHAPTER 3:
STATCOMs and Active Power Filters
create a drooping terminal characteristic, rather than a perfect flat one. This is to
extend the regulation range of the STATCOM and also to help avoid oscillation under
certain unfavourable circumstances. Finally the voltage error Ven is amplified and
processed by the voltage controller, typically a PI block, to generate the
reactive/quadrature current demand Icq* which is to be acted upon by the inner current
loop.
To provide pure voltage regulation and transient stability improvement, the voltage
reference VR* is set equal to a fixed DC value VR. If in addition power oscillation
damping is required, then either frequency variation Af or variation of the real power
flow j\Pdt is measured and used to modulate VR* about the quiescent set point VR.
I
This varies the STATCOM terminal voltage in a direction that opposes any power
oscillations and thus damps them out quicker.
s
j
The second type of control loop is typically employed by distribution level DSTATCOMs, serving one particular end-user and whose main functions include load
compensation and balancing, pov/er factor correction, flicker control and harmonic
compensation [56,59,60,64,67]. Figure 3.5 shows such a STATCOM with its typical
outer control loop structure.
The outer control loop shown in Figure 3.5(b) has the ability to provide power factor
correction and voltage flicker control. Firstly the 3-phase load currents are sensed and
transformed into a synchronously rotating d-q frame. The quadrature load current ILq,
representing the reactive component of the load current is used as the reactive
reference current Icq .
This type of STATCOMs is usually PWM based, and therefore the DC bus capacitor
voltage needs to be kept relatively constant. This is done by comparing the DC bus
voltage Vdc with a reference value VdC*, the difference of which is processed by the
DC bus controller GdC(s) to generate a real current reference Ic<j*. The DC bus
controller is usually of the proportional-integral (PI) type to achieve zero steady-state
error. Finally the direct and quadrature current references are transformed back to the
38
CHAPTER 3:
STATCOMs and Active Power Filters
Distribution Feeder
STATCOM
(a)
i
i
1
Figure 3.5: Distribution level, load specific STATCOM. (a) Circuit arrangement (b)
Typical outer control loop structure
a-b-c coordinates in the form of 3-phase instantaneous compensator current references
ica*, icb* and icc* and then passed on to the inner current loop.
Harmonic current compensation can also be achieved if suitable filter blocks are used
in the synchronous frame to process the load current 1^ and iLq signals. In doing so,
the STATCOM effectively acts as an active power filter. Details of this function are
discussed in the APF section of this chapter.
39
CHAPTER 3:
3.3.2
STATCOMs and Active Power Filters
Inner Current Loop
The VSI is inherently a controllable voltage source with a negligible amount of
thevenin equivalent impedance. For a given switch gating sequence, a fixed voltage
output is obtained between the terminals of the VSI. For many applications including
STATCOM, it is desirable to control directly the VSI output current rather than the
voltage. In this case an inner current loop for the VSI is required. With the help of
feedback control, the inner current loop takes in a current reference and controls the
VSI output voltage in such a way so that the VSI output current tracks the demanded
current reference.
i
For STATCOM applications, two main types of inner current loops have been
proposed, depending on whether the VSI employs fundamental frequency square
modulation or high frequency PWM.
With square-wave modulation, the only dynamically controllable variable is a, the
phase angle of the fundamental VSI output voltage with respect to that of the system
at the point of coupling. The control loop structure is shown in Figure 3.6.
Design of the current controller C(s) is not as straightforward as it seems, because the
relationship between a and Icq is strongly non-linear. This was first studied by
AT
Schauder et al. [68] who found that the linearised open loop transfer function
(*\
Aa(s)
has a pair of complex zeroes that moves along the imaginary axis as a function of the
injected reactive current. The implication is that a conventional linear PI controller for
Current
Controller
C(s)
->N.
a
+CSS\
Gate
Pattern
Logic
N
Gating \
Signals , /
VSI
e
\
d-q
a-b-<
J JJ
e
Phase
Locked
Loop
DJ
v
oJ
Figure 3.6: Inner current loop for square-wave modulation VSI
40
CHAPTER 3:
STATCOMs and Active Power Filters
C(s) cannot be used, as it would tend to result in instability in the inductive region.
Schauder showed that with non-linear feedback in addition to a PI controller,
excellent results can be obtained. This has since been accepted as the standard
controller for square-wave modulation type VSI, although it was later shown by
Padiyar [69] that a controller based on fuzzy logic tends to be more robust against
changes in system parameters.
On the other hand, for STATCOMs using PWM based VSIs, synchronous frame PI
and hysteresis current regulation schemes have been proposed. However, this does not
preclude the use of other standard current regulation techniques for VSI. As current
regulation of a PWM VSI is a rather important aspect of an APF, it will be discussed
later in this chapter.
3.4
ACTIVE POWER FILTER OVERVIEW
With the advent of power electronics technology, there has been a proliferation of
non-linear loads connected to the power distribution system. These include static
power converters, arc furnaces, adjustable speed heating, ventilation, and computers
for data processing and office automation. All these items employ switched mode
type power electronic converters that inherently draw excessive harmonic currents.
Harmonic current components result in voltage distortion, increased power system
losses, cause excessive heating in rotating machinery, can create significant
interference with communication circuits, and can generate noise on regulating and
control circuits causing erroneous operation of such equipment.
Conventionally, passive filters consisting of a bank of tuned LC filters and/or a highpass filter are installed in the vicinity of the non-linear loads to absorb the harmonic
current and to improve the load power factor. However, in practice these second order
passive filters have the following drawbacks [70]:
i)
The filtering characteristic is very dependent on the source impedance, which
is itself usually not accurately known and varies with system configuration.
41
CHAPTER 3:
ii)
STATCOMs and Active Power Filters
The capacity of the filter must be rated by taking into account both the
harmonic and the fundamental current components that flow into the filter.
iii)
There is no control over the amount of harmonic current flowing into the
passive filter, so filter overload can occur when the harmonic current
components increase.
iv)
The passive filter may parallel resonate with the power system, causing
amplification of harmonic currents on the source side at a specific frequency.
v)
The passive filter may series resonate with the power system, so any source
voltage distortion produces excessive harmonic currents flowing into the
passive filter.
Motivated by these shortcomings of passive filters, use of an active power filter (APF)
was first proposed in the early 1970s [71]. Active power filters overcome the above
disadvantages of passive filters, but they are usually more expensive and require more
design effort. They did not attract much attention until the mid 1980s when fast
switching devices like the bipolar junction transistor (BJT) and insulated gate bipolar
transistor (IGBT) began to appear with sufficient ratings. Active power filters have
been one of the most hotly researched areas of power electronics in the past decade
and continues to be so.
APF design is a rather complex topic covering many interrelated aspects such as:
•
Choice of power inverter topology (eg. VSI, CSI, multilevel, etc);
•
Choice of APF topology (eg. shunt, series, hybrid, etc.);
•
Design of switching ripple filter;
•
Sizing of coupling inductance;
•
Sizing of DC bus capacitor for VSI;
•
Choice of PWM and current regulation scheme;
•
Choice of feedback/measured quantities;
9 Choice of harmonic extraction algorithms;
42
CHAPTER 3:
•
STATCOMs and Active Power Filters
Choice of digital or analog implementations.
All of the above aspects have a direct bearing on the functionality, performance and
cost of the resultant APF. Indeed, a wealth of materials regarding APFs can be found
in the literature, each providing small variations and/or improvements on certain
aspects. Thus it can be quite a challenge to select a suitable compensation scheme for
a particular design goal. This section of the chapter intends to provide an objective
classification of state-of-the-art APFs on three levels, namely by their topology, by
their control detection method, and by their harmonic extraction algorithm.
Categorising APFs in this way establishes a framework from which a set of suitable
topologies and control strategies for traction applications can be quickly identified.
Note that although most of the active power filters discussed in the literature are for a
three-phase system, many of these concepts are directly applicable to a single-phase
system, which is the system of interest in this thesis. The following review on active
power filters will therefore cover both three-phase and single-phase techniques with
equal emphasis.
3.5
ACTIVE POWER FILTER TOPOLOGIES
All active power filters are based on either a controlled voltage source or a current
source, capable of generating fundamental and harmonic voltages and currents
respectively. This can be implemented using either a voltage source inverter (VSI)
[70] or a current source inverter (CCI) [72], using PWM. The former uses a capacitor
as the energy storage element on the DC-s J.e and acts inherently like a non-sinusoidal
voltage source. The CSI uses an inductor on the DC side and acts like a current
source. The VSI can be controlled to be a current source by having an inner current
loop to control the output current. This is usually preferred over the CSI because the
VSI has higher efficiency and requires only a fixed DC link voltage smoothed by a
capacitor.
The typical active filtering scenario is depicted in Figure 3.7. The non-linear load,
typically a rectifier type load, draws a current i^ which is rich in harmonics. Without
any filtering schemes, the source current is, which equals 1L and hence contains
43
CHAPTER 3:
STATCOMs and Active Power Filters
Non Linear
Load
Figure 3.7: Active power filter compensation scenario
harmonic components, will flow straight into the source, polluting the rest of the
power system. If the source inductance Ls as seen by the non-linear load is large, the
voltage seen by the non-linear load VD will also be distorted as a result of the
harmonic voltage drop across Ls. The common objective of active power filters is to
ensure that the source current is contains zero or minimal amount of harmonic
components. Furthermore, the non-linear load usually absorbs a significant amount of
fundamental reactive power. Therefore a usual secondary objective of an active power
filter is to ensure that the fundamental component of is is in-phase with VD-
Three types of active power filter topologies can be identified, namely the shunt
active power filter, series active power filter and hybrid active power filter system.
They mainly differ by how they are connected to the system to achieve slightly
different compensation characteristics. The basic principles of these active power
filters are discussed in detail in the following subsections in the context of the above
compensation scenario.
3.5.1
Shunt Active Power Filter
The shunt active power filter is the most basic, widely studied and implemented active
power filter topology. It consists of an active power filter connected in parallel to the
distorting non-linear load, as shown in Figure 3.8(a). The shunt active power filter
acts as a controlled current source, as shown in the equivalent circuit in Figure 3.8(b).
It is controlled so that it supplies all the harmonic components of IL, and therefore by
Kirchhoff s current law i s can be made free of harmonics. The active power filter
function is often quoted in the literature as 'to draw an equal but opposite (harmonic)
current to the load current', depending on the filter current reference direction shown.
In addition, if the active power filter is controlled to supply the fundamental
44
CHAPTER 3:
STATCOMs and Active Power Filters
Non Linear
Load
(a)
Active
Power Filler
t>
(b)
Figure 3.8: Shunt active power filter, (a) System configuration (b) Per phase
equivalent circuit
frequency reactive component in iL, then is contains only the fundamental active
component which is in phase with VD, and thus the non-linear load appears with unity
power factor.
The shunt active power filter has its limitations. Peng [73-75] has shown that
harmonic generating loads can be roughly divided into two categories: current source
non-linear loads and voltage source non-linear loads.
Current source non-linear loads are loads where the harmonic content of the AC load
current is a characteristic of the load parameters and largely independent of the source
side impedance, while the AC load voltage is strongly influenced by the source
impedance. A typical example of this type of load is a thyristor rectifier followed by a
large DC inductance. This type of load has large Thevenin equivalent impedance, and
can be modelled by an equivalent harmonic current source, as is done in Figure
3.8(b).
On the other hand, voltage source non-linear loads are loads where the harmonic
contents of the AC load voltage are a characteristic of the load parameters and largely
independent of the source side impedance, while the AC load current is strongly
influenced by the source impedance. A typical example of this type of load is a diode
rectifier followed by a large DC capacitance. This type of load has small Thevenin
equivalent impedance, and can be modelled by an equivalent harmonic voltage
source.
45
CHAPTER 3:
STATCOMs and Active Power Filters
Peng showed that the shunt topology is only effective against current source nonlinear loads. When attempting to compensate voltage source non-linear loads, ii tends
to increase the harmonic load current and hence the required VA rating of the active
power filter. One way around this problem is to insert a series inductance before the
load to increase the effective load impedance. Although this leads to improved
harmonic compensation characteristics, the fundamental voltage drop across the
inductance decreases the performance of the load and thus may not represent a
satisfactory solution.
3.5.2
Series Active Power Filter
The series active power filter is the dual of the shunt topology. It consists of an active
power filter connected in series with the supply before the non-linear load, as shown
I
in Figure 3.9(a). The series active power filter acts as a controlled voltage source, as
shown in the equivalent circuit in Figure 3.9(b). It is controlled to present zero
impedance at the fundamental frequency, but a large impedance at harmonic
frequencies so that no harmonic current flows into the source. Peng has shown that
the series topology is particularly suited to deal with voltage source type non-linear
loads, ie. loads with small Thevenin equivalent impedance.
Non Linear
Load
(a)
Active
Power Filter
(b)
Figure 3.9: Series active power filter, (a) System configuration (b) Per phase
equivalent circuit
i!
46
CHAPTER 3:
3.5.3
STATCOMs and Active Power Filters
Hybrid Active Power Filter Systems
The main drawback of the basic shunt and series topologies is that VA rating of the
inverter is large. In the shunt topology, the inverter has to withstand the full load
fundamental voltage, whereas in the sent s topology the inverter has to pass the full
fundamental load current. Therefore these two basic topologies can be potentially
expensive. As a result many hybrid topologies consisting of series/parallel
combinations of active and passive RLC filters have been proposed since the late
1980's to take advantage of the superior compensation characteristics of active power
I
filters and the lower cost per VA of passive filters. All hybrid topologies share a
common goal of reducing the rating of the active element in one way or another.
Using different series/parallel combinations of active and passive elements, many
hybrid topologies are possible. Peng showed 18 useful hybrid topologies [75], each
with its own unique characteristics. Senini later demonstrated systematically that with
one active and one passive element, 8 electrically valid configurations are possible
[76]. By extending to one active and two passive elements, another 18 new
configurations are possible. Despite the great number of theoretically possible hybrid
topologies, only three have been studied in any de.ail in the literature [77]. They are
the shunt hybrid parallel topology [71,77,78], series hybrid parallel topology [79-85],
and the hybrid series topology [86-91]. These are described in the following
paragraphs. Other more exotic topologies such as the hybrid parallel with C/L voltage
divider [92] and topologies containing two active elements such as the unified power
quality conditioner (UPQC) [93] are available but will not be discussed as they serve
special functions that are beyond the scope of this thesis.
Shunt Hybrid Parallel Topology
The shunt hybrid parallel topology consists of a shunt active power filter and a shunt
passive filter both connected in parallel to the distorting non-linear load, as shown in
Figure 3.10. The active power filter is controlled as a harmonic current source, as in a
pure shunt active power filter. The active and passive elements are designed to share
compensation in the frequency domain. Typically for a three-phase system, the active
power filter is controlled to compensate only for the 5th and 7th harmonics in IL The
passive filter is a RLC high pass filter designed to sink the 11th, 13th etc harmonics in
47
CHAPTER 3:
STATCOMs and Active Power Filters
iL and perhaps also absorb the high frequency switching components from the active
power filter. This is considered good responsibility sharing as the bandwidth of the
active power filter is dictated by the PWM switching frequency and it is more costly
to operate the active power filter at high switching frequencies. On the other hand
passive filters are better suited for higher order harmonic compensation because the
inductance and capacitance values required decrease at higher frequencies, thereby
resulting in decreased cost and p> lysical size.
One potential problem with this hybrid topology is that the compensating current from
the active power filter may flow into the passive filter [71,86], decreasing the
compensation performance and possibly overloading the passive filter. This can
happen when the high pass filter does not have a sharp cut-off at the low frequency
end, or when the harmonic reference generation algorithm used for the active power
filter control is not selective enough. Under such circumstances the passive filter
I
presents a low impedance at the harmonic frequencies that the active power filter is
trying to compensate. Consequently for this topology it is important that the active
and passive elements have a well-defined (ie. non-overlapping) role in the frequency
domain [73].
i
Depending on the control detection method used, the presence of background
harmonics in the supply voltage may present some problems for this topology. The
'APF
Non Linear
Load
Active
Power Filter
Figure 3.10: Shunt hybrid parallel topology with shunt active and shunt passive
elements
48
CHAPTER 3:
STATCOMs and Active Power Filters
most common control detection method used for the shunt active power
topology is the load current detection method (see Subsection 3.6.1). When this
method is employed, the active power filter will only compensate for the low order
harmonics in the load current IL. When a source harmonic voltage is present, this
forces the passive filter alone to absorb the harmonic current from the source
[71,73,86], potentially resulting in unequal sharing of compensation. For this reason
this type of hybrid filter system is not particularly suitable for systems where a
significant amount of background distortion is present in the source voltage.
Series Hybrid Parallel Topology
The second type of hybrid parallel topology consists of a parallel branch of passive
and active elements connected in series, as shown in Figure 3.11 (a). In this topology,
the active filter is controlled as a voltage source. The operating principle of this
topology can be best understood by considering the function of the active power filter
as trying to improve the filtering characteristics of a conventional passive filter
[81,84].
To sink harmonic load currents, the passive filter usually consists of tuned arms at the
5th and 7th harmonic and possibly a high-pass arm as well. Without the active power
filter, the filtering performance of the passive filter is very much dependant on the
relative size of the source impedance and the filter branch impedance at the harmonic
I
,. ru>
Active
Power Filter
(a)
(b)
Figure 3.11: Series hybrid parallel topology with series connection of active and
passive elements, (a) System configuration (b) Per-phase harmonic equivalent circuit
as seen by the load current when vAPF
=K-iSh
49
i
, V
} *
: < /A
CHAPTER 3:
STATCOMs and Active Power Filters
frequency. To achieve good filtering, the filter harmonic impedance has to be
significantly smaller than that of the source. This can be difficult to achieve in the
case of a stiff supply, and even if this can be achieved, component values do drift as
they age. An equally serious problem is that when the passive filter is tuned to present
a low impedance at the dominant load harmonic frequencies of say 5th and 7th, it will
often form a series/parallel resonance with the source impedance at some lower
frequencies [91], thus amplifying other load current and source voltage harmonics.
This is when the addition of the active power filter connected in series with the
1
passive filter will help.
In the most basic and common implementation of this hybrid topology, the source
current is is measured and the active power filter is controlled to output a voltage VAPF
proportional to the harmonic component in is:
V
APF
(3.7)
where ish = harmonic component extracted from is
K = proportional constant
With some algebraic manipulations, it can be shown that to the harmonic load current,
the active power filter behaves as a K (Q) resistor in series with the source impedance
[81]. The harmonic equivalent circuit is shown in Figure 3.1 l(b). Thus by selecting a
large enough constant K, the active power filter increases the source harmonic
impedance and therefore diverts all harmonic load currents of interest into the passive
filter branch. Also the presence of resistor K tends to damp away any series/parallel
I
\
s
resonance of the passive filter with the source impedance [81,86]. Thus the hybrid
topology improves the compensation characteristics of the passive filter whilst
removing the threat of any resonance. It should be noted that the action of the active
power filter is quite different from simply adding a real resistor K to increase the
effective source impedance. A real resistor is not frequency selective, and will
increase the power loss at the fundamental frequency. However, the active power
filter only acts on selected harmonics of is, as determined by the harmonic extraction
50
CHAPTER 3:
STATCOMs and Active Power Filters
algorithm used, and hence behaves as a resistor only at those harmonic frequencies.
The active power filter does not act on the fundamental frequency component of is.
In comparison to a pure shunt active power filter, the VSI absorbs the same amount of
harmonic current. However, in this hybrid topology the VSI no longer sees the full
fundamental line voltage, as most of this is dropped across the passive filter. The VSI
only needs to maintain a small fundamental frequency voltage to regulate the amount
of real power into the VSI to compensate for power losses in the inverter. Thus the
VA rating of the VSI in the hybrid topology is considerably reduced.
This second form of hybrid parallel topology is also able to supply a controllable
amount of reactive power at fundamental frequency for the purpose of power factor
correction. The tuned passive filter is capacitive at the fundamental frequency. By
controlling the fundamental voltage across the active power filter, the fundamental
voltage drop across the passive filter and hence the generated reactive power can be
varied [83,84].
The advantages of this hybrid topology are that they can be readily retro-fitted to
existing passive filters, and also allow easy protection of the active power filter as
with all shunt connected elements [77]. In addition, this topology is particularly
effective in dealing with a stiff supply system, since it works by increasing the
effective source harmonic impedance.
Hybrid Series Topology
Finally, the third major type of hybrid topology consists of a series active power filter
as well as a shunt passive power filter connected in parallel with the non-linear load,
as shown in Figure 3.12(a). The series active power filter is controlled as a voltage
source, as for a pure series active filter. The most common form of control detection
method used for this topology is again given by equation (3.7). It can be shown that
this results in the same harmonic equivalent circuit as for the hybrid parallel topology
depicted in Figure 3.11(b) [86]. In other words, the active power filter behaves as a
resistor K in series with the source impedance at the harmonic frequencies of interest,
but provides zero impedance at the fundamental frequency. Thus the active power
', i
51
CHAPTER 3:
STATCOMs and Active Power Filters
'Sh
Active
Power Filler
..
...
(a)
(b>
Figure 3.12: Hybrid series topology with series active and shunt passive elements, (a)
System configuration (b) Per-phase harmomc equivalent circuit as seen b y the load
current when
=K •i
Sh
filter serves to provide harmonic isolation between the source and the load, forcing all
harmonic load currents into the passive filter. Again, due to the presence of an
effective damping resistor K, the passive filter cannot easily resonate with the source
impedance.
The advantage of the hybrid series topology in Figure 3.12 over the hybrid parallel
topology in Figure 3.11 is that the VA rating of the filter system is much less sensitive
to the presence of source voltage distortion [89]. In fact Libano et al. [86] showed that
the source voltage distortion vSh is present almost in full in the load terminal voltage
voh for the hybrid parallel topology, but does not appear in voh for the hybrid series
topology. However, as with all series connected equipment, protection is much more
difficult for the hybrid series topology. Furthermore, although fixed power factor
correction can be readily provided by the passive filter's capacitance at the
fundamental frequency, the hybrid series topology is unable to provide a dynamically
varying amount of reactive power in response to a fluctuating demand.
3.6
ACTIVE POWER FILTER CONTROL DETECTION METHODS
All active power filters, regardless of topology, have at their heart a controllable
voltage or current source that needs to be explicitly controlled according to certain
control laws to achieve the desired compensation objectives. Being active devices,
52
CHAPTER 3:
STATCOMs and Active Power Filters
active power filter systems measure the current state of the system to determine the
appropriate instantaneous reference output voltages to apply or currents to inject. This
process is frequently referred to as reference generation. There are two important
aspects of reference generation: the measurement or detection of an appropriate
system variable, and the application of a harmonic extraction algorithm to the
detected system variable in order to generate an instantaneous voltage or current
reference template for the VSI. These two aspects of reference generation are
considered in this section and in the next respectively.
For a given active power filter topology, there may be more than one possible system
variable it can measure for control purposes, hi other words, there can be more than
one control detection method available. The control detection method, together with
liie harmonic extraction algorithm used (see Section 3.7), strongly influences the
compensation characteristics as well as steady-state and transient performance of the
active power filter. For the hybrid series topology mentioned in the last section, the
active power filter control system measures or detects the source current is and
outputs a voltage according to the control law given in equation (3.7), in an attempt to
minimise the harmonics in i$.
Despite its relative cost, the basic shunt topology is arguably the most practical and
versatile active power filter, judging from the large amount of work published in the
literature. Accordingly, as many as four major types of control detection methods
have been proposed and shown to give good compensation characteristics. They are
load current detection [70,94-98], source current detection [77,78,99,100], voltage
detection [77,101-111], and the DC bus voltage detection method [112-116]. These
approaches are discussed in turn in the following subsections. To a lesser extent,
choices of detection method are available for other topologies as well, but will not be
discussed here.
3.6.1
Load Current Detection Method
With reference to Figure 3.8(a), load current detection uses the control law:
53
CHAPTER 3:
STATCOMs and Active Power Filters
l
APF
(3.8)
~ lLh
where im = harmonic components in \i to be compensated
Thus with the load current detection method, the load current iL is measured and its
harmonic components iui are extracted and used directly as the active power filter
current reference, as illustrated in the control schematic shown in Figure 3.13(a). The
active power filter contains an appropriate inner current loop that ensures that the
actual filter current iAPF tracks the reference IAPF* as closely as possible (see Section
3.8 for current regulation). The harmonic extraction algorithm used here to extract im
from iL usually has a notch characteristic designed to remove the fundamental
frequency component. Many algorithms are possible and these are discussed further in
Section 3.7. The operating principle of this detection method is straightforward.
Ultimately, all shunt active power filters need to somehow null the harmonic
components in the load current, so that the source only needs to supply the
fundamental current component. The load current detection method achieves this
directly by measuring the load current and feed-forwarding the harmonic components
as a current reference for the active power filter.
Inner Current Loop
Harmonic
Extraction
Algorithm
f
Current
Controller
APF
'APF^
(a)
APF
(b)
Figure 3.13: Load current detection, (a) Control schematic (b) Control system block
diagram
54
CHAPTER 3:
STATCOMs and Active Power Filters
The entire control system block diagram is shown in Figure 3.13(b), where Gcs(s) is
the current sensor which is represented by a first order lag with time constant Tcs,
GHE(S)
represents the harmonic extraction algorithm and Gic(s) represents the inner
current control loop. As shown, because only feedforward is involved and there is no
feedback path, system stability is automatically guaranteed when the individual
transfer functions are stable, which they always are.
This is the most basic and often cited control method for a shunt active power filter.
Notwithstanding its control simplicity, excellent compensation performance can be
achieved if properly implemented. When a disturbing load or a group of disturbing
loads can be clearly identified and needs to be compensated, the load current detection
represents the simplest and most cost-effective way. This method potentially has the
fastest transient response to sudden load parameter changes, as it detects the load
current directly. With this detection method, reactive power compensation can also be
easily achieved by removing only the fundamental active component, and leaving the
fundamental reactive component as well as the harmonic components in im-
There are however a number of issues that need to be carefully addressed when using
load current detection. Firstly, the method relies on the ability of the active power
filter to supply the load current harmonics iLh as soon as they are generated in the load
current IL. Compensation performance is thus sensitive to the delays in the
feedforward path [78,117]. Any delay would result in significant harmonic residuals
in the source current in the steady state, since there is no feedback mechanism to
correct this error. The delays mainly come from computational delay and finite
bandwidth of the inner current loop, and to a lesser extent the current sensor. The use
of modern digital signal processors (DSP) further exacerbates this problem as they
introduce significant processing delay and sampling delay. Phase-lead compensation
[99] and adaptive predictive controls [72,118] have been shown to be effective in
reducing the impact of these delays and thus improve the filter performance.
The second issue with load current detection is that it is inherently unable to
compensate for any source voltage distortion. This may or may not be a problem
depending on the intended purpose of the filter.
55
CHAPTERS:
3.6.2
STATCOMs and Active Power Filters
Source Current Detection Method
With reference to Figure 3.8(a), source current detection uses the control law:
(3.9)
where K = a proportional constant
ish = harmonic components of i s to be compensated
Thus with the source current detection method, the source current is is measured and
its harmonic components ish are extracted and multiplied by a gain K, and used
directly as the current reference, as illustrated in the control schematic in Figure
3.14(a). The entire control system block diagram is shown in Figure 3.14(b) with the
notations as before. The compensation characteristics for this detection method can be
evaluated from the closed loop transfer function:
(3.10)
Inner Current Loop
Harmonic
Extraction
Algorithm
'Sh
'APF
K
Current
Controller
'APF
i
(a)
'APF
Glc(s)
w
K
'Sh
G
(,).
»
(b)
Figure 3.14: Source current detection, (a) Control schematic (b) Control system block
diagram
56
CHAPTER 3:
STATCOMs and Active Power Filters
It can be seen that the ideal compensation of ish = 0 can be achieved as K approaches
oo. In practice good results can be achieved by choosing a reasonably large value for
K. The value of K is often a compromise between steady-state performance and
system stability constraints, as in all feedback control systems. The open loop transfer
function
ol
= K- Gcs • (s) • GHE (s) • G
(3.11)
K
needs to be examined on a case by case basis to determine the stability of the system.
The source current detection method is particularly advantageous in situations where
the effect of source voltage distortion needs to be compensated for, in addition to load
harmonic compensation [78]. Moreover this method has the added ability to suppress
parallel resonances formed by nearby power factor correction filters and source
impedance, unlike the load current detection. However, reactive power compensation
is not available for this method, as the load current is not measured. Of course, source
current and load current can be both detected at the same time to get the best of both
worlds [78],viz:
l
l
Sh
APF
!
(3.12)
but this can be expensive as an extra set of high quality current sensors is required.
|
i
3.6.3
Voltage Detection Method
With reference to Figure 3.8(a), voltage detection uses the control law:
*APF
=K V
' Dh
(3.13)
where K = a proportional constant
= harmonic components of vD to be compensated
57
CHAPTER 3:
STATCOMs and Active Power Filters
Thus with the voltage detection method, the voltage VD at the point of coupling is
measured and its harmonic components vph are extracted and multiplied by a gain K,
and used directly as the current reference, as illustrated in the control schematic in
Figure 3.15(a). In doing so, the active power filter behaves as a 1/K (Q) resistor at
harmonic frequencies connected between the point of coupling and ground, assuming
an ideal control characteristic with no delays. The entire control system block diagram
is shown in Figure 3.15(b) with the notations as before. The closed loop transfer
functions of interest here are:
(3.14)
-
V
D
KZSGCSGHEGIC
_
(3.15)
It can be seen from the above equations that a sufficiently large K minimises
harmonic distortion in both is and vD. As with the source current detection method,
system stability needs to be taken into account when designing an appropriate value
Inner Current Loop
Harmonic
Extraction
Algorithm
•Dn
'APF
I
Current
Controller
-M+
'APF
(a)
"APF
Glc(s)
'APF
V
K
Dh
*
*
>
G (s) =
(b)
Figure 3.15: Voltage detection, (a) Control schematic (b) Control system block
diagram
58
CHAPTER 3:
STATCOMs and Active Power Filters
of K and choosing the harmonic extraction circuit GHE(S), by ensuring the open loop
transfer function:
Gol (s) = -KZs
(s) • Gcs • (s) • Gm (s) • Glc (s)
(3.16)
has an adequate amount of phase margin. Note that now the power system dynamic
response determined by Zs(s) has a role to play in determining the compensation
rnmnensntinn
performance.
The voltage detection method can be used to compensate a specific non-linear load,
but it tends to overcompensate when source voltage distortion is present [99], unlike
the source or load current detection methods. This is because the active power filter
will attempt to minimise the harmonics in the voltage busbar, without distinguishing
the cause of the distortion. However, a shunt active filter with voltage detection can
be used advantageously to damp harmonic propagation and reduce voltage distortion
in a power distribution system without specific regard as to what types of load are
connected [77,108]. In fact, Akagi et al. [77,101,104] has demonstrated that an active
power filter with voltage detection connected to the end of a distribution feeder is
effective in reducing harmonic voltage distortion throughout the distribution feeder
system. It was further pointed out that for optimum harmonic damping throughout a
long feeder, the gain 1/K for the active power filter should be chosen equal to the
characteristic impedance of the feeder [103]. Also using the voltage detection method,
Sato et al. [108,109] proposed a shunt active power filter that is able to simulate an
ideal passive LC filter in real time.
3.6.4
DC Bus Voltage Detection Method
This method of active power filter reference generation is considerably different from
the rest, and was first proposed by Jou in 1995 [119]. It is sometimes referred to as the
power balance concept [120] in the literature. It does not need to measure any system
variables for information regarding harmonics that it is to compensate, as opposed to
all other methods described above. The method relies on real power balance between
59
CHAPTER 3:
STATCOMs and Active Power Filters
the source, the load and the active power filter, to obtain a current reference for the
i urce current.
With reference to Figure 3.8(a) again, the basic idea is that in the steady state, the real
power supplied from the source (at fundamental frequency) should be equal to the
sum of that consumed by the load and that consumed by the active power filter. When
the real power demand of the load suddenly increases, as happens during a load
transient, the active power filter has to supply that extra real power, causing the DC
capacitor average voltage to drop. At this moment the source current amplitude
I
should be raised to increase the real power supplied from the source. On the other
hand, when there is a sudden reduction in load real power demand, the balance of real
power from the source will flow into the active power filter, causing the DC capacitor
average voltage to rise. In this case, the source current amplitude should be reduced to
decrease the real power from the source. Thus the DC capacitor average voltage
contains real power flow information of the system, and can be used just by itself to
generate the required source current, ie. a reference for the source current.
The basic control schematic for the DC bus voltage detection method is shown in
Figure 3.16va). The measured DC capacitor voltage VdC is low-pass filtered (not
shown) and then compared against a set DC reference value VdC*. The error signal is
processed by the DC bus controller, typically a PI controller to ensure zero steadystate error in the DC bus voltage. The controller outputs the source current magnitude
reference Is*, which is multiplied with a sine-wave in phase with the terminal voltage
vD to generate the instantaneous sinusoidal reference is* for the source current. Note
that in this method the source current reference is is generated, whereas the active
power filter current reference iAPF* is generated by all other detection methods.
Therefore the inner current loop for this method is different from that of other
methods. The inner current loop here will need to regulate is rather than iAPF From
the control system point of view, however, the regulation of source current is the same
as regulation of the active power filter current [112,113]. Both linear [112,113] or
hysteresis [62] current regulation strategies have been shown to give satisfactory
results.
60
CHAPTER 3:
STATCOMs and Active Power Filters
It should be noted that all detection methods require DC bus regulation to regulate the
DC capacitor average voltage. However, in this method the DC bus regulation itself is
used to generate the current reference.
With this DC bus voltage detection method, no harmonic extraction circuitry is
required. The reference generation process generates a fundamental frequency
sinusoidal reference for the source current, and the inner current loop will ensure that
the VSI injects the appropriate harmonic current and fundamental reactive current, so
that the source current contains only the fundamental active component. In other
words, all harmonics (within the bandwidth capability of the current loop) and the
fundamental reactive component are automatically taken care of, and there is no
option to selectively compensate for certain harmonics and/or fundamental reactive
power.
As with all other detection methods, both single-phase and three-phase active power
I
filter implementations are equally possible. In a three-phase implementation for this
method, the sine-wave generator would generate three sine waves of equal magnitude
Inner Current Loop
X
p-i
Controller
Phase
Locked
Loop
•^H-
Current
Controller
Sinewave
Generator
(a)
Inner Current Loop
P-I
Controller
Is"
is
* frfvY^'
•L
Phase
Locked
Locp
Current
Controller
UPF
r ..
Sinewave
Generator
(b)
Figure 3.16: DC bus voltage detection method control schematics, (a) Source current
regulation (b) Conventional VSI current regulation
61
CHAPTER 3:
STATCOMs and Active Power Filters
but displaced by 120° in time, each in phase with the respective phase voltage vDa, vDb
or VDC at the point of filter a apling. All three sine waves are multiplied by the same
DC bus controller output to generate the three source current references. Therefore the
source currents will always remain sinusoidal and balanced with unity power factor
under all circumstances, regardless of load characteristics and whether the source
voltage is balanced or unbalanced. These may be perceived as an inherent
disadvantage of the method, because the inverter requires an increased rating
proportional to source voltage unbalance and load power factor, when all that is
|
required is load harmonic compensation [96].
Although not necessary, the source current reference is so generated can be converted
back into the more familiar active power filter current reference IAPF by subtraction
I
with measured load current signals, as indicated in Figure 3.16(b). This would then
allow one of the many standard VSI current regulation schemes to be used, as for all
other detection methods. Doing so might potentially achieve a faster response to load
transients. However, Singh et al. [62] showed that this not only requires an extra set of
high quality current sensors for measuring the load current, but also gives rise to
significantly poorer harmonic compensation (higher THD in source current). The
reason is that with the source current control method in Figure 3.16(a), the DSP needs
only to compute and process the fundamental frequency reference, which is relatively
slow varying. For the control method in Figure 3.16(b), the DSP has to compute the
active power filter current reference, which necessarily contains all the fast varying
harmonic components in the load current. Therefore the same amount of DSP
computation and sampling time delays has a bigger impact on the accuracy of the
resulting reference output.
The DC bus voltage detection method is suitable for use to compensate a specific load
or a specific group of loads, just like the load current and source current detection
methods. Compared to these two methods, the DC bus voltage detection method
requires a minimum number of current sensors [112,113]. Assuming a single-phase
implementation, load or source current detection requires two voltage sensors, one to
measure DC capacitor voltage for DC bus regulation, and the other to measure the
coupling point voltage for synchronisation purposes. Furthermore, two high quality
sensors are required, one to measure the load or source current which forms part of
62
CHAPTER 3:
STATCOMs and Active Power Filters
the reference generation process, and the other to measure the active power filter
current for VSI current regulation used in the inner current loop. The DC bus voltage
detection method needs two voltage sensors for the same purposes as well. However,
only one current sensor is required, to measure the source current for use in the inner
current loop. Three-phase systems can save on two high quality current sensors, since
each set of current measurements requires only two of the three phases to be
measured. Thus the DC bus voltage detection method is the cheapest in terms of
I
hardware implementation cost. The main drawback of this method is its relatively
slow response as the large inertia of the DC capacitor is involved in the control
dynamics, with settling time up to 4 line cycles not uncommon following a step
change in load [113].
3.7
s
ACTIVE POWER FILTER HARMONIC EXTRACTION ALGORITHMS
Apart from the DC bus voltage detection method, all other current reference
generation processes require the detected variable to be filtered. For the load current
detection method, the fundamental frequency component in iL needs to be removed,
retaining only the harmonic components i^h as the current reference. Similarly, for the
voltage detection method, the fundamental component in vD needs to be removed,
retaining only the harmonic components voh to generate the required current
reference. In all cases the fundamental component needs to be separated. This can be
done either in the frequency domain or in the time domain.
Frequency domain extraction is based on the Discrete Fourier Transform (DFT) and
Fast Fourier Transform (FFT) [121,122], and is conceptually more straightforward.
Unfortunately, it is very computationally intensive and the dynamic response is poor.
This has severely restricted the popularity of frequency domain based extraction
algorithms. Recently Rechka et al. [123] has demonstrated promising results with the
use of a Recursive Discrete Fourier Transform (RDFT), which is essentially an
improved version of DFT suitable for real-time application. However, the superiority
of time domain algorithms remains to be challenged.
63
CHAPTER 3:
STATCOMs and Active Power Filters
For removal of the fundamental component in time domain, a notch type
characteristic centred at the fundamental frequency is desired. However, direct
implementation of a notch filter is met with the following caveats [91]:
1. A sharply tuned high Q factor notch filter is difficult to implement using analog
circuits due to component tolerance and ageing affect;
2. When the system frequency varies, the notch filter circuit parameters need to be
modified, resulting in complicated control circuits.
Therefore in the literature, a range of solutions has been developed to circumvent
!
these problems and are reviewed in the following sections. The use of modem DSPs
does partially alleviate the above concerns. However, the popularity of the special
techniques to be discussed has seemed to continue on.
3.7.1
Instantaneous Reactive Power Method
Known also as the p-q theory in Japan [71], the instantaneous reactive power (IRP)
theory was proposed by Akagi et al. in a classical paper [94] in 1983 for applicatio: .s
in reactive power and harmonic compensation with converter based compensators. It
is generally regarded as the cornerstone of modem active power filters and is certainly
regarded as the benchmark against which other methods are compared.
Firstly, the three-phase source voltages va, vt>, vc and load currents iLa, in,, iix in a
three-p'nase three-wire system are expressed in an a-P orthogonal coordinate system
i/sin * the Clarke transformation:
1 -1/2
-1/2'
(3.17)
v.
0 V3/2 -V3/2
64
CHAPTER 3:
STATCOMs and Active Power Filters
l
1 -1/2
'La
-1/2'
La
l
Lb
0
V3/2
(3.18)
-A/3/2
ihc.
According to Akagi, the instantaneous active power p L and reactive power
consumed by the load can be defined as and calculated from:
ha
PL
(3.19)
MLV
The instantaneous powers above can be decomposed into DC (constant) and AC (time
varying) components:
(3.20)
PL=PL+PL
(3.21)
where pL and qLzre the DC components corresponding to the fundamental load
current, and pL and qL are the AC components corresponding to the harmonic current.
The compensation (active power filter) current reference can be determined from:
-1
p
l
Ca
V
l
cp
•
P
V
(3.22)
q
where p* and q* are the reference instantaneous real and reactive powers. For the
purposes of harmonic compensation and reactive power compensation, the AC term in
PL and all terms of qL must be compensated [119,124,125], which means:
P
=PL+PDC
(3.23)
(3.24)
65
CHAPTER 3:
STATCOMs and Active Power Filters
where pL can be obtained by high-pass filtering PL, and poc is a constant value
obtained from the DC bus regulation PI controller. Finally, the three-phase reference
compensation current can then be obtained by transforming back to the a-b-c
coordinates:
0
'Co
'Ca
(3.25)
l
Cb
}cp
l
Cc
2J
This process is depicted in Figure 3.17. The salient feature of this method is thai the
fundamental frequency component of the load current can be related to the DC
components in PL and qL, whereas the harmonic components are related to the AC
components in PL and qL- This allows the fundamental load current to be easily
removed using a conventional high pass filter with PL and qL. The choice of the highpass filter is critical to the performance of the system. References [71,125] illustrate
how the cut-off frequency of the high-pass filter is selected depending on the
compensation objectives.
There are two main limitations of this harmonic extraction algorithm. Firstly, this
'u
J
Lb
III
ILC
4—
ii
b
v
c
M
— •
Calculation of
Calcalation of
pL and q
'ca'.'cb'and
k i
"Ce
•
u-f
Inner Current
Controller
L
q'
Pu
P'
dc
High-Pass
\r
DC Bus
Controller
Figure 3.17: Instantaneous reactive power method for generating compensation
current reference
66
CHAPTER 3:
STATCOMs and Active Power Filters
algorithm is inherently three-phase, and no single-phase equivalence can be found.
Therefore it cannot be used by single-phase active power filters. Secondly, the
algorithm gives a good filtering characteristic under ideal source voltage conditions
and even under load unbalance. However, when the source voltages become
unbalanced and/or distorted, the compensated source currents will remain distorted
[119].
A modified and improved version of the IRP method [126,127] is available. Whilst
the modified IRP has improved performance under balanced distorted source voltage
conditions, it remains ineffective when the source voltages are unbalanced [120].
3.7.2
Synchronous Reference Frame Method
The synchronous reference frame (SRF) concept is derived from AC rotating machine
theory and was first adapted for use as a harmonic extraction algorithm in active
power filter systems by Bhattacharya et al. [128]. The basic idea here is that any set of
three-phase quantities in a three-wire system can be transformed into the ct-p
stationary reference frame using the Clarke transformation, followed by the Park
transformation into a synchronous d-q reference frame rotating at some chosen
frequency. When combined into a single mathematical operation, these two
transformations can be expressed as:
V
(3.26)
where [c]= j |
cos(co0t)
sin(0)ot)
-sm(coot)
cos(ct)J)
I
2
2
A2 .
Here va, Vb and vc are a set of three-phase quantities, and v<j and vq are the
corresponding direct and quadrature quantities in the synchronous frame of reference
rotating at an angular frequency of co0 (not necessarily the fundamental line
frequency). In the d-q reference frame, the chosen frequency a>0 component in the
67
CHAPTER 3:
STATCOMs and Active Power Filters
original signal becomes a DC component, whereas ;vll other harmonics remain as AC
terms. This allows for easy retrieval or removal of the chosen frequency component
by using a simple conventional low-pass or high-pass filter respectively, before
transforming back into the stationary frame a-b-c quantities.
When applied to a shunt active power filter employing load current detection, the
three-phase load currents iu,, iu, and i^ are first transformed into iui and iLq in the
fundamental synchronous reference frame ((tijln = 50Hz) using equation (3.26),
where sin(a>ot) and cos(co0t) are obtained from the phase-locked loop synchronised to
the system voltage, iu and iLq are high-pass filtered to remove the DC terms (which
correspond to the fundamental components in iu, iu> and im). The output signal ioc
from the DC bus controller is subsequently added to the direct-axis component to
demand a small amount of real power for DC bus regulation. Finally the
compensation (active power filter) current reference is obtained by reverse Park and
Clarke transformations. This process is illustrated in Figure 3.18.
The frequency shifting effect obtained using the synchronous reference frame method
is very similar to that obtained with the instantaneous reactive power theory.
However, because the synchronous reference frame method does not use system
voltage magnitudes in its calculations (only the frequency and phase information are
extracted from the system voltage), this method is not affected by the presence of
unbalance and/or distortion in the source voltages. Consequently, the synchronous
reference frame method has good performance under all conditions [129], unlike the
IRP method.
Synchronous Frame
Stationary Frame
A.
'u"
'u-
vDb
V
Dc
Phase
Locked
Loop
sin(mt)/cos(cot)
Figure 3.18: Synchronous reference frame for generating compensation current
reference
68
CHAPTER 3:
STATCOMs and Active Power Filters
It should be pointed out that, contrary to some early beliefs notably by Bhattarcharya
et al. [89,130], filtering in the synchronous reference frame does not provide any
inherently superior filtering characteristics that are not achievable in the stationary
frame. Recent theoretical work by Zmood et al. [131,132] in relation to linear current
regulation, and later generalised by Yuan et al. [133], has shown that an equivalent
stationary frame transfer function can always be found for a given transfer function in
the synchronous frame. In particular, a low pass filter in the synchronous frame is
equivalent to a resonant filter in the stationary frame, and a high pass filter in the
synchronous frame is equivalent to a notch filter in the stationary frame [134].
Zmood's work has two major implications for active power filter applications. Firstly,
there is no theoretical advantage in embracing the synchronous frame for the sole
purpose of performing certain filter operations. A notch, resonant or other equivalent
filter in the stationary frame is more straightforward, and avoids multiple
multiplications of sine and cosine terms which are potentially time-consuming and
introduce rounding errors along the process.
There are two perceivable situations when the use of the synchronous frame is still
justified. One is when a DSP is not available and analog components have to be used.
Under such circumstances, sharp tuning is difficult to achieve due to component
tolerances, and the synchronous frame method tends to give more accurate results
[89]. The second situation is when significant and frequent system frequency
variations are expected. In this case, the resonant or notch stationary frame filter will
become off-tuned and a drastic decrease in filter performance can be expected, unless
the DSP implements some sort of adaptive algorithm that will monitor the system
frequency and recalculate the filter coefficients as required. In contrast, synchronous
transformation will automatically take into account frequency changes through the
phase and frequency information supplied from the phase-locked loop circuitry.
The second implication of Zmood's work is that notch or resonant filters can be
applied equally well to single-phase systems. The synchronous frame method is a
three-phase concept and no true equivalence exists for single-phase systems.
69
CHAPTER 3:
3.7.3
STATCOMs and Active Power Filters
Various Single-Phase Algorithms
The basic shunt topology is the most popular active power filter topology, and of all
its detection methods, the load current detection is the most used method as it
provides simple and fast compensation for a particular load or group of loads. For
harmonic compensation, the fundamental component in the load current needs to be
removed, and the remaining harmonic components are used as the compensation
current reference. In most cases, however, reactive power compensation is also
required. Therefore the fundamental reactive component in the load is to be retained
for the reference, and only the fundamental active component is to be removed. Of
course this can be readily achieved u?: g the IRP method or in the synchronous
reference frame. However, both are no: mly calculation intensive, but are strictly
1
restricted to three-phase applications. Numerous algorithms have been proposed for
single-phase applications, all with the specific aim of removing just the fundamental
active component. These techniques are briefly discussed here. It should be noted that
since a three-phase system can be constructed from three single-phase systems, these
techniques are equally and directly applicable to three-phase systems.
Mathematically, the source voltage in a single-phase system can be expressed as
(3.27)
and the distorted load current can be represented as
i
„ sin(ncot + 9n)
= Ip smicot) + Iq
(3.28)
n=2
where ip(t) = in-phase or active component
iq(t) = quadrature or reactive component
ih(t) = harmonic component
For harmonic and reactive power compensation, the required compensation current
reference is
70
STATCOMs and Active Power Fi;?.-.s
CHAPTER 3:
(3.29)
= iL(t)-Ipsia(at)
In (3.29), iL(t) is measured, whilst the sin(ot) factor comes from the PLL
synchronised to the system voltage. Hence the only parameter that needs to be
estimated is Ip. Ip has been obtained in various ways in the literature.
The simplest approach for estimating IP is not J estimate it explicitly at all, but
instead to rely on the DC bus conU jller, as shown in Figure 3.19(a). The DC bus
controller is a PI type, and in the steady state it will generate the correct amount of
fundamental component to maintain the DC bus voltage., However, this approach is
potentially slow and inefficient, as it relies solely on the DC bus feedback loop and
does not take advantage of the information available in iL for feedforward purposes.
The second approach [70,135] uses a band-pass filter centred at the fundamental
frequency to extract the fundamental component, which consists of both active and
reactive components ip and iq, as shown in Figure 3.19(b). A peak detector then
detects the peak of the fundan ,ntal component, which is /, ='Jlp2 +Iq2 • Although
this is not quite Ip, it is at least a rough estimate of it. The DC bus controller will take
care of any steady state error, but now the dependence on the DC bus feedback loop is
reduced.
The third approach, presented by Dixon et al. [136j, again uses a band-pass filter to
extract the fundamental component (ip + iq). The idea now is to recognise that
whenever cot- — , the reactive component iq in equation (3.28) is identically zero and
the active component ip is equal to Ip. Thus a sample and hold is used to sample (ip +
iq) once every line cycle at every cot =n— with respect to the zero crossing of vD, as
shown in Figure 3.19(c). Theoretically this gives an exact estimation of Ip.
71
CHAPTER 3:
STATCOMs and Active Power Filters
Another popular method for Ip estimation is based on modulation of the load current
iL(t) with the sin(cot) factor obtained from the PLL. Doing so produces a signal that
has a DC term proportional to Ip:
-M+
I DC Bus
-w Controller
I (P-itype)
'DC-
X
V.
Phase
Locked
Loop
sin(cnt)
(a)
3and-Pass
Filter
A
Peak
Detector
DC Bus
Controller
(P-l type)
Phase
Locked
Loop
(b)
-M-
DC Bus
Controller
(P-l type)
Figure 3.19: Different approaches to Ip estimation, (a) No explicit, estimation (b)
Rough estimation (c) Estimation using sample and hold
72
CHAPTERS:
STATCOMs and Active Power Filters
iL (t)
— — - cos(2ctf)
+—
V
2
2
'
2
.
(3.30)
n=2 ^
Thus Ip can be extracted using a conventional low pass filter, and ic* constructed
according to (3.29). Direct open-loop implementation of this process is illustrated in
Figure 3.20(a) [137]. However, this is prone to errors since the gain of the low-pass
filter and analog multipliers affect the estimated Ip. ma) any changes in the system
frequency will vary the effective gain of the low pass filter. This was subsequently
improved by Tepper et al. [97,138], using the closed-loop implementation shown in
Figure 3.20(b). This implementation is able to produce good steady state performance
DC Bus
Controller
(P-l type)
Feedback loop
Low-Pass
XPhase
Locked
Loop
AL
/
sin(cot)
X
DC Bus
Controller
(P-l type)
V
V.
(b)
Figure 3.20: Estimation of Ip by modulation, (a) Open-loop implementation (b)
Closed-loop implementation
73
CHAPTER 3:
STATCOMs and Active Power Filters
over a wide range of frequencies from 40Hz to 65Hz, but has a relatively slow settling
time of two and a half line cycles.
In [98], Zhou et al. presented a very fast method of estimating Ip based on the
principle of minimising the compensation current. The idea is that the rms or
(rectified) average values of the compensation current ic(t) are minimum when the
estimated Ip corresponds to the true value of Ip. A control mechanism is implemented
whereby Ip is incremented by an increment AIP proportional to the change in the
average value of ic(t). If the average value increases, the sign of AIP is reversed;
otherwise the average value will converge to a minimum value and the true Ip is
found. As this method does not require any filter, it is fast with a transient response of
half a fundamental line cycle being reported.
3.8
VSI CURRENT REGULATION STRATEGIES
In the shunt active power filter and many other filter topologies, the active element is
controlled as a current source. The reference generation process generates a
compensation current reference waveform, and the power inverter attempts to produce
a current as close to the demanded reference as possible. Whilst this strategy lends
itself to the direct application of a CSI, a VSI with closed-loop current control is the
strongly preferred alternative in many cases because of efficiency and cost.
The Current Regulated Pulse Width Modulation (CRPWM) of VSI, as it is often
known, is itself a topic of intense research as it has wide application in areas such as
high performance AC drives and PWM rectifiers. A great number of alternative
strategies have been proposed for CRPWM VSI [139], but three major classes can be
identified, each with its particular benefits and limitations. They are linear current
regulation, predictive current regulation and hysteresis current regulation. All three
I
types of current regulation have been used in conjunction with active power filters.
This section briefly reviews these major classes of current regulation techniques.
There are two good reasons for doing this. Firstly, although current regulation of a
VSI is not a topic exclusive to active power filter, it is one of the most important
design considerations for an active power filter as it directly determines the steady74
CHAPTER 3:
STATCOMs and Active Power Filters
state and transient performance of the filter. The fastest and most accurate reference
generation process is worthless if the active power filter cannot replicate the
demanded current accurately and rapidly. Secondly, of all the numerous applications
for a current regulated VSI, active power filter arguably represents the most
demanding application. This is because the filter often has to track current references
with steep slopes or high — values, and therefore the bandwidth requirement of the
dt
current loop is necessarily high. Not all current regulations are suitable and a careful
choice of current regulation technique is crucial for satisfactory performance.
3.8.1
Linear Current Regulation
Linear or Ramp current regulation is a straightforward extension of open loop PWM
strategies whereby the target output voltage waveform is not directly calculated but
rather determined by the current error, as shown in Figure 3.21. The instantaneous
phase current is measured and compared against the current reference waveform irefBased on the current error the PI regulator generates a voltage demand which is
i
|
passed to a sine-triangle pulse width modulator.
The key advantage of this current regulation strategy is that a constant switching
frequency can be achieved with the use of a triangular carrier in the PWM modulator,
t
and therefore well defined harmonic spectrums are produced and the switching
harmonics can be filtered easily. The main drawback of this basic scheme is that a
Demanded
Voltage
A/V
Figure 3.21: Stationary reference frame linear current regulation
75
CHAPTER 3:
STATCOMs and Active Power Filters
steady-state amplitude and phase error always exists between the reference and the
measured current. The PI regulator has an infinite gain at DC and therefore has zero
steady-state tracking error for DC signals. However, at the fundamental frequency the
gain of the PI regulator is finite and a steady-state error exists. Although the gain of
the PI regulator can be increased to help reduce the steady-state error, it is often
limited by feedback stability concerns as well as the restriction that the slope of the
current error should never exceed that of the triangular carrier. For some AC drive
applications this basic scheme may be acceptable, but it is generally unsatisfactory for
active power filters because harmonic components need to be tracked. The gain of the
PI regulator falls off sharply with increasing frequency and therefore the steady-state
error is proportionally larger for higher frequency components.
To solve the problem of steady-state error, the PI regulator is often executed in the
synchronous reference frame for three-phase systems. In the synchronous reference
frame rotating at the fundamental frequency, the fundamental frequency components
become DC terms and thus a PI regulator will be able to ensure zero steady-state
tracking error for fundamental components. To track multiple harmonic frequencies,
!
I
multiple synchronous references rotating at harmonic frequencies running in parallel
could be used. Whilst the synchronous reference frame is effective in reducing steadystate errors, there is no equivalent technique for single-phase systems, until only
recently.
It is recently established by Zmood [131,132] that a PI regulator implemented in the
synchronous frame is mathematically equivalent to a second order resonant controller
centred at the rotating frequency of the synchronous frame. The equivalent resonant
filter is not only more efficient to implement but is equally applicable to single-phase
systems.
"i
3.8.2
Predictive Current Regulation
Predictive current regulation (PCR), also known as dead-beat current control, is a
computationally intensive scheme and lends itself naturally to DSP implementation.;.
This method involves calculating the inverter voltage that is required to force the
76
CHAPTER 3:
STATCOMs and Active Power Filters
current error to zero during the next switching interval [140]. This is done separately
for each phase of a three-phase system.
Mathematically, for a constant switching frequency operation, the phase current error
at the sampling instant [k] is given by:
=
rf[k]-Imeas{k]
(3.30)
If the backemf and the reference current can be assumed constant over the next
switching period AT, the average inverter outpui voltage (ie. the demanded voltage)
that will reduce this error to zero over this period is:
V [k] = e[k]
[k] -
(3.31)
assuming the inverter is driving against a backemf with pure inductive coupling.
Therefore by measuring the backemf e and phase current Imeas at every sampling
instant, the demanded voltage can be calculated according (3.31) and passed to the
pulse width modulator. In situations where the backemf is not available, it can be
predicted from the actual current change that occurred in the previous switching
interval [140]. Since predictive and linear current regulation both require a separate
pulse width modulator, their harmonic performance should theoretically be the same
as that of a conventional open loop PWM VSI.
The advantages of predictive current regulation is again a constant switching
frequency, and its fast deadbeat dynamic response [140], The iirnt^iaons are the lack
of inherent current limiting capability, and large computational overhead.
Furthermore, its performance can be very sensitive to the accuracy of the system
model. In particular, when the backemf is not known and needs to be predicted in the
algorithm, the performance is very sensitive to load impedance mismatch. A mere
10% mismatch in the load inductance can significantly degrade the performance of
the system.
77
CHAPTER 3:
3.8.3
STATCOMs and Active Power Filters
Hysteresis Current Regulation
Hysteresis current regulation is the simplest of all current regulation strategies, and is
also suitable for both single-phase and three-phase implementations. The measured
current is compared against a reference to create the current error, which is passed to a
hysteresis comparator. A basic single-phase hysteresis controller is shown in Figure
3.22(b). The hysteresis comparator will only change state when the current error is
greater or smaller than the assigned band values of +B/2 and -B/2 respectively, and
the VSI is switched in a way to drive the current error in the reverse direction, as
shown in Figure 3.22(c). In this way the actual current can be constrained to within a
band of width B centred on the current reference waveform, as shown in Figure 3.23.
For a three-phase VSI, three independent hysteresis controllers can be implemented,
one for each phase [141]. When the phase current error reaches the upper band limit
+B/2, the corresponding phase-leg is switched low, and the opposite happens when
the error reaches the lower limit -B/2. If no neutral connection exists, only two phase
currents need to be measured and controlled.
The advantages of hysteresis current, regulation are its simplicity of implementation
using analog components, its good accuracy, and that the peak output current is
I
naturally limited. It is also capable of the fastest transient response of all regulation
strategies, and is clearly superior in tracking steep slope/high-order harmonics
[142,143]. Unlike linear and predictive current regulation, the controller requires no
I
CO CO
1
i Kr >B/2
(a)
SW3
SW4
OFF
ON
ON
OFF
(c)
Figure 3.22: Hysteresis current regulation, (a) Single-phase VSI (b) Current controller
(c) Switching rules
78
CHAPTER 3:
STATCOMs and Active Power Filters
Output Current
Hysteresis
Bandwidth
-•• Time
Output Voltage
- • Time
Figure 3.23: Current and voltage waveforms for hysteresis current regulation
knowledge of load parameters, making it a very robust controller.
The major problem with this strategy is that the inverter switching frequency varies
with the instantaneous value of the backemf. For the arrangement shown in Figure
3.22(a), the instantaneous switching frequency can be shown to be:
2B-L-V,dc
(3.32)
where s = instantaneous backemf
L = load inductance
Vdc = the DC bus voltage of VSI
B = hysteresis band magnitude
For a sinusoidal backemf (eg. when the inverter is connected to an AC power system),
the switching frequency will vary sinusoidally at double the line frequency. Note that
the maximum switching frequency occurs when the backemf is instantaneously zero.
This will need to be taken into account when selecting inverter switches during the
design stage;. Also the spread of harmonics means that they are much harder to filter.
There are also phase interaction and limit cycle problems under certain conditions
79
CHAPTER 3:
STATCOMs and Active Pov.er Filters
[141], but these are three-phase problems. More sophisticated hysteresis
implementations do exist to achieve almost constant switching frequency and/or
decouple phase interactions whilst retaining the fast dynamic response of the
technique [144], but these advanced techniques are not required in this thesis and are
therefore not discussed here.
i
3.9
SUMMARY
This chapter has presented a systematic review of two power electronic systems that
represent the latest generation of technology for power quality improvement, namely
the STATCOM and the APF. The STATCOM is a shunt connected device operating
I
at the fundamental frequency. By providing very fast control of the reactive power it
generates, it can be used to perform a range of network functions. In most cases the
STATCOM is used to regulate the voltage on a connecting busbar.
On the other hand, the main function of the APF is to compensate for the harmonics
generated by certain loads. APFs can be categorised according to their topology,
control detection method and the harmonic extraction algorithm used. Many
topologies are possible for an APF but the basic shunt topology is the most researched
and versatile topology with proven performance in the industry. The shunt APF can
use different control detection methods and harmonic extraction algorithms to
generate the current reference, each suited to different applications and objectives.
The common trait between the STATCOM and a shunt APF is that both are structured
with a VSI power stage connected in parallel to the system, so in principle they should
be able to accomplish the same functions. When the primary role of the VSI is to
compensate for reactive power, it is more commonly referred to as a STATCOM,
especially by power system engineers. On the other hand, when it is used to primarily
compensate for harmonic distortions, it is more often called an active power filter.
Traditionally STATCOM is meant for high power, high voltage system applications
so that it can only economically be switched at line frequency and therefore does not
have any capability for dealing with harmonics. This scenario is slowly changing as
fast devices of higher rating become available, and STATCOMs are now being
increasingly proposed for distribution level applications and employ high frequency
80
CHAPTER 3:
STATCOMs and Active Power Filters
PWM switching, under the name of D-STATCOM. With PWM strategies, a
STATCOM can accomplish a whole new range of harmonic related functions and it is
at this point that the distinction between a STATCOM and a shunt APF blurs.
Jin chapter 4, the knowledge presented here relating to STATCOM and APF controls
is used to assemble a composite function shunt compensator to simultaneously
regulate the pantograph voltage of a railway system and to provide harmonic
mitigation throughout the traction feeder.
SI
I
81
CHAPTER 4: A NEW TRACTION POWER
QUALITY CONDITIONER FOR 25KV
RAILWAY SYSTEMS
It has been shown in Chapter 2 that 25kV electrified railway systems tend to suffer
from low rms and average voltage at the pantograph, leading to inferior locomotive
performance, hi addition, it has been pointed out that the rms voltage can be boosted
if reactive power can be supplied, whilst the average voltage can be restored if low
order harmonics can be removed. Chapter 3 has surveyed modem power electronic
solutions based on the VSI and has found that the STATCOM is an effective means of
providing a dynamically variable source of reactive power, whilst the shunt APF is
focused on compensating for harmonics.
This chapter presents a novel VSI based power quality conditioner (T-PQC) which
combines the functions of a STATCOM and an APF, and is aimed at traction
applications. The proposed compensator is capable of providing controllable reactive
power whilst simultaneously atid actively mitigating the harmonics throughout the
railway feeder. The chapter first provides an overview description of the proposed
power quality conditioner, highlighting its novelty in relation to existing STATCOMs
and APFs reported in the literature. A suitable harmonic extraction algorithm for the
proposed conditioner is then developed and analysed to justify its suitability for this
unique single-phase application. The effectiveness of the T-PQC for harmonic
compensation is evaluated and clarified by examining the reduction in harmonic
Ii
impedance as seen by locomotive loads. Through detailed transmission line
modelling, it is shown that the power conditioner should be controlled as a low
impedance at harmonic frequencies, which will guarantee suppression of low order
harmonics throughout the feeder. Finally, the reactive power compensation loop and
i
DC bus voltage control loop design philosophies are presented.
82
CHAPTER 4:
4.1
A New Traction Power Quality Conditioner for 25kV Railway Systems
PROPOSED TRACTION POWER QUALITY CONDITIONER
The harmonic voltage in the feeder is a direct result of the load harmonic current
flowing through the system impedance. Similarly the reactive voltage drop in the
feeder is a direct result of the load reactive current flowing through the system
impedance. Two fundamental approaches are possible to minimise system voltage
harmonics and reactive voltage drops with an active compensator. The first approach
involves installing an active power filter on board the locomotive to modify the load
current as seen by the system. The second approach involves a track-side active power
filter to modify the system impedance as seen by the moving load.
On-board filters have been studied by a number of researchers [145-147] in the
context of PWM converter fed locomotives, with the aim of minimising high-order
harmonics (~lkHz; to avoid harmonic overvoltages. The on-board approach, if
applied to low order harmonics and reactive power, is likely to give superior
Is
0
performance as the actual disturbing load current can be measured accurately ar>J
acted upon by an active power filter. However, this is often not a feasible option as
real-estate on a typical locomotive is severely limited. Also with an on-board filter,
every single locomotive would need to be retro-fitted, whereas only one track-side
filter would be needed per feeder section, which is potentially more cost-effective.
Hence only track-side filters are considered in this thesis.
The second consideration in developing an active power filter for railway applications
concerns its placement along the feeder. Previous studies by Morrison and Hu et al.
[5,25] involving thyristor based SVCs for voltage boosting purposes, have shown that
the end of the feeder section is the most effective location for a single compensator.
Investigations by Akagi [101] using a shunt active power filter for harmonic damping
in a Japanese public power distribution system has also indicated that the end of the
feeder line is the optimum filter location in terms of compensation performance and
filter rating. Finally, in searching for a suitable location for an overvcltage passive
damping filter, Morrison ct al. [9] again concluded that the end of the feeder section is
the most effective and practical location, partly because of the physical space
available at the track-sectioning cabin (see Figure 2.1) for housing the filter.
83
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
Therefore a shunt active power filter connected to the end of each feeder section is
proposed.
The proposed shunt active power filter is, in its basic form, a single-phase voltage
source inverter (VSI) consisting of four self-commutated semiconductor switches
I
(IGBTs or IGCTs), with an anti-parallel diode connected across each switch. As the
active power filter is not intended to supply any real power, the DC side of the VSI
consists of a capacitor for energy storage purposes only.
With the appropriate modulation strategy, the VSI is intrinsically a control) .ole
I
I1
(fundamental and/or harmonic) voltage source, and can be controlled to generate
fundamental reactive and/or harmonic currents. Thus a VSI offers the potential to
compensate for reactive power and also for system harmonic distortion compensation.
Some of the main observations from Chapter 3 about the STATCOM and shunt active
power filter are:
1. Almost all STATCOM implementations in the literature do not use high
frequency PWM switching, but instead rely on using multi-pulse magnetically
coupled circuits to eliminate low order harmonics in the output voltage waveform.
This means that whilst they can be controlled to supply or absorb reactive power
at the fundamental frequency, they cannot easily be explicitly controlled to
compensate for system harmonics at the same time;
2. Using various PWM strategies, shunt active power filters have been proposed to
perform reactive power compensation in addition to harmonic compensation.
However, these dual-function active power filters are installed in the vicinity of
the non-linear load. By measuring the distorted load current and/or supply current,
they are controlled in such a way so that the source 'sees' the active filter/nonlinear load combination as a resistive load with near unity power factor. In other
words, the compensation is only local to the distorted load.
It is seen that no existing STATCOM or active power filter directly serves the needs
of railway systems. To solve the problems on 25kV railway systems, a new shunt
active power filter based only on voltage detection is now proposed. The control
84
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
strategy is novel in that it compensates for system voltage drop with reactive power
compensation, as well as providing harmonic mitigation throughout the connected
feeder system. As the compensator possesses functions beyond that of either a
conventional STATCOM or an active power filter alone, it is referred to as a Traction
Power Quality Conditioner (T-PQC) in the remainder of this thesis. The proposed TPQC is shown in Figure 4.1, ard the associated controller block diagram is given in
Figure 4.2. The T-PQC is connected to the system via a coupling transformer which
matches the voltage and current ratings of the T-PQC inverter to that of the 25kV
system. Also shown in Figure 4.1 is a coupling inductance Lc, which adds to the
leakage inductance of the coupling transformer to limit switching ripple in the inverter
current.
The T-PQC consists of an inner current loop, thus it behaves like a controllable
current source, accepting an instantaneous inverter current demand ijnv* which it will
attempt to generate. Details of and justification for the three-level hysteresis inner
current loop that has been used are left till Section 5.4, where it is discussed along
with novel current regulation techniques developed for multilevel inverters.
As shown in Figure 4.2, the T-PQC consists of three independent outer control loops:
low order harmonic compensation loop, reactive power compensation loop and DC
bus control loop. The three control loops are responsible for generating the 3 distinct
components that make up inverter demanded current ij nv \ and have the components
of:
50Hz HV Supply
HV source Impedance
(Z = j1 .On, referred to 25kV)
f fnciioiTpomrQuaiityConditloner (T~PQC)
Feeding Transformer
(Z=j7.5n, referred to 25kV)
Conventional
Single-Phase
VSI
Coupling
Z = (0.169 + jO.432) n/km, C = 0.011 nF/km
{Transformer L
c
rrm
QD—- —
- - - - - • — - - - - - - - - — — - - - — - - - - — - "
Train Load A
Train Load B
Train Load C
Train Load D
Figure 4.1: 25kV railway system with proposed power quality conditioner
85
A New Traction Power Quality Conditioner for 25kV Railway Systems
CHAPTER 4:
Low Order Harmonic Compensation
v D (0
Harmonic
Extraction
Circuit G(s)
Current
Transducer
Gain
K
'Fundamental Voltage Control/Reactive Power Compensation \
v D (0
Three-Level
Hysteresis Controller
JT
Switching
Signals
DC Bus Voltage Control "•
Single-Phase
H-Bridge
Inverter
Running
Window
RMS Calculator
Figure 4.2: Controller block diagram of proposed Traction Power Quality Conditioner (T-PQC)
86
1. ihar, containing only harmonic components extracted from the measured VD, the
voltage at the point of T-PQC coupling. This is for harmonic compensation.
2. iq*, a 50Hz fundamental component 90° out of phase with vD. This current causes
reactive power to be supplied or absorbed by the T-PQC.
3. id , a 50Hz fundamental component in phase with VD. This current causes a small
amount of real power to flow into the T-PQC to compensate for inverter power
losses and maintain the DC bus voltage.
The three control loops are discussed in detail in the next few sections of the chapter.
It should be pointed out that the controller of the proposed T-PQC shown in Figure
4.2 is to be implemented digitally on a low-cost DSP, and the choice of various
algorithms will reflect this, as discussed below.
4.2
Low ORDER HARMONIC COMPENSATION
The objective of the harmonic compensation loop is to reduce the low order voltage
harmonics in the feeder, bringing the voltage average values higher and clc zr to the
ideal without distortion, or equivalently bringing the form factor closer to 1.11.
4.2.1
Control Detection Method
The first consideration of the harmonic current reference generation is the choice of
the detection method. As has been discussed in Chapter 3, for the shunt active power
filter four basic detection methods are possible for determining the harmonic current
reference ihar »viz:
1. by directly measuring the load harmonic current to be compensated and using the
current signal as a reference command;
2. by controlling the filter to minimise the source harmonic current;
87
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
3. by measuring and controlling the harmonic voltage at the active power filter point
of coupling to minimise particular harmonics.
4. by making use of the DC bus control loop to generate a sinusoidal source current
reference.
In a traction system, the locomotive load is physically moving. Since the shunt active
power filter is to be added to the far end of a feeder to be most effective, the AC
source will be physically quite distant from the active power filter point of coupling
(POC). Given that it is not feasible to remotely measure load or source current, the
harmomc voltage measurement approach seems the only practical possibility for the
active power filter control. Consequently the selected control strategy for the T-PQC
harmonic compensation loop is to measure the feeder voltage at the T-PQC POC
(Node D in Figure 4.1), and to process the voltage to provide a harmonic current
reference ihar* for the filter, ie.
= KG(S) VD
(4.1)
where VD is the voltage at the point of T-PQC coupling, K is a constant gain and G(s)
is the equivalent transfer function of the harmonic extraction algorithm.
4.2.2
Harmonic Extraction Algorithm
The function of the harmonic extraction algorithm is to extract and pass only
harmonics of interest from vD, and strongly attenuate other components in VQ. Ideally
G(s) in equation (4.1) should have a value of 1 at the harmonic frequencies of interest
and therefore the T-PQC behaves as a resistor of -1/K Q. (Note that in this thesis the
reference direction for the T-PQC current ijnv is out-going, therefore K is always
negative numerically for a positive damping resistor.) At other frequencies G(s)
should have values of 0, so that an infinite impedance is presented. This subsection
first briefly discusses how the harmonic extraction algorithm is usually implemented
for three-phase systems, and then proposes a novel single-phase equivalent algorithm
for the T-PQC which has some rather different compensation requirements.
ss
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
Three-Phase Systems
To obtain the current reference signal, it is necessary to extract the harmonic
components from the measured voltage signal vp. Many three-phase active power
filter systems rely on the synchronous reference frame (SRF) for harmonic extraction,
as discussed earlier in Subsection 3.7.2.
There are two obvious ways of getting rid of the fundamental component in the
measured signal using the SRF. The first is to transform the measured signal into a
synchronous frame rotating at the fundamental frequency, thus turning the
fundamental component in the original signal into a pair of DC quantities (in the
direct and quadrature axes respectively) and all the harmonics into non-DC (or AC)
quantities. A high-pass filter to remove the DC component in the synchronous frame
can then be used, followed by a transformation back to the stationary frame. This will
produce a signal free of the fundamental component.
A second SRF approach to remove the fundamental component is to transform the
measured distorted signal into a synchronous frame at some chosen harmonic
frequency, thus shifting the chosen harmonic component into a pair of DC quantities
in the synchronous frame, and all other components including the fundamental into
AC quantities. The transformed signal can then be easily processed by a low-pass
filter and reverse-transformed to give only the chosen harmonic component. Several
of such transformation/filtering blocks can be used to extract the individual harmonic
components of interest. Their outputs may then be summed to produce the desired
harmonic current reference to drive the active power filter.
The first approach passes 'everything but the fundamental', whereas the second
approach passes harmonics selectively. To date, all SRF implementations reported in
the literature use the first approach, because only one transformation is needed to
capture all harmonics to be compensated.
Single-Phase Systems
Traction systems are single-phase, and the Park Transformation does not quite apply.
The closest equivalent method for a single-phase system is to multiply the measured
89
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
y(t)
G AC (s)
Figure 4.3: Single-phase equivalent synchronous reference frame filter
signal, in turn, by sine and cosine functions at a chosen frequency [148], as shown in
Figure 4.3. This achieves the same effect of transforming the component at the chosen
frequency to DC, leaving all other components as AC quantities.
Take for example a voltage signal consisting of the fundamental and the 3rd harmonic
components:
(4.2)
V = VX cos(cot + 0x) + V3 cos(3cot + 03
Multiplying this with cos(<2tf)and sin(fitf) gives respectively:
Vc = ^
— {cos(2cot + 03) + cos(4at
(4.3)
2*
Vs = %- {sin(-0,) + sin(2fitf
—{sin(-2o)t - 03
03
(4.4)
It is observed that the fundamental term now appears as DC quantities cos(Gi) and
sin(-Gi). The difference between this equivalent transformation for singe-phase
systems is that the chosen frequency component not only appears as a DC quantity in
the synchronous frame, it also contributes to a term at a higher frequency [in the
example above, the fundamental component gives rise to the cos(2cot+Gi) and
sin(2cot+0i) higher frequency terms]. This is unlike the 3-phase Park Transformation
90
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
where the chosen frequency component contributes only towards the DC term, due to
cancellations between the 3 phases. The implication for a single-phase system is that,
to extract the harmonics in the measured signal, the signal cannot be transformed into
the fundamental synchronous frame and processed by a high-pass filter. A solution to
this problem is to use the second approach (selective harmonic) outlined above for 3phase systems.
A suitable harmonic extraction algorithm, therefore, is to use several harmonic
synchronous reference frame filters in parallel, each extracting one harmonic
component of interest from the measured VD signal. Tliis happens to suit the
compensation requirements of railway systems particularly well, since the objective
here is to compensate only for thefirstfew low order harmonics which have the most
impact on the average voltage. To compensate for anything more than these would
firstly be a waste of inverter capacity, and secondly risking the possibility of severe
switching distortion as the T-PQC attempts to compensate for the >lkHz resonance
which is likely to be present in the measured voltage signal. T/iis is unlike
compensation for public power systems where the goal is to lower the THD as much
as possible by compensating for all harmonics that are present. In that case, the
'everything but fundamental' filtering approach is desired [101,102,134]. The
selective harmonic extraction algorithm is depicted in Figure 4.4, where compensation
of only the 3 rd , 5th and 7th harmonics is proposed for the T-PQC.
In the harmonic synchronous reference frame, the filtered DC output is the harmonic
voltage magnitude. The lower the filter cut-off frequency, the more accurately the
harmonic voltage component will be extracted in the steady state, but the transient
response time will increase correspondingly as a consequence. In a 3-phase Park
Transformation, the lowest ripple component is at 6 times the fundamental frequency.
This contrasts with only 2 times the fundamental frequency for the single-phase
transformation [148]. In other words, for the same attenuation and hence extraction
accuracy, the low pass cut-off frequency has to be lower in a single-phase system,
resulting in the transient performance being significantly poorer. All these
considerations point to the fact that application of an active power filter to a traction
system is quite challenging.
91
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
cos(3a>st)
cos(3cost)
X
Low-Pass
Filter
X
x2
X
Low-Pass
I Filler
T
X
I
sin(3cost)
sin(3w s t)
cos(5cost)
cos(5o>st)
X
*D3
Low-Pass
Filler
X
v(t)-
x2
'D5
Low-Pass
X
X
sin(5o)st)
sin(5cost)
cos(7cost)
T
1
cos(7cost)
Low-Pass
X
X
y
x2
Low-Pass
X
sin(7cost)
D7
x
T
sin(7tost)
Figure 4.4: 3 rd , 5th and 7th synchronous frame selective harmonic filter (cos = system
line frequency) suitable for traction applications
As with the three-phase SRF filter discussed in Subsection 3.7.2, the synchronous
filter shown in Figure 4.4 automatically adapts to variations in system frequency,
provided that the phase information (cost) is derived from a phase-locked loop (PLL)
circuit which has a sufficiently wide bandwidth to track the frequency variations,
which is usually the case. However, implementing the three transformations shown in
Figure 4.4 can prove to be an onerous task especially for low-cost (and hence lowend) DSPs. Also a linear stability analysis cannot be performed directly on Figure 4.4
as the equivalent transfer function is not immediately obvious.
Fortunately, it can be readily proven using elementary Laplace transform
manipulations (see Appendix A) that for any given transfer function GDC(S) in the
92
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
synchronous reference frame, the corresponding overall transfer function of an
equivalent stationary filter
GAC(S)
shown in Figure 4.3 is exactly given by:
GAC (s) = GDC (s - jo)o) + GDC (s + jco0
(4.5)
where co0 = angular rotating frequency of the synchronous reference frame.
If a simple first-order low pass filter with cut-off frequency of coc is used in the
synchronous frame, ie.:
1
(4.6)
(S/6)C)
then using (4.5) it can be shown that
2
c
+COO2)
(4.7)
This is seen to be a second-order resonant type network with a peak magnitude at the
resonant frequency of
°>r =
'o
• - c
-°>c
(4.S)
The parameter coc determines the width of the resonant peak. If coc « a>0, then (4.7)
can be simplified to
••'1
(4.9)
i
V4
which has a resonant peak of 1 centred exactly at s = jo)0. Thus (4.7) and (4.9) provide
the mathematical basis for linear analysis to be carried out on the entire system. Also,
93
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
as (4.9) requires less signal processing on a DSP to implement compared to Figure
4.3, it is proposed for use in the T-PQC.
The transfer function for the harmonic extraction algorithm used in the proposed TPQC is thus given by
GM--T-
^
2o)cs
• + •
2(ocs
(4.10)
where cos = system frequency = 2TI (50) rad/s. The frequency response of G(s) given
in (4.10) is plotted in Figure 4.5 for two values of coc. Note that G(s) has values of 1
at the compensation frequencies of 150Hz, 250Hz and 350Hz, and is heavily
attenuated at other frequencies. The smaller the coc, the more selective G(s) is and the
heavier is the attenuation at other frequencies. Note also that the gain of G(s) at 50Hz
is not 0, but is 0.01 for coc = lOrad/s and 0.001 for coc = 1 iad/s. Given that the 50Hz
fundamental component in vD is at least 10 times larger than any other harmonic
components, there will be a significant amount of 50Hz component in ihar*, which
should ideally contain low order harmonics only. If uncompensated for, this would
lead to an unnecessary increase in the VSI current rating. However, in the steady state
at least, the 50Hz component in ihar* will be compensated/corrected by the DC bus
regulation and reactive power compensation loops, since they directly control the
50Hz active and reactive currents respectively.
I
Even so, it is important to ensure as much 50Hz attenuation in G(s) as is practically
possible (ie. ©c as small as possible), so as to minimise the extent of interaction
between the various control loops. (This tends to degrade transient performance and
complicate control loop design). The downside of using a small (oc is that it makes the
filter performance mo-e sensitive to frequency variations and also leads to a slower
transient response. Fiuvermore, an accurate implementation of a resonant filter with a
small coc is difficult on a low-cost 16-bit DSP due to coefficient quantisation and
94
CHAPTER 4:
i;
-20
CD
•§
-40
O)
—
—
— -
250Hz
150Hz
• wc=1 rad/s wc=10 rad/s
0
£•
A New Traction Power Quality Conditioner for 25kV Railway Systems
JV
—
j
•
—
•—.
I
Frequency (Hz)
10
t
—
7 ^
r—"
-80 -
100
350Hz
I
I
10
I
r,
\
\
S1
Q
0-
I
Q_
-50 1
S —J
i
-100
10
Z
Frequency (Hz)
.
.
•
i
.
J
10
Figure 4.5: Frequency response of equation (4.10) for coc = 1 rad/s and 10 rad/s
roundoff errors. In practice coc values between 5-15 rad/s have been found to provide
a good comp.- wnise.
4.2.3
Compensation Performance
The T-PQC is controlled to present a low impedance of 1 l\K Q at the third, fifth and
seventh harmonic frequencies, which will lower the system harmonic impedance as
seen by a locomotive load at any point along the feeder. The motivation is that
locomotive loads have a large enough DC inductance, so that to a good approximation
they can be treated as a harmonic current source, ie. load harmonics are largely
determined by locomotive parameters rather than by system voltage. This means that
the feeder harmonic voltages are the products of the load current harmonics and
system impedance as seen by the load. Therefore by reducing the system harmonic
impedance the harmonic voltages can be lowered.
95
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
Locomotive
Load
, +
i
Substation
Equipment
zs(s>
V2(x)
r
Zc(s)
T-PQC
_
K* =0
-H
x =L
x= (t
Figure 4.6: Distributed parameter line model of railway feeder
To appreciate the compensation performance of the T-PQC, it is instructive to
examine the driving-point impedance of the system as seen by a locomotive load
along the feeder. The distributed parameter line model of a railway system is shown
in Figure 4.6, where the substation transformer and T-PQC have been represented by
equivalent impedances Zs(s) and Zc(s) respectively.
For a transmission line with distributed parameters R, L, G and C. the steady-state
time-harmonic solution is given by [149]
(4.11)
(4.12)
where position x is measured from the substation, and Zo and y are the characteristic
impedance and propagation constant respectively given by
R + jcoL
G + jcoC
y{(o) =
(4.13)
jcoC)
(4.14)
96
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
It can be readily shown that the driving-point impedances
looking into the
substation and T-PQC of the system at A- = £x are given respectively by
, +Z0
Zo cosh/ • ix + Zs sinh/ • £l
(4.15)
and
Zc cosh/ • (L - £l) + Zo sinh/ -{L-£x)
Zo cosh/ • ( Z - £ } ) + Zc sinh/ • (L-
tx)
(4.16)
Therefore the total impedance as seen by a locomotive load at x = £x is
(4.17)
Note that since Zo and y are functions of frequency co, the impedances Zi, Zi and Z
are also functions of ©as well as functions of I,.Equation (4.17) is used to
determine the harmonic impedance seen by a locomotive load at various locations
along a 30km feeder section, as shown in Figure 4.7, for ©c = 5 rad/s and K = -0.2
Q'1. It is seen that the T-PQC produces notches at 150Hz, 250Hz and 350Hz, whilst
the impedance at other frequencies is not modified significantly. Thus the low order
harmonic voltages generated by the load harmonic currents are significantly reduced
by the T-PQC.
Again using (4.17), the third, fifth and seventh harmonic impedances as seen by a
load are plotted as a function of the locomotive position along a 30km feeder section
in Figure 4.8, Figure 4.9 and Figure 4.10 respectively. K = -0.2 is used, ie. the T-PQC
behaves as a 5Q resistor at third, fifth and seventh harmonic frequencies. It is seen
that all three low order harmonic impedances are reduced by the T-PQC at all points
along the feeder section.
97
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
The ratio of compensated harmonic impedance to uncompensated harmonic
impedance, which provides a measure of the harmonic voltage reduction as a function
of load position, is summarised in Figure 4.11 for the third, fifth and seventh
harmonic frequencies for K = -0.2. It should be noted that the further away the
locomotive load is from the end of the feeder section, the less effective is the
harmonic compensation provided by the T-PQC. However, at such positions the
harmonic distortion is also less severe to begin with, because the load sees a lower
amount of uncompensated source/feeder impedance, as indicated in Figure 4.8, Figure
4.9 and Figure 4.10.
(a)
80
1 —r
r -i—i-i r-i
— - Ur•compensated
smpensated with K = -0.2
\i
:
i
i
i
Tf
40
J-20
i-
\\/
II
I—'
.——
——
( b)
80
III
1
I I
! 60
J
401-20
\
\
T
_ —
:::
:
%
1
(c)
80
; ; ; i
CO
40-
V
i
i
V\
i
*
-
J-20 ———•
L
_ _
J
L-
0
(d)
80
S60
I 40
9-20
A
.^^—J
10
\
V
1
1
1
1
1
1
1
1
L L L.
— " * •
l_l
1
\
/
I 1
10
10
10
Frequency (Hz)
Figure 4.7: Impedance as seen by locomotive load at (a) Okm, (b) 10km, (c) 20km and
(d) 30km from feeder substation of a 30km feeder section
98
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
70
-1
1—
— - Uncompensated
Compensated with K = -0.2
*•*
•*-
60
**•
40
s
f
30 -
20-
'
10 -
10
15
20
Locomotive position along feeder (km)
25
30
Figure 4.8: 3 rd harmonic impedance as seen by a locomotive load at different positions
along feeder section, before and after compensation (K=-0.2, coc= 5rad/s)
120
— - Uncompersated
—— Compensated with K = -02
100 -
g 80
E
u
S 40
—
—
20 -
10
15
20
25
30
Locomotive position along feeder (km)
Figure 4.9: 5th harmonic impedance as seen by a locomotive load at different positions
along feeder section, before and after compensation (K=-0.2, coc= 5rad/s)
99
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
160
—
Uncompensated
Compensated with K = -02
i
uo 120 -
a 100
r
80-
o
'c
(0
60 -
40 •
—
.
—
20 •
^
10
15
20
Locomotive position along feeder (km)
_
25
30
Figure 4.10: 7th harmonic impedance as seen by a locomotive load at different
positions along feeder section, before and after compensation (K=-0.2, coc= 5rad/s)
0.7
— 3rdtermonic
— • 5th harmonic
7th harmonic
8
•g 0.6 £
f
H 0.5
I
|o.4
o
S
0.3 C>^
?x 02
o
.S 0.1
10
15
20
25
30
Position along feeder (km)
Figure 4.11: Feeder voltage distortion gain for the third, fifth and seventh harmonic
frequencies as a function of locomotive load position along the contact feeder length
(K=-0.2, toc= 5rad/s)
100
CHAPTER 4:
4.2.4
A New Traction Power Quality Conditioner for 25kV Railway Systems
Gain Considerations
It has been assumed thus far that by controlling the T-PQC to behave as a low
impedance at the compensated harmonic frequencies, the system impedance seen by a
locomotive load anywhere along the feeder will be lowered, leading to reduced feeder
harmonic voltages. This is certainly true for the examples shown in Figure 4.7 to
Figure 4.11. If the feeder line is 'sufficiently short' (in comparison to the wavelength
of interest) so that it can be accurately represented by its longitudinal (or series)
impedance alone at the harmonic frequencies of interest, then this conclusion is quite
trivial. However, if the feeder line is not so short and the full distributed line
representation is needed, then the result is not immediately obvious. Indeed, basic
transmission line theory shows that a short-circuited lossless transmission line has an
input impedance (seen from the other end) whose absolute value ranges from 0 to +°o,
depending on the length of the line [149]. A thorough investigation is therefore
necessary to ensure that the effectiveness of T-PQC harmonic compensation loop can
be guaranteed under all possible railway operating conditions.
This problem is best understood by examining the standing wave pattern along the
transmission line. Consider a simple lossless transmission line of length L terminated
in a resistive load RL at one end and fed by a sinusoidal voltage source Vs of a certain
frequency at the other end. Using the general solutions of (4.11) and (4.12), it is
possible to show (see Appendix A) that the voltage magnitude along the transmission
line is given by
\V(x)\ =
J3-L
sin2
J3-x + (Ro IRL)2 sin2
fix
(4.18)
where Ro and P are defined by equations (4.13) and (4.14) respectively and position x
is measured from the load end.
101
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
y
/
\
//
' J
\
\\\
\
\
\
\
\ 1/
/> w
/1
j /
A—\
\
V
\
V
\
/
k
/
/
w
/
/
/
\\
/
\\ .
\
/
\
\
//
'*
If
\\>\
i
•'
>A \
1/
/
\
i
/
»
\
\
\
\
/
'
/
i
/
i
/
\
i
i
i
•r
0
Load
End
i
i
i
= o\
'
/
/
i
/
i
i
\ /
\
\lV
\
t
\
/
\
t
«
•
% i
V
A/
A
i
i
Line Length x
i
i
t
\
\lV
j
\ ;
V
Source
End
Figure 4.12: Voltage profile on lossless line with different resistive terminations
The standing wave magnitude |V(x)| of (4.18) is plotted in Figure 4.12 to illustrate the
effect of reducing the load termination RL. Starting with RL = «> which corresponds to
an open-circuit termination, the voltage possesses maxima and minima at fixed
locations along the transmission line; the ratio of maxima value to minima value is
large. When RL is reduced to 2Ro, the maxima reduce in value, and the minima value
increase in value; the ratio of the two reduces. When RL is equal to the characteristic
resistance RQ, the voltage profile is flat along the line; there is no maxima or minima.
When RL is further reduced to Ro/2, maxima and minima reappear but have swapped
positions. Finally when RL is reduced to 0, the maxima continue to increase in value,
and could end up with values higher than that under the open-circuit condition. Note
that for this transmission line and at this frequency, reducing the value of the
terminating impedance does reduce the voltage magnitude at the load end (x=0), but
does not necessarily guarantee that the voltage magnitudes at other positions along the
line also reduce. In this case, using a low or zero impedance can lead to worse voltage
distortion along the line; the best termination impedance would be Ro, as it provides
the lowest maxima along the line. This observation is quite different from that for a
short line which can be represented by its series impedance alone. In that case, it is
102
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
obvious that the lower the terminating impedance, the lower is the voltage at all points
along the line.
Indeed, it can be readily proven analytically that —
-is always positive for all
dRL
values of G < x < L, provided Z, < —, where X is the wavelength of the voltage (see
4
Appendix A). This means that if either the transmission line length is short enough or
the frequency in question is low enough such that L < — is satisfied, then the lower
4
the terminating resistance RL used, the lower will be the voltage magnitude |V(x)|
along the entire line. Although the above discussion pertains to lossless lines, similar
conclusions can be drawn for a lossy line, except that now the voltage profile decays
with increasing distance from the source.
The situation for a railway system is slightly more complicated as the harmonic
current source (locomotive load) is located somewhere along the transmission line, as
indicated in Figure 4.6. The voltage profile along the feeder line is given by two sets
of equations, one each for the left and right hand line sections respectively:
*-r-x
(4.19)
(V+e rx
'
and
= V2+e~rx +V2~e
(4.20)
The four constants Vi+, Vf, V2+, V2" in (4.19) and (4.20) can be expressed in terms of
s, Zc and im using the boundary conditions
103
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
(4.21)
(4.22)
(4.23)
(4.24)
The solution for a 30km railway feeder section is plotted in Figure 4.13 and Figure
4.14. Figure 4.13 shows the third, fifth and seventh harmonic voltage profiles
generated by a harmonic current source at the 10km position. For each harmonic
frequency, three terminating conditions are shown, namely open-circuit (no
(a)
-40
07
o>30
3
Zc = 350Ohms
Zc = 5 Ohms
Z 20
—
—
—
—
•
~~—-—.1
10
10
20
15
25
30
(b)
I"
§,60
40
L-
ii———1-.
f
J
"
10
20
25
30
(c)
£.100
S
15
- ,
80
J—
1
—
-
—
.j—
^
—
„
..
'
•
•
i
g 60
o
i
i
•
———i
20 p
i
1
10
15
20
Position along feeder (km)
25
30
Figure 4.13: Harmonic voltage profiles for 30km feeder section due to a single
harmonic current source of lkA at 10km from substation (a) 3rd harmonic (b) 5th
harmonic (c) 7th harmonic
104
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
compensation), 350Q (roughly the characteristic impedance of the line) and a low 5Q
(ie. K = -0.2) termination. It is seen that for all three harmonics, with open-circuit
termination the voltage harmonics along the line are high. When the line is terminated
with its characteristic impedance, the voltage harmonics at all points along the line
reduce marginally. Finally when the line is terminated with a low 5Q impedance,
there is a marked reduction in the voltage harmonics at all points along the line.
Figure 4.14 shows the harmonic voltage profile generated by a harmonic current
source at the 20km position for the same 30km railway feeder. The same conclusion
is observed, namely low impedance termination is most effective in suppressing the
voltage harmonics throughout the entire feeder section. For this 30km feeder and the
harmonic frequencies concerned, terminating with the characteristic impedance is not
useful as it provides negligible improvements.
(a)
5-60
I
I
^50
o>
|
— - Zc = o/c
40
0 30
|
•
Zc = 350 Ohms
Zc = 5 Ohms
20
1 10
co 0
10
I
15
20
25
1
1
30
(b)
5-100
I
1
80
!
o
60 40 -
rt
20
i
0
i
~
1
1
t
10
15
—
•
—
—
.
20
25
20
25
30
(C)
5-150
I
1
s. 100 •
50 .
f
p
0
1
• —
1
—
10
15
—
30
Position along feeder (km)
Figure 4.14: Harmonic voltage profiles for 30km feeder section due to a single
harmonic current source of lkA at 20km from substation (a) 3rd harmonic (b) 5th
harmonic (c) 7th harmonic
105
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
For comparison, Figure 4.15 shows what could be expected of the harmonic voltage
profile for an unrealistically long 300km feeder based on the same line parameters as
before. The harmonic current source is located at the 100km position. Because a truly
long line is involved, it is observed that there is a significant rise in voltage magnitude
at the open-circuit end of the line compared to the sending end. This is the Ferranti
effect as predicted from transmission line theory. In terms of lumped circuit model,
this phenomenon can also be interpreted as a resonance effect between the shunt
capacitances and series inductances. At the third harmonic frequency, the use of a low
impedance again tends to suppress the harmonic voltage magnitude at all points
throughout the line. At the fifth harmonic frequency, still a big improvement is
obtained by using a low impedance termination, although it is observed that in region
around the 100km position there is a small increase in harmonic voltage compared to
(a)
<5-4O0
_ _ _ _ _
_ _ _
S>300
_—
— — ~~
!
J
— - Zc = o/c
Zo = 350 Ohms
—— Zc = 5 Ohms
»- —
.9 200
I 100
~
••»—-
T~
P
50
150
100
"*"" ;——
200
250
300
250
300
800
en 600
CO
400
1
200
Co
-c^
—
0
50
100
200
150
—
,
(0
. 800
_ _ _ _
^
1^
.
1 **- — •
50
100
•
—
—
•— "
1
150
200
250
300
Position along feeder (km)
Figure 4.15: Harmonic voltage profiles for 300km feeder section due to a single
harmonic current source of lkA at 100km from substation (a) 3rd harmonic (b) 5th
harmonic (c) 7th harmonic
106
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
the open-circuit (uncompensated) case. However, at the seventh harmonic frequency,
a low impedance termination gives rise to a huge bulge in the voltage profile well
above the maximum of the open-circuit case [Figure 4.15(c)]. Thus for a line of this
length, the characteristic impedance termination seems most suitable instead for the
seventh harmonic frequency.
Also of interest in Figure 4.13 and Figure 4.14 is that with a low impedance
termination, the harmonic voltages at the feeder substation (0 km position) are also
significantly reduced. This means that the harmonic currents flowing into the
substation decrease. Effectively the T-PQC at the terminating end has partially
diverted and absorbed the locomotive harmonic currents. This is of practical
significance since the power company operating the high voltage network often has
strict stipulations about the levels of harmonic current at the point of common
coupling, particularly when the high voltage side is weak with a low fault level
[33,150]. Although not the main compensation objective, the reduction in substation
harmonic current is an additional benefit of the T-PQC.
Overall, the analysis suggests that if the feeder is shorter than about a quarter of the
signal wavelength, then the smaller the terminating impedance, the better is the
reduction in harmonic voltage magnitude. However, if the feeder is longer than a
quarter of the signal wavelength, the harmonic voltage profile needs to be carefully
examined to determine a suitable choice of terminating impedance to obviate a
possible unexpected increase in harmonic voltage some.vhere along the line. In this
case terminating with the line's characteristic impedance seems to be more
appropriate.
Note that the propagation speed (in km/s) of electromagnetic waves in a transmission
line is given by
1
v=
(4.25)
where L and C are the series inductance and shunt capacitance per km. The
wavelength (in km) of a wave of frequency f is given by
107
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
(4.26)
This problem of active power filter termination was also studied by Wada et al. [103]
in relation to a public distribution feeder. Even though the feeder studied was only
9km, it had L rge power factor correction capacitors evenly distributed along the line.
From equation (4.26), it is clear that the wavelengths on an equivalent distributedparameter line are much shorter with large values of C. Under those circumstances, it
is imperative to operate the active power filter to provide a characteristic impedance
termination.
For typical 25kV railway systems, the propagation speed is slightly less than the
speed of light in free space (3 x 108 m/s). For the system used in this thesis (see
Chapters 6 and 7 for further information), L = 1.38mH/km and C = O.OlluF/km so
that v = 2.57 x 108 m/s. The relevant wavelengths are summarised in Table 4.1.
Typically 25kV railway feeder sections are 15km to 30km long [8,151], limited by the
voltage regulation requirement. With reactive power compensation to provide voltage
support, it has been proposed to double the conventional section lengths, up to 60km
in length [7]. It is seen that this is well below the quarter wavelength even at the 7th
harmonic frequency. Even during second emergency conditions (see Section 2.1)
when each feeder transformer has to feed twice the normal feeder length, the feeder
line is still comfortably less than 183km. Thus for controlling low order harmonics up
to the 7th harmonic on railway systems, it is appropriate to have the T-PQC providing
a low impedance (resistance) termination. Doing so will always ensure that the
harmonic voltage magnitudes are mitigated at all points along the feeder. In theory,
A. (km)
A,/4(km)
3rd harmonic (150Hz)
1711
428
5th harmonic (250Hz)
1027
256
7th harmonic (350Hz)
733
183
Table 4.1: Wavelengths of a typical railway system
108
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
the lower the terminating impedance, the lower is the harmonic distortion. In practice
how low the impedance should be depends on stability considerations of the system,
the rating of the T-PQC and on how sharply tuned the harmonic extraction algorithm
is.
4.3
REACTIVE POWER COMPENSATION
The objective of the reactive power compensation loop is to inject a controllable
amount of fundamental frequency (50Hz) reactive current. Equation (2.2) shows that
by injecting a suitable amount of purely capacitive compensation current, the system
fundamental voltage can be boosted to any reasonable level, even possibly well
beyond the nominal system voltage. The T-PQC is controlled to inject the right
amount of reactive current to bring the terminal voltage vD up to a set point level,
much like the outer voltage loop of a conventional transmission line STATCOM
discussed in Subsection 3.3.1.
As shown in Figure 4.2, a running window rms calculator is used to determine the rms
value of VD, which is then compared against a voltage set point. The error signal
passes through a proportional plus integral (PI) controller which demands a certain
amount of reactive current magnitude I<,\ Iq* is then multiplied by a sine wave 90°
leading with respect to vD to obtain the instantaneous fundamental reactive current
demand iq*. The output of the PI controller is internally limited to prevent the VA
rating of the inverter from being exceeded. Obviously, the VA rating of the inverter is
sized according to the intended loading level and required voltage regulation limits.
4.4
DC Bus VOLTAGE CONTROL
The objective of the DC bus voltage control loop is to regulate the DC bus (capacitor)
average voltage to a fixed value. For proper operation of the T-PQC, the DC bus
voltage needs to be reasonably constant. Without an explicit control loop for the DC
bus, the DC capacitor will discharge quickly to zero as its stored energy is consumed
by the inverter switching and conduction losses as well as DC capacitor leakage loss.
The DC bus voltage controller demands a small in-phase fundamental current to flow
109
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
into the inverter, transferring just enough real power from the system to replenish the
inverter losses in the steady state.
In a conventional STATCOM that uses fundamental square-wave modulation, the DC
capacitor voltage is varied according to the required output fundamental
voltage/current, as the modulation index (ratio between the output voltage and DC bus
voltage) is inherently fixed (Subsection 3.2.1). For a PWM VSI, the output voltage
magnitude is directly controllable by means of the modulation index, giving one extra
degree of freedom (Subsection 3.2.2). As such, two basic approaches of controlling
1
the DC bus voltage are possible for PWM STATCOM [50]. The first is to maintain
the DC bus voltage at a fixed value, and vary the modulation index in response to the
output
I
fundamental
voltage/current
demand
[59]. As
this
excludes
the
charging/discharging dynamics of the DC capacitor from the main control loop, it
tends to give better transient response. The second approach is to fix the modulation
index at the maximum value, and vary the capacitor voltage in response to output
fundamental
voltage/current demand, much like a STATCOM
employing
fundamental square-wave switching [51]. The benefit of using this approach is that
the modulation index can be kept at the maximum value under all operating
conditions. A high modulation index is always associated with a lower THD in the
output voltage, since the PWM switching harmonic magnitudes do not scale with the
modulation index [54]. Also a high modulation index incurs lower switching losses
for a given output voltage.
For active power filter applications, even though the same PWM VSI power stage is
used, the DC bus voltage has to be kept approximately constant. This is in contrast to
the two choices available for PWM STATCOM. This is because in active power filter
applications, the inverter is controlled to explicitly generate a voltage/current of more
than one frequency (fundamental, 3rd harmonic, 5th harmonic, etc); in a PWM
STATCOM, only a fundamental frequency voltage/current needs to be controlled.
Clearly, individual control of more than one frequency component is impossible to
realise by varying the DC bus voltage alone. In this case, the DC bus voltage needs to
be kept constant whilst the modulation indices for the individual frequencies are
varied. Hence the choice of the DC bus voltage control loop for the T-PQC is to
maintain a constant DC bus voltage.
110
CHAPTER 4:
I
A New Traction Power Quality Conditioner for 25kV Railway Systems
AV
/£
p-i
2) > Controller
r
Al
A\
sVjC
Figure 4.16: Small-signal control system block diagram for DC bus voltage loop
1
As indicated in Figure 4.2, the measured DC capacitor voltage is low-pass filtered to
remove the ripple in the measured capacitor voltage. When the inverter is supplying
fundamental reactive current, there will be significant lOOHz ripple in the DC
capacitor voltage. The low pass filter needs to provide adequate attenuation of the
ripple component to avoid generating unwanted harmonic components when it is
modulated by the 50Hz reference sine wave. The filtered voltage is compared against
a set point voltage to generate an error signal. The error signal passes through a
proportional plus integral (PI) controller which demands a certain amount of real
current magnitude Ip*. Ip* is then multiplied by a sine wave in-phase with VD to obtain
the instantaneous fundamental real current demand ip*. The output of the PI controller
is internally limited which prevents the VA rating of the inverter from being exceeded
during large transients.
The parameters of the PI controller can be designed using the small-signal control
system block diagram shown in Figure 4.16. Vs is the rms system voltage, VdC0 is the
average DC bus voltage, C is the DC capacitance, GLP(S) is the transfer function of the
ripple low pass filter and AI is the change in rms inverter current.
Two important parameters related to the DC bus voltage control loop are the choices
of DC bus voltage and DC capacitance. The DC voltage must be chosen high enough
so that the VSI is able to generate maximum rated current against the maximum
expected system voltage for the given coupling inductance, without entering too much
into over-modulation operation. Operation in over-modulation will inject low order
harmonics into the system in an uncontrollable fashion and should therefore generally
be avoided. On the other hand, a higher than necessary DC bus voltage incurs extra
switching losses in and stresses on the inverter switches.
ill
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
The DC capacitance value is chosen to limit the DC bus voltage fluctuations to below
a certain level. If significant amount of fluctuation exists on the DC bus, the output
voltage THD deteriorates. Two types of fluctuation can be found on the DC bus. The
first is a steady-state effect caused by the inverter compensation current.
Corresponding to the 50Hz reactive current supplied by the inverter, a harmonic
current of lOOHz flows through the DC capacitor. Similarly a third harmonic inverter
current gives rise to lOOHz and 200Hz DC capacitor currents. These capacitor
currents generate capacitor voltage fluctuations at the respective frequencies, although
the lOOHz component predominates since the capacitor impedance decreases with
frequency. The second type of fluctuation is associated with sudden load variations,
which tend to cause the DC capacitor average voltage to deviate transiently from the
set point. Both types of fluctuations are sub-cycle events beyond the correction
capability of the DC bus voltage control loop, which is a relatively slow loop intended
to regulate the long term average DC bus voltage value. The only way to suppress the
fluctuations is to use a sufficiently large DC capacitor. A larger capacitor is of course
more costly, and there is usually a trade-off between size and cost. In this thesis,
digital simulation was used for capacitor sizing.
4.5
SUMMARY
hi response to the unique requirements of 25kV railway systems, this chapter has
presented a novel traction power quality conditioner (T-PQC) capable of
simultaneously providing harmonic and reactive power compensation. The associated
control algorithms have also been discussed and analysed in detail. By controlling
itself to appear as a low impedance at the third, fifth and seventh harmonic
6
t
!
frequencies, the T-PQC is able to significantly suppress harmonic voltages throughout
the entire feeder section, thus improving the pantograph average voltages regardless
of the locomotive position on the feeder. A unique feature of the conditioner is the use
of selective harmonic compensation, as it accomplishes the compensation objectives
of railway systems with a minimum inverter bandwidth rating.
It is also demonstrated in this chapter that 25kV railway systems are short enough at
third, fifth and seventh harmonic frequencies to warrant the use of a low impedance
112
CHAPTER 4:
A New Traction Power Quality Conditioner for 25kV Railway Systems
termination for harmonic mitigation. In contrast, in a general public distribution
network, the presence of many power factor correction capacitors may require
characteristic termination, which can severely restrict the usefulness of voltage
detection based harmonic compensation.
Whilst the basic form of T-PQC presented in this chapter may be useful in some
traction applications, it has certain limitations. These limitations are addressed in the
next chapter, which presents a more advanced form of the traction power quality
conditioner based on multilevel inverters and takes advantage of a passive damping
filter to extend the capability of the T-PQC.
113
CHAPTER 5; A ROBUST MULTILEVEL
HYBRID POWER QUALITY CONDITIONER
FOR 25KV RAILWAY SYSTEMS
Chapter 4 has presented the Traction Power Quality Conditioner (T-PQC) which
addresses the low average voltage and low rms voltage problems in 25kV railway
systems by means of low order harmonic compensation and reactive power
compensation. On many railway systems, the threat of harmonic overvoltage is
another pressing issue that needs to be dealt with as well. Furthermore, the switching
frequency and output power obtainable from a conventional H-bridge as presented in
the previous chapter are rather limited, resulting in less than ideal noise ripple
performance and limited power flow control on the traction systems.
To address these shortcomings, this chapter proposes a more robust hybrid power
quality conditioner which incorporates two major extensions, namely the addition of a
passive damping filter and the adoption of a hybrid multilevel inverter topology. The
chapter first begins with a brief review of currently available multilevel converter
topologies and selects the appropriate topologies for further investigation based on the
criteria of reduced active switch count and ease of control. Next, the multilevel hybrid
T-PQC is presented, and its improvements over the basic form of the T-PQC are
clarified. Particular attention is drawn to the hysteresis inner current loop with the
s
s%
I
Si
i
three-level hysteresis current regulation strategy used for controlling a conventional
H-bridge examined in detail. Based on these concepts, new hysteresis current
regulation strategies with both a wide tracking bandwidth and fast dynamic response
are developed for the reduced inverter topology as well as the cascaded topology.
Finally, the capacitor voltage balancing issues for multilevel inverters are investigated
to further demonstrate the practicality of the proposed multilevel compensator.
114
CHAPTER 5:
5.1
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
MOTIVATIONS FOR MULTILEVEL HYBRID TOPOLOGY
Whilst the basic form of T-PQC proposed in Chapter 4 is effective in improving the
traction supply quality, it has certain practical limitations. As pointed out in Section
2.6, the presence of a l-2kHz harmonic overvoltage is an annoying feature of many
25kV railway systems, as it tends to promote premature failures of connecting
equipment. It is thus desirable to have some control over the harmonic overvoltage.
This issue has not been specifically dealt with by the T-PQC in Chapter 4, as it only
1
addresses power quality at the fundamental frequency (rms voltage) and at low order
harmonic frequencies (average voltage).
Secondly, in order to ensure that the switching harmonics do not trigger any harmonic
overvoltage, simulation studies have shown that the two-level VSI (conventional Hbridge) needs to switch at an average rate of 3.5kHz or higher. This immediately
places a constraint on the MVA power rating of the inverter, since the higher the
switching rate of the active switches, the higher also are the switching losses and
therefore the current passed/voltage sustained must be reduced accordingly to prevent
excessive temperature rise. Constraints on the inverter MVA rating in turn mean that
the amount of reactive power the inverter can supply, and therefore the amount of
permissible traffic growth, is limited. In particular, with current generation IGBT
technology, the basic T-PQC is not considered a suitable means for doubling the
existing feeder lengths to 50km, which would require up to 20MVAR of reactive
power in order to maintain the minimum track voltage at 19kV [24],
Thirdly, the switching harmonics of the basic T-PQC can cause a significant amount
of high-frequency switching ripple and a relatively poor total harmonic distortion
(THD) in the overhead feeder voltage (but still much better than before any
compensation is applied), especially towards the end of the feeder section where the
T-PQC is connected. This is usually not an issue as traction loads are quite tolerant of
a distorted supply. However, on some systems high-frequency noise must be kept to a
minimum, for example, to avoid interference with nearby communication equipment.
Since the feeder voltage switching ripple is essentially determined by the ratio of the
overhead line's impedance to the T-PQC's coupling (or filter) inductance (Lc in
Figure 4.1), it can be reduced by using a larger coupling inductance. However, this
115
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
would not only be more costly but would also reduce the amount of reactive power
that can be supplied by the T-PQC for a given DC bus voltage. Hence, the value of
the coupling inductance is always a compromise. A more cost-effective means of
reducing the switching ripple is therefore preferred.
To address all the above limitations and to offer a more robust and practical power
quality solution to a wider range of traction systems, it is thus proposed that two
i
I
extensions be made to the basic T-PQC topology, namely by adopting a multilevel
inverter topology and by adding a second order RLC damping filter. Before
describing the proposed extensions in detail, the next section briefly reviews state-ofthe-art multilevel inverter topologies to help with the understanding of the final
design.
5.2
REVIEW OF MULTILEVEL INVERTER TOPOLOGIES
Multilevel inverter systems are often proposed for high power systems, since they
have particular advantages that suit these types of applications. The main operating
concept of these inverters is to divide the DC link potential into multiple sections, so
that each phase-leg can switch between multiple voltage levels (rather than the two
voltages only of a two-level inverter). Advantages of multilevel inverters include the
higher power output levels that can be achieved using commercially available power
switches, and the reduced magnitude and higher frequency switching harmonics that
are produced by the modulation process [152]. This in turn means a reduction in
passivv filtering requirements, and for traction systems in particular, the potential to
minimise the risk of triggering system resonances in the frequency range of l-2kHz.
Although various different topologies have been reported in the literature, multilevel
inverters can generally be divided into four classes, each having a unique topological
layout. The four classes are commonly referred to as diode-clamped, flying-capacitor,
cascaded and hybrid inverters.
116
CHAPTER 5:
5.2.1
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
Diode-Clamped Multilevel Topology
A five-level diode-clamped inverter is illustrated in Figure 5.1(a) [153]. As can be
seen, the inverter generates the various DC voltage levels by subdividing the primary
DC bus with a series string of capacitors. For a five-level converter, 2 capacitors are
required and each capacitor is charged to a voltage equal to the DC link voltage
(a)
IGBT
(b)
IGBT
IGBT
IGBT
IGBT
IGCT
IGBT
IGBT
?' <J
(c)
(d)
Figure 5.1: Five-level inverter topologies, (a) Diode-clamped (b) Flying-capacitor (c)
Cascaded (d) Hybrid (reduced). (Ideally Vdc, = Vdc2 = Vdc)
117
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
divided by 2. In addition, clamping diodes are included to ensure that each switch
never blocks more than one individual capacitor voltage.
I
The main advantage of the diode-clamped topology is that the multiple voltage levels
required for the inverter are easily obtained with a low cost string of DC capacitors.
However, this gain is achieved at the expense of possible fluctuation of individual
capacitor voltages due to the non-uniform power drawn from them. This issue is
commonly referred to as the Capacitor Neutral Potential Balancing problem. Much
effort has been directed at solving this problem but most attempts are effective only
for diode-clamped inverters with a smaller number of DC levels. Indeed, this
complication has significantly limited the application of the diode-clamped topology
to higher power systems.
5.2.2
Fiying-Capacitor Multilevel Topology
The configuration of a five-level flying-capacitor inverter is illustrated in Figure
5.1(b) [154]. For this topology, each capacitor within a phase-leg is charged to a
different voltage level and the phase voltage waveform is then synthesised by turning
on the various switches within the phase-leg to combine the various capacitor voltage
levels. The only constraints with the switching process are that no capacitor is to be
short-circuited and current continuity between the DC link and the (inductive) output
has to be maintained at all times for each phase leg.
The flying-capacitor topology however has several disadvantages that have limited its
use. For example, before it can be modulated, each clamping capacitor has to be precharged to its required voltage level. This can complicate its control and hinder its
performance under ride-through conditions. Another problem is the rating of the
capacitors that form the clamping network. Since these capacitors have to sustain
large fractions of the DC bus voltage across them, the voltage ratings and ripple
current rating of these capacitors have to be considerably higher than those used with
the diode-clamped topology. Hence a flying capacitor system will generally be fairly
expensive.
118
CHAPTER 5:
5.2.3
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
Cascaded Multilevel Topology
The cascaded inverter, shown in Figure 5.1(c) for a five-level layout, is made up of a
number of single-phase H-bridges, each with its own isolated DC supply [155],
connected together in series. Due to its modular structure (series connection of Hbridges), the cascaded topology allows distributed control of each module, which is an
advantage as compared to the other two topologies discussed above. However, the
requirement that each H-bridge has its own DC source means that this converter
usually needs a costly multiple output winding transformer, which is a major
constraint for this topology.
5.2.4
Hybrid (Reduced) Multilevel Topology
The hybrid topology is based on the combined use of a three-level diode-clamped
phase-leg and a conventional two-level phase-leg, as illustrated in Figure 5.1(d) [156].
The two-level phase-leg is made up of power switches with a high voltage blocking
but not necessarily fast switching characteristic (eg. IGCTs), and switches between
±Vdc. The diode-clamped phase-leg is constructed using switches which have fast
switching characteristics but not necessarily high voltage blocking capability (eg.
IGBTs), and switches between the three DC levels of +VdC, 0 and -VdC. The hybrid
inverter therefore marries the best performance characteristics of current generation
power devices and can achieve similar performance to other five-level multilevel
inverter topologies with a reduced switch count (eg. 6 switches for a hybrid five-level
inverter as opposed to 8 switches for the other topologies).
Note that the term 'hybrid' can be used in two senses, one referring to the
combination of active and passive filter elements, and also to the inverter topology
discussed in this subsection. To avoid potential confusion, when talking about the
inverter topology, the hybrid five-level inverter topology is referred to as the reduced
five-level inverter topology in the rest of this thesis, whilst the term 'hybrid' L
reserved to signify the use of both active and passive elements.
119
CHAPTER 5:
5.3
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
PROPOSED MULTILEVEL HYBRID TRACTION POWER QUALITY
CONDITIONER
5.3.1
Hybrid T-PQC Topology
The proposed multilevel hybrid power quality conditioner is shown in Figure 5.2. For
the multilevel VSI, either a cascaded five-level inverter or the reduced switch-count
inverter is selected. The cascaded topology is selected because of its common usage in
power system applications and possible modular current control (as presented in
Section 5.4). On the other hand, the reduced topology is selected because of its
reduced structure and also its possible modular current control.
In principle transmission lines have an infinite number of resonant frequencies.
However, to date only harmonic overvoltages at the lowest feeder resonant frequency
have been reported [13,20,28-30], usually between l-2kHz, depending on the length
of the feeder section. In theory, these resonant overvoltages could be damped using
the active power stage, provided the inverter switched at least ten times faster than the
frequency to be compensated. Hence to damp the traction system resonance, the
active power stag'' would need to switch at 10-20 kHz. Clearly this is not practical at
MVA power levels, and a separate means of resonance damping is required.
50Hz HV Supply
HV source Impedance
= j1.0O, referred to 25kV)
Multilevel Hybrid Traction Power
Quality Conditioner
Feeding Transformer
(Z=j7.5n. referred to 25kV)
Z = (0.169 + jO.432) fl/km, C = 0.011 nF/km
Train Load A
Train Load B
Train Load C
Train Load D
Figure 5.2: 25kV railway system with proposed multilevel hybrid power quality
conditioner
120
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
Also shown in Figure 5.2 is a passive RLC filter connected in parallel with the VSI to
form a hybrid parallel filter system. The passive filter has a high-pass characteristic
and its main function is to damp out any l-2kHz harmonic overvoltage. The second
order passive filter has already been shown to be effective and practical in dealing
with the harmonic overvoltage problem [9]. The filter consists of a resistor, inductor
and a capacitor, whose values are determined iteratively to arrive at a surgeimpedance termination at the resonant frequency, whilst minimising the filter losses at
the fundamental frequency. Combined with the active power stage, the high-pass
damping filter also provides the second purpose of partially absorbing the highfrequency switching current ripple of the active power stage. As noted in Subsection
3.5.3, this form of hybrid parallel system exploits the falling cost and size of passive
filters at high frequency to provide a cost-effective compensation solution over a wide
range of frequencies.
5.3.2
Hybrid T-PQC Control
Figure 5.3 shows the proposed hybrid T-PQC control structure. As shown, no
modification to the outer loop controller structure is required, except for an addition
of a small proportional term P in the harmonic compensation controller to further
optimise the dynamic performance. The proportional term is not used for the basic TPQC as it would result in the feedback of a significant amount of switching ripple. As
for the inner current loop, hysteresis current regulation is again chosen. Details of this
are presented in the next section.
121
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
'3rd, 5th and ?h Harmonic Compensation
—*
vD(0
Current
Transducer
150Hz Resonant
Filter G3(s)
250Hz Resonant
Filter G5(s)
Five-Level Hysteresis
Regulator
350Hz Resonant
Filter G7(s)
Proportional Term P
DC Bus Voltage Control \
'Fundamental Voltage Control/Reactive Power Compensation*
vD(0
\__
Running
Window
RMS Calculator
p-i
Controller
TIDv •
V
X
Sine wave ' •
leading v^by 90"
•
X
*
»d*
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Five-Level
Inverter
Low Pass
Filter
k
90° Phase
Lead
vD(0
Zero-Crossing
Detection
Phase angle of 50Hz
Algorithm
component of v
D
50Hz
Siiie Wave
Generator
3.
Sine wave in phase with vD
N
^__
Figure 5.3: Controller block diagram of proposed multilevel hybrid power quality conditioner
122
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
Equation (4.17) is again used to determine the harmonic impedance seen by a
locomotive load at various locations along a 30km feeder section, as shown in Figure
5.4, for coc = 5 rad/s and K = -0.2 Q"1. In all four locations, it is seen that the passive
damping filter flattens out the resonant peak at around 1.3kHz, whilst the active
power stage produces notches at 150Hz, 250Hz and 350Hz. Thus both harmonic
voltages (both low order and those around the 1.3kHz resonant frequency) generated
by the load harmonic currents are significantly reduced by the multilevel hybrid
compensation system.
(a)
80
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10
Frequency (Hz)
Figure 5.4: Impedance seen by locomotive load at (a) 0km, (b) 10km, (c) 20km and
(d) 30km from feeder substation of a 30km feeder section
123
CHAPTER 5:
5.4
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
HYSTERESIS CURRENT REGULATION
The role of the inner current regulation loop is to modulate the inverter to inject the
demanded current determined by the filter outer control loop. There are many types of
current regulation schemes available, but the review in Section 3.8 has shown that
hysteresis control is especially attractive because of its extreme robustness,
unmatched dynamic response and wide command-tracking bandwidth. This makes it
particularly suitable for use in active power filter applications where close tracking of
non-sinusoidal multiple frequency current references is required. In many active
power filter applications, however, the convenience of full digital control together
with the need to circumvent the major shortcomings of hysteresis control has resulted
in the predictive current control also receiving a significant amount of attention
[157,158], particularly since it also boasts good dynamic response. Thus for active
power filter applications, the choice of current regulation essentially narrows down to
hysteresis or predictive techniques [159].
The major shortcomings of hysteresis modulation are the spread of switelling
frequencies and possible phase interactions in three-phase systems. For traction
applications, which are single-phase, phase interaction is not a problem. On the other
hand, the performance and even the stability of the predictive current regulation
technique depends critically upon an accurate model of the system impedance and
backemf (or supply voltage). Traction systems are weak, feeder voltage varies
significantly and therefore a model of the entire feeder needs to be included in the
equations of any predictive technique used. As feeder models contain resonances, and
the parameters are not known accurately, there is no guarantee that a predictive
technique will remain stable under different operating conditions, let alone closely
tracking the given reference current.
All these considerations suggest the simple and robust hysteresis technique as the
superior choice for traction applications, and therefore hysteresis techniques have
been adopted for the T-PQC. The only remaining uncertainty is whether the spread
spectral characteristics of a hysteresis technique are going to be a problem, as it does
increase the potential for the switching harmonics to coincide with the resonant modes
of the overhead system. At the same time, however, it should be remembered that
124
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
there is generally much less energy at any one switching harmonic frequency to excite
a significant overvoltage. As a consequence of investigating hysteresis current control
for the proposed hybrid filter (in simulation and experimentally), the results also
confirm that the spread spectral characteristics of a hysteresis current regulator do not
introduce resonant complications to the system especially when the passive filter is
present, as presented in Chapter 8.
Whilst hysteresis current regulation is well established for a two-level VSI, the
literature is more limited for hysteresis techniques for higher-level VSI topologies.
Hysteresis current control techniques are available for cascaded [160] and flying
capacitor [161] topologies, but the only hysteresis technique proposed [156] for the
reduced switch-count topology is sub-optimal and works only under very restricted
conditions. The next subsection explains the principle of three-level hysteresis current
regulation reported in [162], which is used to control a basic two-level VSI in this
thesis. Based on the three-level regulator, new and improved current regulation
strategies for the reduced and cascaded five-level inverter topologies are then
presented.
5.4.1
Conventional H-Bridge
In [162], three-level current regulation is achieved using two hysteresis bands placed
as shown in Figure 5.5. The upper hysteresis band Bl is used to switch the inverter
between the DC levels of 0V (lower limit of Bl) and -VdC (upper limit of Bl) while
the lower hysteresis band B2 switches the inverter between +V& (lower limit of B2)
and OV (upper lirnii of B2). At any instance, the current error (defined as measured
current minus the demanded current) will be confined within a hysteresis band until
the selected inverter state is insufficient to force the current error towards zero. This is
illustrated in Figure 5.5 where the current error is initially confined within the lower
band B2 and causes the inverter to switch between +VdC and 0V. This switching
process continues until time instant ti when the inverter voltage output of 0V is no
longer sufficient to reduce the current error, and it curves out and increases towards
the upper limit of hysteresis band Bl. This causes the inverter to switch to -Vdc and
the current error again reduces. The inverter now switches between -Vdc and 0V until
125
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
Current Error
/
^
f
7
i
k
k
-V- —
\
+v d c '
-v d c
Bi
\
/
B2Jr
Time
r
Offset Hysteresis
Bands
Zero
State
Inverter Switcheid
Output Voltage
Time
Figure 5.5: Band placements for three-level hysteresis current regulator.
the inverter voltage output is again insufficient to reduce the current error and it
curves out towards the lower hysteresis band B2.
Note that this hysteresis regulation technique introduces a positive or negative
tracking error into the average output current since the two bands are centred slightly
above and below the horizontal axis. However, this error can be corrected by adding a
compensation factor of half the band cifset placement magnitude to the demanded
current [162]. The polarity of this compensation factor is determined by the polarity
of the most recent inverter active output, i.e. positive (negative) factor added when
recent inverter output is positive (negative).
5.4.2
Reduced Five-Level Inverter
To control the single-phase reduced five-level inverter, the three-level current
regulator needs to be extended as shown in Figure 5.6. The resulting current regulator
consists of an inner three-level regulator and a single outer band two-level regulator.
The inner three-level regulator functions as before and controls switching between the
upper or lower three adjacent DC voltage levels of+VdC, OV and -Vdc. The outer twolevel regulator commands an offset of -Vdc (lower limit hits) or +VdC (upper limit
hits), whenever the three-level regulator acting alone cannot control the current. Note
that the polarities of the various bands have been arranged in such a way so that the
inverter output voltage is obtained by subtracting the output of the two-level regulator
from that of the three-level regulator.
126
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
LEGEND:
for three-lsvei regulator;
for two-level regulator
,, Time
2[
Offset
Hysteresis
Bands
Output of three-level
reg ulator
Output of two-level
regulator
+2V d c
-2V de
Commutation spike
Inverter lineline output
Figure 5.6: Band placements for reduced five-level hysteresis current regulator.
The switching sequence shown in Figure 5.6 illustrates this process, where the twolevel regulator initially commands an offset of +VdC- As the three-level regulator
switches, the overall inverter output voltage can be OV, -VdC or -2VdC. At time instant
t2, the inverter output of OV can no longer reduce the current error, and it continues
towards the lower limit of the outer hysteresis band. This causes the two-level
regulator to command an offset of -Vdc and the inverter output can now be controlled
over 0, +Vdc and +2VdC by the three-level regulator, to again confine the current error
I
within the inner three-level hysteresis bands Bl and B2. Notice that during this state
transition of the two-level regulator, a commutation spike of magnitude 2VdC results
since when the two-ievel regulator switches to -VdC, the state of the three-level
regulator remains at +VdC, giving rise to a sudden jump in inverter output from OV to
+2Vdc, as shown in Figure 5.6. The spike is unavoidable with the reduced converter
topology because two switch transitions are required (see Table 5.2) to change the
output voltage by only VdC when the two level regulator switches, and these
transitions can never happen simultaneously.
For the reduced five-level inverter, the digital logic outputs from the inner three-level
regulator and outer two-ievel regulator can be directly used to control the three-level
diode-clamped IGBT phase-leg and two-level IGCT phase-leg respectively without
127
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
requiring any external logic processing. This ensures that the two-level phase-leg is
switched once per fundamental cycle while the three-level phase-leg is pulse-width
modulated.
It is commented that the hysteresis current regulation strategy for the reduced fivelevel topology proposed in this thesis is robust and works under all system conditions,
unlike that reported in [156]. The inverter output voltage selection logic of the
strategy proposed in [156] depends also on the instantaneous magnitude of the sensed
system voltage (VD) instead of solely on the current error. As a result, excellent current
tracking can only be guaranteed when the inverter output voltage is in phase with the
system voltage. This in turn means that the strategy in [156] wastefully restricts the
amount of real power that can be transferred between the system and inverter to well
below the over-modulation threshold, and therefore represents a sub-optimal strategy.
5.4.3
Cascaded Five-Level Inverter
The proposed current regulation strategy can be further extended to control a cascaded
five-level inverter, as shown in Figure 5.7, using an inner three-level regulator with
LEGEND:
for inner three-level regulator;
for outer three-level regulator
Offset
^ c i! r I e J]L E l r 9- r _
Hysteresis. _ ,
Bands -
+v
Output of outer
three-level regulator
Output of inner
three-level regulator
Inverter lineline output
Figure 5.7: Band placements for cascaded five-level hysteresis current regulator.
128
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
bands {Bl & B2} and an outer three-level regulator with bands {B3 & B4}. Note that
here the inverter output voltage is obtained by adding the outputs of the two
regulators. Again, to illustrate its principle of operation, assume that the outer
regulator initially commands an offset of OV and the inner regulator switches between
+V<ic and OV when the current error is in band B2, and between OV and -VdC when in
band Bl. At time U, the inverter output of VdC is not enough to force the current error
to zero, causing it to continue towards the lower limit of hysteresis band B4. Upon
hitting B4, the outer regulator demands an offset of +Vdc, while the inner regulator
remains switching between +Vdc, 0 and -VdC to again confine the current error within
the inner hysteresis bands {Bl & B2}. The cascaded five-level inverter now switches
between +2VdC, +Vdc and OV. Note that for controlling a cascaded five-level inverter,
which uses only one type of power switches, the digital logic outputs from the two
hysteresis regulators should be externally processed to equalise switching stresses
among the eight switches. Implementation of such equalisation logic is
straightforward as discussed in [160] and therefore will not be further pursued in this
thesis.
Compared to the existing hysteresis regulation strategy for cascaded topology
reported in [160], this proposed strategy results in simpler hardware requirements.
This is because in the proposed strategy the same offset amount can be used for the
inner set {Bl & B2} and outer set {B3 & B4} of bands, and thus only a single offset
compensation factor needs to be added to the demanded current. In [160], however,
the outer set of bands requires a proportionally larger offset, which means hardware
implementation can be difficult as the number of voltage levels increases [163].
It is further mentioned that this current regulation technique can also be used for
controlling the reduced seven-level inverter proposed in [164], which uses the same
cascaded topology as in Figure 5.1(c), but now the upper H-bridge uses IGCT
switches and has a DC bus voltage of 2VdC, while the lower H-bridge uses IGBT
switches and has a DC bus voltage of VdC. In this case, the logic outputs from the
regulators can be directly used to control the reduced seven-level inverter with the
upper IGCT bridge switched at fundamental frequency and the lower IGBT bridge
pulse-width modulated.
129
CHAPTER 5:
5.5
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
DC CAPACITOR VOLTAGE BALANCING ISSUES
In the vast majority of mainstream inverter applications (sg. AC drives, UPS), the
inverter is used to supply real power. In those applications, DC capacitor voltage
balance is not a problem for the cascaded multilevel inverter topology, since the DC
capacitors are always fed by individual rectifier circuits which effectively clamp the
capacitor voltages to within a narrow range. However, DC capacitor voltage balance
can be a problem when the cascaded inverter is used in active power
filter/STATCOM type applications, where the capacitors are just floating. Needless to
say, being a derivative of the diode-clamp topology, capacitor balance on a reduced
topology always ne ' s to be treated carefully.
The 16 possible switching states of the cascaded five-level inverter are given in Table
5.1. A logic T signifies a turned-on switch, whilst a logic '0' represents a turned-off
switch. Note that many redundant switching states exist for the cascaded topology,
with ±Vd.; output each having 4 possible states and 0V output having 6 states. These
redundant states are usually selected cyclically to distribute the switching losses
equally among the eight switches. By ensuring equal switch utilisation together with
State
No.
v«
1
S'AI
(SSAI)
SA4
S'A3
(!S'A4)
(ISAJ)
Vdc, for
i«>0
Vdc2 for
OS'AJ)
i«,>0
Vdc for
U<0
Vdd for
i..t<0
2V*
1
1
1
1
Decrease
Decrease
Increase
Increase
2
Vdc
1
1
1
0
Decrease
No change
Increase
No change
3
Vdc
1
1
0
1
Decrease
No change
Increase
No change
4
Vdc
1
0
1
1
No change
Decrease
No change
Increase
5
Vdc
0
1
1
1
No change
Decrease
No change
Increase
6
0
1
0
1
0
No change
No change
No change
No change
7
0
1
0
0
1
No change
No change
No change
No change
8
0
0
1
1
0
No change
No change
No change
No change
9
0
0
1
c
1
No change
No change
No change
No change
10
0
0
0
1
1
Increase
Decrease
Decrease
Increase
11
0
1
1
0
0
Decrease
Increase
Increase
Decrease
12
-Vdc
0
1
0
0
No change
Increase
No change
Decrease
13
-V*
1
0
0
0
No change
Increase
No change
Decrease
14
-Vdc
0
0
0
1
Increase
No change
Decrease
No change
15
-Vdc
0
0
1
0
Increase
No change
Decrease
No change
16
-2Vdc
0
0
0
0
Increase
Increase
Decrease
Decrease
SAI
Table 5.1: Switching states of cascaded five-level inverter (ideally Vdci = Vdc2 = Vdc)
130
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner fe- AV Railway Systems
AC symmetry, the usages of the two capacitors will be equal, and the capacitor
voltages will be naturally balanced.
In contrast, the reduced five-level topology has only 6 allowable switching states,
with only 1 redundant state for 0 output and none for other output voltages. Table 5.2
shows the switching states for the reduced topology. During the positive half
fundamental cycle, SAI toggles between 1 and 0 to switch between 2Vdc and Vdc (SA2
held at 1), whilst SA2 toggles between 1 and 0 to switch between V<jc and 0 (SAi held
at 0). Similarly during the negative half cycle, SA2 toggles between 0 and 1 to switch
between -2V dc and -V dc (SAi heM at 0), whilst SAI toggles between 0 and 1 to switch
between -VdC and • (SA2 held at 1). SAI and SA2 thus experience the same number of
switching transitions over a fundamental cycle. Since the other two switches (S'Ai and
S'A2) in the three-level phase leg are just complements of the first two, it is ea;*y to see
that all four switches in the three-level phase leg will always have equal switching
losses without requiring special optimisation circuitries as needed for the cascaded
topology. This also means that the two capacitors in the reduced five-level topology
are utilised equally and will theoretically remain balanced over a fundamental cyr.le.
In practice, due to slight mismatches between the power switches and capacitors used,
the voltages across the capacitors can deviate from the ideal case of Vdci = VdC2 = Vdc
even when averaged over a fundamental cycle (see Figure 5.1). For the cascaded
topology, this voltage deviation (AVdC = Vdci - VdC2) can be sensed and an appropriate
redundant state selected, based on the polarity of the output current, to re-balance the
capacitor voltages (see Table 5.1). For the reduced five-level topology, an alternative
capacitor voltage balancing method as reported in [156] has to be used due to its lack
State
No.
S AI
SAJ
S'B.
(!S'AJ)
(!SBI)
V,),, for
i M <>0
V,ici for
i«u>0
Vfc, for
i«t<0
Vdc2 for
(!S'A,)
»«<o
1
2V*
1
1
1
Decrease
Decrease
Increase
Increase
2
Vdc
0
1
1
No change
Decrease
No change
Increase
3
0
0
0
1
No change
No change
No change
No change
4
0
1
1
0
No change
No change
No change
No change
5
-V*
0
1
0
Increase
No change
Decrease
No change
6
-2V*
0
0
0
Increase
Increase
Decrease
Decrease
Table 5.2: Switching states for reduced five-level inverter (ideally Vdci = VdC2 = V«iC)
131
CHAPTER 5:
A Robust Multilevel Hybrid Power Quality Conditioner for 25kV Railway Systems
of redundant states. The method again involves sensing of AVdc and subsequently
adding an appropriate (small) DC bias to the reference current to re-balance the
capacitor voltages (not shown in Figure 5.3). Both methods of capacitor voltage
balancing are well established and a more detailed discussion is beyond the scope of
this thesis.
5.6
SUMMARY
This chapter has extended the functionality and practicality of the basic traction power
quality conditioner presented in the previous chapter to also deal with harmonic
overvoltages. Also multilevel inverters are explored to further increase the capacity of
the conditioner. The result is a multilevel hybrid traction power quality conditioner
consisting of alternatively a cascaded or a reduced topology active power stage and a
low rating passive damping filter. The additional benefits of the multilevel hybrid TPQC are virtually eliminated harmonic overvoltage problems, much less switching
noise in the feeder voltage, and more capacity to support longer feeder lengths.
This chapter has also offered justifications and explanations of the hysteresis current
regulation techniques used. In addition, the offset band concept used in the three-level
hysteresis current regulator for two-level VSI has been extended to arrive at new and
improved current regulation techniques for controlling the reduced and cascaded fivelevel inverters. The proposed hysteresis technique for the reduced topology is much
more robust and significantly improves the capability of the existing technique.
Concerns about DC capacitor voltage balancing in the multilevel topology have also
been addressed and have been determined not to be an issue.
This chapter completes the theoretical development of knowledge in the thesis. The
remaining chapters present details of the simulation approach, details of the
experimental systems used to verify the simulation studies, and selected simulation
and experimental results to confirm the validity of the theoretical ideas developed.
132
CHAPTER 6: DESCRIPTION OF
SIMULATION SYSTEMS
The theoretical knowledge developed for this thesis has been presented in the last two
chapters. The next step is to confirm these theoretical predictions using digital
simulations on a personal computer and then finally through physical experiments in
the laboratory.
In engineering, digital computer simulation is the use of numerical methods to solve
complex sets of mathematical equations that represent physical systems. Computer
simulation studies have now become an integral part of the process of power system
and power electronic design and analysis, for very good reasons. Firstly, power
electronic switching processes and many power system phenomena are inherently
non-linear, often making an exact analytical solution almost impossible to achieve.
Secondly, simulations allow new ideas to be readily explored before committing to
complex hardware development, which is usually time-consuming, expensive and
carries the risk of physical damage in the event of unforeseen design flaws. Thirdly,
simulations allow detailed waveforms at critical points of the system to be easily
monitored and studied. It can be difficult, impractical, or at least corrupted by
measurement noise, to obtain similar measurements in a real system. This is
especially true for power electronic systems involving high frequency switching
processes. Lastly, physical experiments require component voltage and current ratings
to be suitably specified beforehand, which is often a difficult task without detailed
knowledge of voltage and current waveforms. Simulations, on the other hand, can be
carried out without regard to component sizing.
Simulation studies have played a major role in developing and fine-tuning the active
compensation strategies presented in this thesis. They have also assisted in the design
of the experimental control system, allowing second-order effects of non-linear
processes such as sampling, quantisation, roundoff and overflow to be investigated
and minimised as necessary. In particular, implementing filtering algorithms on a
133
CHAPTER 6:
Description of Simulation Systems
fixed-point DSP system requires more effort than just the straightforward application
of continuous to discrete transformation formulae. Because of limited dynamic range,
the coefficients in the difference equations need to be carefully scaled, to avoid
overflows in the worst situation whilst retaining maximum resolution. This involves
some trial and error, and therefore is best accomplished in simulations. As with every
simulation study, considerable thought has been given to the detail of modelling to
achieve a satisfactory compromise between simulation speed and its accuracy.
This chapter now describes the simulation approach taken and models developed for
this thesis.
6.1
DESCRIPTION OF THE PSCAD/EMTDC SIMULATION APPROACH
In general, the performance of power systems can be evaluated through either time
domain or frequency domain simulations. The frequency domain approach usually
requires less computation time [165], but its accuracy and convergence are
questionable on weak systems where significant interactions between the non-linear
loads and the power system are expected [9,166]. The time domain approach is
therefore the preferred choice for railway system studies. Although there are maiiy
well-established electrical circuit simulation programs designed for this purpose, the
PSCAD/EMTDC V3 package has been chosen for use in this thesis because of its
comprehensive library of power system and power device models and Ihe avails -lity
of a range of commonly used controller blocks.
EMTDC is a professional simulation tool for studying electromagnetic transient of
electrical systems. PSCAD is its interactive graphical user interface (GUI) allowing
construction, simulation, and analysis of electrical circuits in an entirely integrated
graphical environment.
Modelling in PSCAD generally involves assembling components from the large base
of built-in components found in the Master Library that is shipped with PSCAD.
Occasionally, custom designed components are needed and these can be included as
FORTRAN routines and easily interfaced to the rest of the system. After the system is
assembled, simulation is started within the interactive environment that allows model
134
CHAPTER 6:
Description of Simulation Systems
parameters to be modified during the course of the simulation. The immediate effects
of these parameters can be studied directly from the graphs or meters that display the
quantities of interest. The final results of the simulation can then be written to an
output file for further processing and analysis as required.
One shortcoming of PSCAD V3 is that it lacks many of the post-processing facilities
found in the previous version. Li particular, it lacks the Fourier analysis feature much
needed in this project to examine the harmonic spectra of voltage and current
waveforms. This was overcome by outputting the simulation data to a text file and
reading this data into MATLAB for analysis.
hi this thesis, simulation studies were carried out in two stages. The first stage was
performed assuming a continuous-time analog implementation for the T-PQC control
system, ignoring the sampling and finite word length effects found in a practical DSPcorjtrolled experimental system. This process helps facilitate the initial debugging
process and allows the theoretical understanding to be developed without having to
consider second-order complications.
After a good understanding of the basic theory was attained, the second-order effects
were introduced into the simulation to assess the impact of these non-idealities on the
overall system performance. This also allowed a good match to be achieved between
simulation and experimental results, as will be shown in Chapter 8.
All simulations were performed using an integration time step of 1 fis, unless
specified otherwise.
6.2
OVERVIEW OF SIMULATION SYSTEMS
The overall system schematic layout assumed in this thesis is shown in Figure 6.1. For
discussion purposes, it is broken down into 4 major sub-systems, namely the 25kV
power supply system, the locomotive loads, the power inverters for the Traction
Power Quality Conditioner (T-PQC), and the T-PQC control system. Modelling of
each of these sub-systems is described in turn in the following sections.
135
CHAPTER 6:
Description of Simulation Systems
50HzHV Supply
HV source Impedance
(Z=j1.0fl, referred to 25 W)
Traction Power Quality Conditioner
Feeding Transformer
(Z=j7.5n, referred to 25kV)
Power Inverter
30km Transmission Line
' Zj=_(0._169+j0.432) mm. C = 0.011 nF/km _
Coupling
Transformer
|_
LT
Train Load A
Train Load B
Train Load C
Train Load D
.:""":
Passive
J : v:;p_ Damping
•:: ^
Filter
Gating
Signals
Measured
Current i •
Hysteresis Current Regulator
Current
|Reference|
Measured Voltage
•I
DSP Controller
Measured
Voltage
Active Filter Contro! System
Figure 6.1: Overall system schematic layout assumed in this thesis
6.3
MODELLING OF 25KV POWER SUPPLY SYSTEM
The power supply system includes the source impedance as seen from the incoming
supply to the feeder substation, the substation feeding transformer impedance, and the
impedance of the 30km transmission line.
The HV supply is represented by an ideal voltage source behind an inductance. The
feeding transformer impedance consists mainly of its leakage inductance and resistive
losses. A standard transformer representation results in a frequency dependant
resistance in series with the leakage inductance, where the frequency variation of
resistance can be matched against data supplied by transformer manufacturers [20].
However, when constructing experimental models, fixed component values are
preferred as frequency dependant components are not as readily available. Experience
has shown that a parallel combination of constant resistance and inductance also gives
gocd accuracy [20], and thus it has been adopted both in the simulations and
experiments in this thesis.
136
CHAPTER 6:
Description of Simulation Systems
For an exact representation of a transmission line, a distributed parameter line model
is required. However, this is difficult to realise in the laboratory and so cascaded
nominal pi-sections were used instead. Cascading a sufficient number of pi-sections
produces a good approximation to a true distributed transmission line [167]. The
number of pi-sections to be used depends on the frequency range of interest and the
length of transmission line to be represented. The MATLAB help file for a Pi-Section
Line suggests using
N=
(6.1)
v=
(6.2)
where N is the number of pi-sections, fmax is the maximum freqeuncy of interest (in
Hz), 1 is the transmission line length (in km), v is the wave propagation speed (in
km/s), L and C are the line inductance (in H/km) and capacitance (in F/km)
respectively.
In this thesis, it is required to have accurate system representations at 50Hz
fundamental frequency for the voltage regulai on investigations, at low order
harmonics (150Hz, 250Hz, 350Hz) for form factor compensation, and also at the 1st
resonant frequency around 1.3kHz for harmonic overvoltage damping studies. Other
higher order parallel resonant frequencies are not excited in practice, as mentioned in
Section 2.5, and thus need not be modelled. Allowing for some margin, taking fmax =
3kHz and using the L and C values as".ume:i in this thesis, equation (6.1) gives N = 3.
This is in good agreement with the 'one pi section per 10km length' rule of thumb
proposed in [20,168] for harmonic overvoltage studies. Thus 3 pi-sections were used
to model the 30km transmission line in the experimental studies.
In order to maintain good agreement between simulation and experimental results, pisections have also been used in the simulation studies, even though a distributed line
model is readily available in PSCAD. Using 3 pi-sections provides 4 load points
(nodes A, B, C and D) for the locomotives, as shown in Figure 6.2, which shows the
137
KKi
CHAPTER 6:
Description of Simulation Systems
1000.0
R=0l
NodeA 1.69
0.0271
0.0138
NodeB 1.69
Ya.
0.0138
NodeC 1.69
A/VV
YiL
0.0138
'»•-*-'—
NodeD
yg.
p
bin
Figure 6.2: PSCAD model of 25kV power supply system
25kV power supply system model developed in PSCAD. The Zimbabwe railway
system [9] has been chosen for use in simulation and experimental studies in this
thesis as it has many features typical of 25kV railway systems.
6.4
MODELLING OF THYRISTOR LOCOMOTIVES
The locomotives considered in this thesis are the widely used dual-bogie type
thyristor locomotives. Each such locomotive typically has two pairs of seriesconnected bridges, as shown in Figure 2.3. It is assumed that both pairs operate
identically, and therefore they were modelled with an equivalent single pair [9,21].
The PSCAD model used for the 2.5MW locomotives (rated at 25kV) is shown in
Figure 6.3. The constant current source is normally set to 130A, representing the
maximum armature current. The transformer ratio is 1:0.5:0.5. All locomotive
parameters have been converted to a 25kV base. Not shown are the separate
circuitries used for setting the thyristor firing angles. Note also that the lower bridge
has been replaced with a diode bridge to represent the operating condition when the
lower thyristor bridge is in full conduction.
As identified in Section 2.2.1, m accelerating from rest to full speed, a thyristor
locomotive traverses 4 distinct operating regimes giving rise to 4 possible locomotive
models. Although Figure 6.3 shows a locomotive model for region 2 operation when
the locomotive is operating between half base-speed and base-speed, the firing angles
of the top bridge can also be adjusted to 0° to me -del region 3 operation. By further
reducing the current source value to below 130A, region 4 operation can be
represented. For simplicity, region 1 operation was not investigated although this
could be easily added in the future if required.
138
CHAPTER 6:
Description of Simulation Systems
oa,:
O74
Figure 6.3: PSCAD model of a 2.5MW locomotive
When two or more such locomotives are running together hauling a single train, they
were assumed to have identical firing angles. This assumption allows two locomotives
to be modelled as a single locomotive of double the real size, which is easily obtained
by halving the locomotive inductances, and doubling the capacitance and load current.
6.5
MODELLING OF POWER INVERTERS FOR T-PQC
Figure 6.4 shows the PSCAD model of the single-phase two-level VSI that was used
for the T-PQC. The coupling transformer, which was assumed to have a turns ratio of
1:1 for the simulation and experimental studies carried out in this thesis, was
modelled by an inductor that represents its leakage inductance plus any external
inductance needed to limit the current switching ripple.
Switching device forward voltage drops are usually a negligible fraction of system
voltages in medium to high power systems, and therefore have been neglected in the
PSCAD models. Small fictitious RC snubbers were included in the PSCAD model
mainly to damp spurious high frequency oscillations introduced by fixed-step
numerical integration. In reality RC snubbers are usually needed to limit device dv/dt
and also to reduce switching losses. However, no attempt has been made to mod'3l
realistic snubbers, as their effects are not relevant to the work presented in the thesis.
139
CHAPTER 6:
Description of Simulation Systems
j£harge
"T
.1..' A~
Gate3
-C3r
Gate4
Gate2
Figure 6.4: PSCAD model of single-phase two-level VSI
Other second order effects such as switch transition characteristics and dead time are
unimportant in power system studies, particularly since an inner current loop for the
inverter was employed, and hence have also not been modelled.
Figure 6.5 illustrates the PSCAD model of the single-phase reduced five-level VSI
that has also been used. Most of the comments regarding simulation of the two-level
VSI apply to this topology also.
6.6
MODELLING OF T-PQC CONTROL SYSTEM
The total T-PQC control system is composed of two physically distinct but
interconnected subsystems, namely the hysteresis current regulator and the DSP
controller, as indicated in Figure 6.1. These two subsystems will be described in the
following subsections.
GatelA
Gate2A
Vaf
/at
Gatel B
Gate2B
Figure 6.5: PSCAD model of single-phase reduced switch-count five-level VSI
140
CHAPTER 6:
6.6.1
Description of Simulation Systems
Hysteresis Current Regulator
The purpose of the hysteresis current regulator is to generate the gating signals for the
power inverter switches, based on the error between the reference current generated
by the DSP controller and the measured inverter current. The three-level hysteresis
enrreni regulator used for controlling the two-level VSI is illustrated in Figure 6.6,
which has been adapted from the MATLAB/Simulink model given in [162] to a
PSCAD implementation.
The hysteresis current regulator for the reduced five-level VSI consists of two
different module;;, one for the three-level PWM switching phase-leg and the other for
the two-level fundamental frequency switching phase-leg. They are illustrated in
el
Ga e3
Figure 6.6: PSCAD model of three-level hysteresis current regulator for controlling
conventional single-phase two-level VSI
141
I
CHAPTER 6:
Description of Simulation Systems
Three-level
phase leg
Two-level
phase leg
Figure 6.7: PSCAD model of hysteresis current regulator for reduced five-level VSI
Figure 6.7.
6.6.2
DSP Controller
Although much of the T-PQC control discussed in Chapter 4 was considered in the
continuous time analog domain, the experimental system used a DSP to implement
reactive power compensation, harmonic compensation and DC bus voltage regulation.
This means that sampling effects, ADC quantisation errors, filter coefficient
quantisation errors and roundoff errors are introduced into the control loop. However,
provided that the sampling frequency is sufficiently large and the numerical bit
representation is large enough, these errors can be kept to a minimum. To ensure a
close match between simulation and experimental results, the sampling and
quantisation processes were modelled exactly. The various compensation controllers
were implemented in simulation using difference equations as were done in the actual
DSP program.
One further complication is that the DSP used was a 16-bit fixed-point processor,
giving very narrow dynamic range for number representation. As a consequence
variables are prone to overflow, and therefore much care is needed to select the
142
CHAPTER 6:
Description of Simulation Systems
scaling factors. Simulating the DSP controller with these details allows any potential
overflows to be identified and resolved before testing on the actual experimental
system.
Whilst PSCAD is shipped with a good range of flexible analog controller blocks,
there is no direct provision for digital controller implementations using difference
equations or the equivalent z-domain transfer functions. Therefore 3 custom models
were created, as shown in Figure 6.8, to model respectively the DC bus PI controller,
the harmonic controller and the reactive power controller. FORTRAN codes were
written to reflect as closely as possible the C codes used in the actual DSP program.
Integer variables were used in the FORTRAN codes where appropriate to account for
roundoff errors, quantisation errors and potential overflows. Figure 6.9 shows a
] Voltage measured in kV
need to convert to V
: Analog anti-aliasing filter
fc = 3316Hz
Vd
MB Analog input
and ADC gain
+/• 10V limits of
actual DAC
->
1000
ref
positive value
corresponds to
i supplying leading
i reactive current
Figure 6.8: PSCAD custom models of the DSP controller
143
CHAPTER 6:
Description of Simulation Systems
skeleton of the custom routines as well as illustrating how the custom routines
interface with the rest of the network. Note that the PSCAD simulation time step used
was lus, therefore the controller states are only calculated every 100 simulation time
steps to reflect the 10kHz sampling frequency used in the actual DSP.
Attention was ulso paid to arranging important building blocks, such as the antiliasing filter and the ADC gain block, in the logical order that they are found in the
actual experimental hardware implementation. Such a close linkage between the
simulation and experimental systems has greatly assisted in debugging and finetuning the physically implemented control system. Further details can be found in
Chapter 7 where the details of the DSP implementation are described.
6.7
OTHER CUSTOM MODELS
Two of the most importani cr1 :aa used in this thesis to measure the performance of
the proposed compensator are the system rms voltage and form factor values. For rms
measurements, PSCAD has built-in single-phase and three-phase rms meter blocks, as
shown in Figure 6.10. In the three-phase rms meter, a three-phase diode rectifier
output voltage is smoothed by a first order lag network and multiplied by a suitable
scaling factor to obtain the rms value. In the single-phase rms meter, the input
quantity is squared, smoothed by a first order lag network and then, the square root
taken. For the three-phase meter, the rectified voltage pulsates : t six times the
fundamental frequency; for the single-phase meter, the squared quantity pulsates at
two times the fundamental frequency. In both cases, the smoothing time constant must
be chosen that is large enough to obtain an accurate DC output reading with minimal
npple. This means that this simple form of rms measurement is suitable neither for
dynamic system monitoring nor for real-time control (as required by the reactive
power compensation loop), as a large time constant is often required to keep the ripple
down. This is particularly unacceptable for single-phase systems, since the dominant
ripple is at twice the fundamental frequency, requiring a three times larger time
constant compared to a three-phase measurement.
144
CHAPTER 6:
Description of Simulation Systems
To provide dynamic monitoring of rms and form factor, a custom model has been
created in PSCAD, as shown in Figure 6.11, based on a running window algorithm
written in FORTRAN. A listing of the code can be found in Appendix C. In the
algorithm, the incoming signal is sampled N times per fundamental cycle, and at each
Initialisation
PSCAD Main Time
Loop
Time == Time + At
Solve for History
Terms
I
fcustom model r outine:
T
Harmonic Controiler
^»^.
No
L
.Custom model routine:
|
.Custom model routine:
' Reactive Power Controller
1
1
<^ls Count = 1007^>
JYes
Count = 0
1
i
Copy state values
from STORI global
array into local
variables
L.
1
1
1
Network Solution
1
Execute difference
equations and update
state values
i
Interpolation
1
Save state values onto
STORI global array for
use in next time step
DSOUT
1
i
RUNTIME
Communication
t
Controller output gets
vslue from STORI
array
^
1
<
t
Write Output Files
t
1
Count = Count + 1
X
L
< J s Run Finished?N
No
1 Yes
(
END
J
Figure 6.9: PSCAD flow chart showing custom model routines
145
CHAPTER 6:
Description of Simulation Systems
sample time the rms and average values are computed over a data window of one
fundamental cycle according to (6.3) and (6.4). The data window is moved sample by
sample as the simulation progresses.
(6.3)
V
(6.4)
=—
To reduce the computing burden when calculating the rms value, the squares of the
signal samples are stored in an array of size N, to avoid squaring all N samples at each
sample time. Furthermore, rather than summing all N squared samples at each sample
time, a sum of squares variable is maintained and updated according to
(6.5)
where Sn = the latest sum of squares for this sample time,
Sn-i = sum of squares from previous sample time,
vn = latest sample of incoming signal,
vn_N = oldest signal sample within the fundamental cycle.
RMS
V
3 Phase
RMS
(a)
(b)
Figure 6.10: PSCAD built-in RMS meter blocks, (a) Single-phase (b) Three-phase
rms
RMS and
avg
Average
Calculator ff
Figure 6.11: PSCAD custom model for rms, average, and form factor measurements
146
CHAPTER 6:
Description of Simulation Systems
The algorithm described above is also used for real-time rms calculation in the
reactive power compensation loop, both in the PSCAD simulations as well as in the
experimental DSP controller.
A similar algorithm is used for average value calculation, where the absolute values of
signal samples are stored for one fundamental cycle. The sum of absolute values Sn is
then updated according to
Sn=Sn.l+\v\-\vn_N
(6.6)
at each sample time.
Using these results, the form factor is calculated as the ratio of rms to average values
as given in (2.5).
6.8
SUMMARY
Simulation is an indispensable part of any power system and power electronic
investigation as it enables the complex behaviour of non-linear system interactions t
be evaluated accurately, safely and cheaply. In any simulation, however, there is
always a trade-off between simulation execution time and accuracy, and in this thesis
the PSCAD models have been developed to obtain a good compromise between the
two.
Initially, simulations were carried out using continuous time analog control systems to
allow a fundamental understanding of the theoretical knowledge to be gained without
being complicated by second order details. Then the actual DSP control system was
modelled down to the difference equation level to reflect practical second order issues
such as sampling and finite word length effects. This modelling approach has proven
to be fruitful as it not only allowed the experimental system to be fine-tuned with
ease, but also resulted in a close match between the simulation and experimental
results presented in Chapter 8.
147
CHAPTER 6:
Description of Simulation Systems
The next chapter proceeds to describe tTie experimental system developed.
Presentation of the simulation results is postponed until Chapter 8, where simulation
and experimental results are presented and compared.
148
CHAPTER 7: DESCRIPTION OF
EXPERIMENTAL SYSTEMS
•3*'^r''J*'•&'•*"'&'iTJF*F'jrtf'&'jt
AT'Jf &*~ jrs#j?JF. jp JF'^4?w'jr'jt4P&JF.£?•£''•&•£!'.JTwjf.',w&'&'^:jr.^JT&^&
JTjr. JFAFJT-*'JF-JT^'JF'JFJF'J" jr.jF-^^.Jt JT jf- & Mjf.irM
The major goal of this thesis is to study the performance of a 25kV railway system
under active compensation. The linear analysis presented in Chapters 4 and 5 shows
promising results, and these have been validated by the simulation studies described
in Chapter 6. However, whilst computer simulations are extremely helpful in
determining the performance of complex non-linear system interactions, it is quite
difficult to ascertain that all the relevant features of the full scale system have been
properly included in the simulation models. It is also difficult to know if important
practical features may have been overlooked or over-simplified. This is of great
significance because practical effects can limit the performance of a real converter
system to well below theoretical expectations. A convincing conclusion can only be
reached after physical experiments have been carried out to confirm the results
obtained from theoretical developments and computer simulations.
As it is impossible to build a real system solely for this purpose and impractical to
perform tests on an existing system, a scaled physical model of a 25kV railway
system and the Traction Power Quality Conditioner (T-PQC) have been built. This
chapter describes the experimental system that was developed to provide the
experimental confirmation.
7.1
OVERVIEW OF EXPERIMENTAL SYSTEMS
The arrangement of the 25kV railway system and the T-PQC considered in this thesis
is shown in Figure 6.1. The overall schematic of the experimental system used to
model the real system is shown in Figure 7.1. The experimental system consists of
scale models of the 25kV power supply system, the thyristor locomotives, the power
inverters for the T-PQC and the T-PQC control system. The first two models are
briefly explained in the next two sections respectively, whilst the bulk of this chapter
is devoted to the description of the experimental T-PQC implementation.
149
Description of Experimental Systems
^Traction Power
QualityCondiuone~(CascadedVsi)\
H-Bridqe
Traction Power Quality Conditioner (two-level VSI)
Hysteresis Current Regulator 1
Host PC
Figure 7.1: Schematic of experimental system with TPQC implemented using either a two-level VSI or a cascaded five-level VSI
150
CHAPTER 7:
7.2
Description of Experimental Systems
MODELLING OF 25KV POWER SUPPLY SYSTEM
A scale model of the 25kV power supply system was assembled for the experimental
system. One of the first design decisions in developing the experimental system was
to choose the appropriate voltage, current and impedance scaling factors. Any two of
these three factors can be chosen independently, while the third is constrained by
Ohm's Law. It was decided to operate the experimental system at a system voltage of
lSOVmrs. This was considered high enough that the inverter and rectifier
semiconductor forward voltage drops were below 0.5%, and at the same time low
enough that the T-PQC inverter could be operated with a DC bus voltage comfortably
below its absolute maximum rating of 400V. On the other hand, the impedance
scaling factor is basically dictated by the values of inductors available in the
laboratory. The final scaling factors adopted by the experimental system are given in
Table 7.1. Note that the current scaling factor is determined by the voltage and
impedance scaling factors through Ohm's Law.
A 50Hz 0-260V variac was used to supply power to the experimental system.
Isolation of the experimental system from the mains for safety purposes was achieved
through a large isolation transformer, which has negligible series impedance
compared to the rest of the system. As shown in Figure 7.1, the 30km overhead
transmission line was represented in the laboratory by 3 pi-sections, each representing
10km of line. Care was taken in using air-core and/or over-rated inductors where
available to represent the substation transformer and overhead line inductances. This
was to make sure the resistive losses at the resonant frequency were kept to a
minimum so that overvoltages were not excessively damped.
The actual values of the components used in the experimental system are given in
Real: Experimental
Voltage (V)
166.67: 1
Current (A)
281.4:1
Impedance (Q)
0.592 : 1
Table 7.1: Scaling factors adopted for the experimental system
151
CHAPTER 7:
Description of Experimental Systems
Real
System
Experimental
System
System voltage Vs
25kV
150V
Line frequency
50Hz
50Hz
27.1mH
46mH
Substation transformer equivalent resistance Rs
1000Q
1690Q
Pi-section inductance L
13.8mH
23.3mH
Pi-section resistance R
1.69Q.
2.86Q
Pi-section capacitance C
0.1 luF
0.068uF
T-PQC coupling inductance L c
51.2mH
86.5mH
Passive filter capacitance Cp
0.84uF
0.5jiF
Passive filter inductance Lp
385mH
650mH
Passive filter resistance Rp
344Q
581Q
Substation transformer inductance L s
Table 7.2: Real and experimental system parameters
Table 7.2, along with the real unsealed values for comparison. These values are based
on the Zimbabwe railway system [9], as it has all features typical of 25kV railway
systems discussed in Chapter 2.
7.3
MODELLING OF THYRISTOR LOCOMOTIVES
As discussed in Subsection 2.2.1, four distinct operation regimes can be identified for
a typical thyristor locomotive, requiring three different locomotive rectifier topologies
(regime 4 shares the same diode rectifier topology as regime 3 but with a reduced DC
current). Since the experimental work is intended simply to confirm the results of the
simulation studies, it is not necessary to model all three different locomotive rectifier
Figure 7.2: Schematic of experimental locomotive load
152
CHAPTER 7:
Description of Experimental Systems
topologies. Indeed, for the experimental system only simple diode rectifier models
were used, which correspond to the locomotives operating at maximum output power.
The schematic of the locomotive loads used in the experiments is given in Figure 7.2.
Rather than implementing a constant DC current source, which was not readily
available, a variable DC resistor RdC was used and adjusted to give the specified
locomotive DC current. This approach has the downside that each time the system
condition changes (eg. after applying compensation), R<jC needs to be adjusted to give
the same DC current. However, in practice this did not cause any particular
difficulties. The scaled values of the 2.5MW, 5MW and 10MW locomotive
parameters used in the experimental system are given in Table 7.3, Table 7.4 and
Table 7.5 respectively, along with the real unsealed values for comparison. Note that
as explained in Section 6.4, a basic 2.5MW locomotive has been assumed, and when
Real
System
Experimental
System
Main transformer inductance Lac
92mH
156mH
DC load inductance Ldc
0.74H
1.25H
DC load current IdC
130A
0.462A
Table 7.3: Real and experimental 2.5MW locomotive parameters
Real
System
Experimental
System
Main transformer inductance Lac
46mH
78mH
DC load inductance Ldc
0.37H
0.64H
DC load current ldc
260A
0.925A
Table 7.4: Real and experimental 5MW locomotive parameters
Real
System
Experimental
System
Main transformer inductance Lac
23mH
39mH
DC load inductance Ldc
0.185H
0.313H
520A
1.85A
DC load current ldc
Table 7.5: Real and experimental 10MW locomotive parameters
153
CHAPTER 7:
Description of Experimental Systems
two or more such locomotives are hauling a single train, the locomotive parameters
are simply scaled proportionally.
7.4
EXPERIMENTAL POWER INVERTERS FOR
7.4.1
Single-Phase Two-Level VSI
T-PQC
The experimental two-level VSI was implemented with the CS-IIB Integrated Inverter
Board [169], shown in Figure 7.3, which is developed by the Power Electronics
Group of Monash University. The CS-IIB is a flexible, low voltage, commercial
quality 4-phase-leg integrated inverter system that has been designed for applications
requiring a single simple inverter platform. The board includes an on-card IGBT
based power stage and sufficient digital and analog conditioned signals to enable it to
operate, with plug-in CS-MiniDSP processor card, cs a standalone voltage source
inverter without additional circuitry.
The power stage of the CS-IIB is capable of operation up to 15A at up to a 400V DC
bus. The power stage has been designed with flexibility in mind, and can be readily
DC Bus Capacitors
Heat Sink &
IGBT Inverter
(underneath)
Switched Mode
Power Supply
MlniDSP
Card
TMS320F240
DSP Chip
Analog
Measurement
Inputs
Figure 7.3: Digitally rendered image of CS-IEB Integrated Inverter Board
154
CHAPTER 7:
Description of Experimental Systems
configured into a variety of common inverter topologies ranging from one or two
independent single-phase H-bridges to a four phase-leg inverter. For the purposes of
this thesis, it was configured as a single-phase H-bridge (two-level VSI), as shown in
Figure 7.4. Each of the phase-legs incorporates a high frequency 0.1 fiF capacitor
across the DC bus connection to the IGBT, to minimise the voltage spikes generated
by parasitic inductance in the DC bus wiring. This is a common practice for any
power converters of reasonable ratings.
The associated DC bus is connected to an on-board single-phase diode bridge
rectifier, which can be used to energise the DC bus from an incoming single-phase
AC supply for applications where the inverter is required to supply real power. In
STATCOM and active power filter applications, the inverter only supplies reactive
and harmonic power, and the DC bus voltage is actively regulated by the controller
through the inverter. The diode rectifier inputs were therefore left open when the CSIIB was operating as a two-level VSI.
7.4.2
Single-Phase Cascaded Five-Level VSI
The cascaded five-level topolog) was adopted for the experimental work in this
thesis. Whilst the reduced switch-count topology was also proposed in Chapter 5, all
five-level inverter topologies have a similar harmonic performance and therefore it
\_CS-IIBH-Bridgo_
A +
«,___t A — - -
Hysteresis Current Regulator
Figure 7.4: Structure of experimental single-phase H-bridge (two-level VSI)
155
CHAPTER 7:
Description of Experimental Systems
was considered sufficiently general to provide experimental verification with only a
cascaded topology.
Although the CS-HB comes with four IGBT phase-legs and can be configured into
two independent single-phase H-bridges with separate DC buses, it is not designed
with cascaded multilevel operation in mind, and this mode of operation could
potentially breach the voltage isolation design limits between the DC buses. To be on
the conservative side, it was decided to operate a single-phase H-bridge from the CSIIB in cascade with a suitably connected three-phase laboratory inverter to obtain a
single-phase cascaded five-level inverter, as shown in Figure 7.5. The three-phase
laboratory inverter is a single unit which contains a three-phase diode rectifier
module, a three-phase two-level VSI, a DC bus capacitor bank and associated wiring.
Aux.
Isolation
Variac Transformer!
CS-IIB H-Bndge
' A A
fi
'
Hysteresis Current Regulator 1
Isolation
Transformer!
i Laboratory Inverter • 1 - r '
• ~i T '
Hysteresis Current Regulator 2
Figure 7.5: Structure of experimental cascaded five-level VSI
156
CHAPTER 7:
Description of Experimental Systems
The DC bus control loop was verified experimentally only with the two-level VSI.
DC bur regulation was not experimentally implemented for the cascaded inverter,
since it would require additional effort in dealing with capacitor balancing and would
not offer any additional insights into the T-PQC compensation performance. Instead,
the two DC buses were fed by their respective input diode rectifiers through an
isolation transformer fed from an auxiliary variac, which maintained the DC bus
voltages at the desired value. As a precautionary measure, a 500Q rheostat (not
shown) was also connected across each of the DC buses to help clamp the DC bus
voltage in the unlikely event of excessive real power flow back into the DC buses.
The presence of the rheostats also allowed the two capacitor voltages to be balanced
manually if large deviations between them occurred.
7.5
EXPERIMENTAL T-PQC CONTROL SYSTEM
The experimental T-PQC control system was implemented with a combination of
analog and digital circuitry. The general arrangement of the control system has been
shown in Figure 7.1. Effectively the signal processing of the outer control loops,
system voltage synchronisation, data logging, fault monitoring and other house
keeping tasks are handled digitally by the DSP controller. The DSP controller
generates a reference current digital output, which is passed to an external 12-bit
digital-to-analog converter (DAC) [170]. The hysteresis current regulator, which itself
consists of a mixture of analog and digital circuitry, utilises the analog reference
current together with the measured inverter current signal from a Hall effect current
sensor (LEM) to produce gating signals to be fed to the gate drivers of the inverters.
Further details of the control system hardwai.- are presented in the following
subsections, whilst the DSP controller software is described in Section 7.6.
7.5.1
Hysteresis Current Regulator
The hysteresis current regulator is an experimental system developed by Bode et al.
[162] to generate three-level switching signals for a two-level VSI (conventional Hbridge) using the operating principles detailed in Subsection 5.4.1. A functional
diagram of the regulator board is shown in Figure 7.6, which shows only the features
used in this thesis. The experimental system works as follows.
157
CHAPTER 7:
Reference
Current
Measured
Current
Description of Experimental Systems
Error Band
Offset
Error Band
Width
Finite State
Machine to
select
appropriate
switching state
Phaseleg 1
IXYS630
Dead Time
Generator
Phaseleg 2
Hysteresis Current Regulator Board
Figure 7.6: Functional diagram of three-level hysteresis current regulator board
The reference current, after adding an appropriate offset compensation factor, is
subtracted from the measured current signal derived from the LEM transducer to give
the current error. The current error is then sent to two hysteresis comparators which
detect when it exceeds the upper and lower limits of the two bands Bl and B2 in
Figure 5.5. Separate trimpots are provided for tuning the current error band offset size
and band width. A finite state machine, based on logic gates and flip-flops, then uses
the output signals of the comparators to select the next inverter switching state. The
primary goal of the state machine is to ensure equal use of the two OV output
switching states of the H-bridge, thereby distributing the switching losses equally
among the four switches. The state machine also remembers the polarity of the most
recent inverter active output, which is used to determine the polarity of the
compensation factor added to the reference current. Finally, the desired switching
states of the two phase-legs are passed to an IXDP630 dead time generator, which
generates four gating signals, one for each IGBT of the H-bridge, allowing for a
suitable blanking or dead time between the switching transitions of complementary
switches in the same phase-leg. A dead time of approximately 2.1jus was used. The
gating signals generated are delivered to the respective gate drivers of the H-bridge.
To control the cascaded five-level inverter, two identical hysteresis current regulator
boards were used, one for each H-bridge. As indicated in Figure 7.1, the two current
regulator boards use the same analog reference current signal from the DAC. Also,
the two boards are fed with the same measured current from the LEM transducer. As
noted in Subsection 5.4.3, for the cascaded five-level inverter consisting of two
158
CHAPTER 7:
Description of Experimental Systems
identical H-bridges, the digital outputs from the two regulators should be further
processed to equalise switching stresses among the eight switches. Failure to do so
results in one H-bridge switching at the fundamental frequency and the other
switching at twice the rate of an equally shared cascaded inverter. However, the total
inverter outputs remain identical whether the switching losses are equalised or not.
Since the objective of the experimental work is to verify the proposed hysteresis
current regulation technique and to examine the harmonic performance of the fivelevel inverter on the traction system, switch optimisation was deemed unnecessary.
This allowed operation of the cascaded inverter to be quickly and accurately validated
using existing three-level hysteresis regulator boards without modification.
7.5.2 DSP Controller
The DSP controller used in the experimental system is the CS-MiniDSP controller
card and CS-IIB Integrated Inverter Board combination. The CS-MiniDSP [171], also
designed and manufactured by the Power Electronics Group at Monash University, is
a low cost, high performance DSP based controller, intended specifically for
applications where a discrete BUS based system would be too expensive, and where
time/money/resource constraints make a custom design impracticable.
The CS-MiniDSP card is designed around a Texas Instruments TMS320F240 DSP
chip, which has been specifically optimised for use in digital motor/motion control
applications, running from a 20MHz clock oscillator. The card includes on-card
memory, an 8-bit I/O MINI BUS interface (INTEL iSBX compatible), analog inputs,
PWM outputs, digital I/O, communications and ancillary support circuitry. The CSMiniDSP controller card plugs straight into the CS-IIB board, as shown in Figure 7.3,
which provides additional facilities essential to the operation of an inverter.
The default arrangement on the CS-MiniDSP/CS-IIB platform is that each of the 8
gate driver circuits, corresponding to the 8 IGBTs in the power stage of the CS-IIB, is
directly driven by a PWM output of the DSP chip. This assumes the PWM modulator
is implemented digitally using the DSP. In this thesis, however, the gate drivers on the
CS-IIB were driven by external inputs from the hysteresis current regulator boards
described in the previous subsection. To avoid signal contentions, the 74HC245
159
CHAPTER 7:
Description of Experimental Systems
buffer chip between the DSP PWM outputs and the gate drivers was removed from
the CS-MiniDSP card.
The remainder of this subsection describes the hardware features of the CSMiniDSP/CS-HB platform that are relevant lo the experimental work carried out in
this thesis. Figure 7.7 shows the simplified functional diagram of the DSP controller,
highlighting only the functions actually used.
Analog to Digital Converter (ADC)
The TMS320F240 DSP has two integrated 10-bit ADCs, each with a built-in sampleand-hold circuit [172]. The DSP provides 16 separate analog input channels, grouped
into two sets of 8 channels, with each set handled by an eight-to-one analog
multiplexer and converted by a one of the two ADC units. Only two analog quantities
can be sampled and converted concurrently at any one time. The maximum total
conversion time for each ADC unit is 6.6jns.
With appropriate signal-conditioning stages, the CS-IIB configures the 16 analog
Digital I/O (Bank 1)
CS-MiniDSP/CS-IIB Controller
DIP _
Switches
LEDs-*
I Buffer | | Latch 1
DATA
A
V
iiiiiiiiiiiimiiii
128k RAM
64k EPROM
16
TMS320F240
DSP Chip
t
ADDR
T
iiiiiiiiiiiiiniiii
ikV ISOLATION
a
a.
D)
A
V
Port
-—|
Analog ADC (6x Vac, 6x lac, 2x Vdc, 2x pots)
Host
/
S/H, Gain
\ & Offset
\ Buffers
RS-232 S
A
/
Tl
O
—
|-
Figure 7.7: Simplified functional diagram of CS-MiniDSP/CS-IIB board
160
CHAPTER 7:
Description of Experimental Systems
input channels into the following:
1) 6 AC current inputs compatible with CT's and LEM's. These are not used in
this thesis.
2) 6 AC differential voltage inputs with a default maximum of +450V peak. Two
of these voltage inputs have special zero-crossing circuitries that generate a
square wave signal synchronised to the zero-crossings of the input waveform.
Four of the inputs were used to measure vA, VB, VC and VQ (see Figure 7.1) for
calculating the voltage rms values and form factors along the line, and for use
in the T-PQC control loop (vD only). To improve digital resolution, the
maximum voltage was dropped (by modifying on-board resistors) to ±346V
peak, which left a comfortable margin for the 150Vrms experimental system
even allowing for a 50% overvoltage.
3) 2 DC differential voltage inputs with a default range of 0-510Vdc. One of
these inputs was used to measure the DC capacitor voltage for DC bus voltage
regulation.
4) 2 analog potentiometer inputs between -10V to +10V. One of these was used
to set the reference DC bus voltage level.
In fully-digital-controlled closed-loop PWM inverter systems (eg. PCR or linear
CRPWM), the sampling of the inverter currents and system voltages/backemfs is
always synchronised to the start of the PWM half-carrier interval. This automatically
ensures that the measured quantities coincide with the low frequency target average
and do not contain any switching ripples [107]. It is with this assumption that the AC
voltage and current analog signal conditioning stages on the CS-IIB were designed
with cut-off frequencies in excess of 150kHz, well above the switching frequency
range of inverters of this size. For the T-PQC, however, a hysteresis current loop is
proposed, which always switches asychronously based on the switching rules
described in Section 5.4. This means that the measured voltage signals (vA, vB, v c , vD)
will always contain switching ripple, which must be adequately filtered before they
161
CHAPTER 7:
Description of Experimental Systems
are sampled into the DSP to avoid anti-aliasing effects. For the experimental work,
the voltages were sampled at 10kHz. The relevant CS-ID3 signal conditioning stages
were therefore modified to act as a first order anti-aliasing filter with a cut-off
frequency of about 3.3kHz.
Digital I/O
The CS-IIB board provides two banks of general-purpose digital I/Os, with 16 bits for
each bank. As shown in Figure 7.7, 8 bits of Bank 1 accept digital inputs from DIP
switches, and the remaining 8 bits drive LEDs indicators. In the experimental work,
the DIP switches were used to indicate the start-up configuration, whilst the LEDs
were used to indicate the status of various faults. As these features were employed
only for convenience especially during the debugging phase, and are in no way
critical to the operation of the controller, they will not be discussed further.
Apart from providing general-purpose digital I/O facilities, the 16-bit Bank 2 has a
few pins which have extra functionality. Two of these pins are used by the zerocrossing circuitry to send digital transitions to the DSP chip's timer capture inputs
whenever a zero-crossing occurs in the input waveforms. The on-chip Capture Units
then record the time of the transitions. This feature was used to detect zero-crossings
in vD for synchronisation to the system voltage.
MINI BUS I/O Interface
The CS-MiniDSP/CS-HB platform supports additional I/O peripherals through the
MINI BUS, which is an 8-bit I/O data bus interface. In the experimental system, the
MINI BUS was used to interface with an auxiliary analog I/O card [170], which
provides up to 4 channels of digital to analog conversion (DAC). The DAC was
required to convert the reference current output from the DSP controller into an
analog signal for use by the hysteresis current regulators.
RS-232 Serial Communications
The CS-IIB offers a standard RS-232 serial connection for interfacing with a standard
PC serial port, with lkV of voltage isolation. This was used to download programs
162
CHAPTER 7:
Description of Experimental Systems
into the DSP's memory for execution, and for providing overall control over the DSP
controller's operation. It was also used to transmit real-time data stored in the DSP's
RAM back to the host PC, both for on-line monitoring purposes and for subsequent
analysis.
7.6
DSP SOFTWARE OVERVIEW
The primary function of the DSP controller is to generate an appropriate reference
current signal for the hysteresis current regulator, based on the feedback controls
described in Chapters 4 and 5. The hardware elements that enable the generation of
this signal have been discussed in the Subsection 7.5.2. This section discusses the
general structure of the DSP software that was written.
The DSP program was written in C, and was adapted from the code for a three-phase
predictive current regulated (PCR) PWM VSI system developed by the Power
Electronics Group at Monash University, for a different hardware platform that also
used the same TMS320F240 DSP chip. The DSP program is organised into two parts,
the background code and the time-critical interrupt (foreground) code, that are
discussed in turn in the next two subsections. A complete listing of the program code
can be found in Appendix D.
7.6.1
Interrupt Code
A timer in the Event Manager Module of the DSP chip is set-up to trigger a high
priority interrupt exactly once every IOOJIS. Every time the interrupt is triggered, the
DSP diverts from the current background task and executes an interrupt service
routine (ISR). All the time-critical tasks are performed in this main ISR. A flow chart
illustrating the major tasks performed within the main interrupt code is shown in
Figure 7.8.
As the main ISR is called every I00(is, it is crucial that the code in the ISR must not
take longer then 100|iS to execute, otherwise the timing of the subsequent interrupt
calls are disturbed and unexpected results can occur. Furthermore, sufficient CPU
time must be allowed for processing background tasks as well as other lower priority
163
CHAPTER 7:
Description of Experimental Systems
interrupts, thus in practice the main ISR should be restricted to an execution time
window of no more than 60-70|is.
Analog to Digital Conversion
The 6 analog quantities (see Section 7.5.2) are sampled and updated once every main
interrupt call, ie. at 10kHz. They are arranged into 3 pairs of two for conversion, since
only two ADC units are available. The conversion process takes 6.6|xs and once
initiated does not require any CPU intervention, but the CPU does need to know when
the conversions are complete so that they can be read. Two common methods of
detecting an end of analog conversion are to have a separate interrupt to indicate the
end of conversion, or to have the CPU poll an ADC conversion flag. Neither method
f
Start ISR
J
Read Vdd and Vac2
f
Initiate Sampling and
Conversion of Vdd and Vac2
Reactive Power
Compensation:
Compute iq*
>f
Zero Crossing
Processing:
Compute coft
Read Vac3 and Vac4
r
Read Vad and Pot2
>r
Initiate Sampling and
Conversion of Vac3 and Vac4
r
Output Reference
Current i c ' to DAC
DC Bus Regulation:
Compute id*
Enable Sampling and
Conversion of vaci and Pol2
f
Harmonic
Compensation:
Compute !„,,'
/Return to ~N
( Background )
V
Code
y
8
Figure 7.8: Flow chart illustrating the structure of the main interrupt service routine
164
CHAPTER 7:
Description of Experimental Systems
was implemented in the experimental system as the interrupt method would incur
significant interrupt overhead and the polling method is even worse, forcing the CPU
to wait for 3x 6.6jas whilst doing nothing. Instead, to minimise the effect of analog
conversion time delay, the start of a pair of ADC conversions and the reading of the
conversion results are separated by code sections that are known always to take more
than 6.6(is to execute. Thus no CPU time is wasted to service extra interrupts or to
determine whether the conversions are complete.
As shown in Figure 7.8, the conversion of Vac 1 and Pot2 are enabled at the end of the
interrupt, but conversion is not started until the beginning of the next interrupt call. In
the following interrupt call, the conversion results are read after the zero crossing
code, allowing more than enough time for complete conversion. Another feature of
the DSP ADC units that was used is the ability of the conversion initialisation to be
shadowed [172], At the beginning of the interrupt, conversions of Vdcl and Vac2 are
initiated (and shadowed), but do not start since the ADC units are still busy dealing
with Vacl and Pot2. The conversions of Vdcl and Vac2 start automatically and
immediately after conversions of Vacl and Pot2 have finished, which occur at some
time during the zero crossing processing. The conversion results for Vdcl and Vac2
are read after the DC bus regulation and harmonic compensation block, by which time
their ADC conversions are expected to have finished.
Zero Crossing Processing
The purpose of the zero crossing processing is to calculate and maintain a phase
counter synchronised to the supply voltage. By using the phase counter as an index to
a sine look-up table, a sinewave in phase and in quadrature with the supply voltage
can be generated to demand real and reactive currents respectively.
Initially, the zero crossing processing routine samples a series of zero-crossings to
estimate the fundamental frequency. The algorithm then calculates the phase
difference between the internal phase reference and the supply voltage phase (from
the zero-crossing signal). If this phase error is small, then the internal phase error
steps toward the external phase reference in one step. If the phase error is large, then
the internal phase error steps toward the external phase reference over multiple
165
CHAPTER 7:
Description of Experimental Systems
fundamental cycles. The frequency (or rate of change of phase) is slowly adjusted to
correct for consistent phase errors. Furthermore, if no zero-crossing signal is detected
within 50ms, a loss of synchronisation is declared. The calculation of this
synchronising process is split across several main interrupt calls to reduce the worst
case interrupt processing time.
As the traction system supply voltage VD is potentially noisy, the analog zero-crossing
circuitry on the CS-HB board incorporates a first order filtering stage to provide
heavy attenuation of harmonic components in case they affect the accuracy of the
synchronising algorithm. The fixed delay of the first order filter at 50Hz is easily
compensated within the zero crossing processing code with a constant phase offset.
Harmonic Compensation
The T-PQC controllers in Chapters 4 and 5 are presented as continuous time analog
transfer functions. These controller transfer functions need to be discretised for DSP
implementation. Many methods of producing a discrete equivalent transfer function
are possible [173,174]. For harmonic compensation purposes, the resonant filter
network
2cocs
2cocs
s2 + 2CDCS + (3o>s)2
2acs
S2
+ 2cocs + {5cos )7
(7.1)
is used to extract the third, fifth and seventh harmonic components. In the
experimental system, the prewarped bilinear (Tusdn) transform has been used to
obtain the discrete equivalent transfer function of (7.1). The bilinear transform is
given by
O),
z-\
(7.2)
tan(<a,772) z
where ©i = prewarped frequency
166
CHAPTER 7:
Description of Experimental Systems
T = sampling period.
Equation (7.2) is substituted into (7.1) to obtain the z-domain (discrete) transfer
function, from which the difference equati' >ns for DSP implementation can be easily
derived. Note that when expanded, (7.1) represents a sixth order transfer function. In
analog implementations or with floating-point data representations, whether (7.1) is
calculated as a single sixth order network or as a summation of three second order
networks has no effect on the output value. With fixed-point digital representations,
the common practice is to realise a high-order filter as a cascade or parallel
combination of first or second order stages to minimise the effects of coefficient
quantisation errors and round-off errors. Equation (7.1) is already conveniently
expressed in the parallel form, hence it is implemented as such.
Thus for the third harmonic resonant branch, the first term in (7.1) discretises to
0.00099752417 - 0.00099752417z-2
l-1.9891377z"' + 0.99800495z - 2
(7.3)
with coc = 10 rad/s, ©s = 27t(50) rad/s and where z is the forward shift operator. The
corresponding difference equation is easily obtained to be
y(n) = 0.0009975241 l[x{n) - x(n - 2)]
+ 1.9891377>>(H -1) - 0.99800495y(« - 2)
(7.4)
For fixed-point implementation, the coefficients in (7.4) have to be normalised by
multiplying them by the maximum integer value of the chosen word length. The
choice of word length is dictated by the size of coefficient quantisation errors that can
be tolerated. Large coefficient quantisation errors can change thr frequency
characteristics of a filter, and even render it open-loop unstable. Furthermore, the
more selective the filter is, the more significant is the effect of coefficient
quantisation, and thus a larger word length is required for representation.
id
For the 16-bit DSP used, a chosen word length of 16 bits results in the fastest
execution, since (7.4) would then involve three 16-bit x 16-bit multiplications and
167
CHAPTER 7:
Description of Experimental Systems
each of these can be done by the DSP's 16-bit x 16-bit hardware multiplier in a single
machine cycle. The C compiler also supports a 32-bit x 32-bit multiplication, which
takes about five times longer to execute. However, the 32-bit multiplication gives
meaningful results only when the product can be represented with 32 bits.
It was found that 16-bit representation resulted in significant performance
deterioration, and hence a 20-bit representation of the coefficients in (7.4) was used.
This was possible because the input to the filter, ie. the measured system voltage vD,
comes from the ADC, which has only a 10-bit resolution. A larger than 20-bit
representation for the coefficients would result in overflows when the terms in (7.4)
are added under certain conditions.
Satisfactory performance has been achieved in simulations and experiments with the
conventional shift operator implementation of resonant filters given in (7.3) and (7.4).
However, when compared to PSCAD simulations based on continuous time s-domain
transfer functions, some performance degradation can be observed. With the shift
operator implementation, the shape of the compensated system voltage vD changes
slightly from cycle to cycle, causing significant fluctuations in its rms value. This is
due to roundoff errors associated with the use of integer variables on a fixed-point
DSP (so-called finite word length effect). 16-bit fixed-point implementations always
have finite word length effects, but the problem is particularly pronounced at a fast
sampling rate and for sharply tuned filters such as the resonant filters used in the TPQC.
To improve performance, the use of the delta operator 8 in place of the conventional
shift operator has been investigated. The delta operator has recently gained interest in
fast digital control due to its superior finite word length performance [175-177]. The
delta operator can be defined in terms of the more familiar conventional shift operator
zas
As'1
1-z' 1
(7.5)
168
CHAPTER 7:
Description of Experimental Systems
where A is a positive constant less than unity which must be chosen. Essentially, deltc
operator filter implementation involves converting a second order section in z:
-1
-I
-2
+b
2z
a2z
(7.6)
-2
into a corresponding second order section in 8:
(7.7)
using the conversion formulae listed in Table 7.6. Equation (7.7) is then implemented
using the transposed direct form II (DFIIt) structure shown in Figure 7.9. Of the many
filter structures available, the DFIIt has been shown to possess the best roundoff noise
performance for delta operator based filters [176]. From Figure 7.9, the difference
equations to be coded for the DSP can be written, in processing order, as:
I
w4 («) = Aw 3 (« -1) + w4 {n -1)
w2 (n) = Aw, (« -1) + w2 (n -1)
y(n) = pox{n) + w4{n)
w3(n) = Pxx(n) - axy(n) + w2 (n)
ws(n) = p2x{n)-a2y{n)
(7.8)
Note that the first two equations in (7.8) for w4(n) and w2(n) are obtained from the
definition of the delta operator given in (7.5). Similar to (7.4), the coefficients in (7.8)
will initially be floating point numbers and must be normalised by multiplying them
Po
Bo
cto
I
p.
2b,+bx
A
a.
2 +a,
A
p*
bo+br+ b2
A2
a2
l + a, + a2
A2
I
Table 7.6: Conversion formulae from second-order shift to delta coefficients
169
CHAPTER 7:
Description of Experimental Systems
x(n) O—•-
-O
-o y(n)
w4(n)
p<
^
'
w,(n)
0-
w2(n)
O
Pz w,(n)
-0-
-a,
-6
Figure 7.9: Direct form II transpose (DFIIt) structure for second-order digital filter
by the maximum integer value of the chosen word length. Here, the word length and
the constant A represent two degrees of design freedom that are used to optimise the
roundoff performance against coefficient quantisation and potential overflows, often
by trial and error. PSCAD simulations have shown that a word length of 21 bits and A
= 1/16 produces excellent results for the purposes of this thesis, and this has been
confirmed in the experimental studies.
DC Bus Regulation
For the DC bus regulation loop, the PI controller
(7.5)
Gdc(s) =
is discretised using the backward-rectangular integration [178] to obtain a discrete
equivalent controller
(7.6)
l —z
where T = sampling period. If x and y denote respectively the input and output of the
PI controller, then the corresponding difference equations for (7.6) are
I
170
CHAPTER 7:
Description of Experimental Systems
n) = KP-x(n)
(7.7)
Of course, I(n) needs to be suitably clamped to provide integral anti-windup. Further,
the equations in (7.7) have to be appropriately scaled to prevent overflows on a 16-bit
data representation whilst maximising the resolution.
i
In the actual experimental code, a loop counter is maintained to ensure that the DC
regulation block is only executed once every ten main interrupt calls, giving the DC
bus regulation loop an effective sampling rate of 1kHz. This is possible because the
DC bus regulation loop is relatively slow, and does not require a particularly high
sampling rate. This frees up valuable CPU time for other tasks.
Reactive Power Compensation
The reactive power compensation loop mainly consists of a running window rms
calculator followed by a PI controller. The PI controller is implemented in a similar
fashion as for the DC bus regulation controller discussed above. The rms calculator
employs a similar algorithm as that described in Section 6.7 to calculate a sum of
squares during each sampling interval, and then uses a look-up table to perform the
square root operation as it is too costly to calculate square roots in real time.
7.6.2
Background Code
The background code coordinates the various background tasks according to the finite
state machine shown in Figure 7.10. State transitions are triggered by user inputs (eg.
Start Pressed, Stop Pressed), hardware interrupts (eg. Fault) or simply just the
completion of designated tasks (eg. Initialisation Complete, Ramp Up Complete).
Each time a state is traversed, the DSP also performs other housekeeping tasks such
as:
171
CHAPTER 7:
Description of Experimental Systems
• checking for various faults, including gate faults, DC bus overvoltage, lost of
synchronisation, etc;
• calculating rms and form factor values for the four measured voltages VA, VB, VC
and VD to be sent to host PC for display;
• communicating with host PC via the RS-232 serial link. This allows compensation
to be started and stopped from the host PC and on-line variation of harmonic
compensation gain and reactive power compensation reference rms voltage.
Critical system data such as rms and form factor values, current system state are
also sent to the host PC for display.
7.7
SUMMARY
This chapter has described the experimental systems used to verify the theoretical
analysis and simulation studies for the proposed traction power quality conditioner,
Otherwise
Wait
Otherwise
Wait
Otherwise
Wait
State
___
Init yinitialisation\Restart
Complete
J1
Otherwise
Increase DC
Bus Reference
Otherwise
Update from
Background
Wait for
Cleared and
Acknowledged
Fault
I
I
Otherwise
Decrease DC
Bus Reference
Figure 7.10: State transition diagram for the background code
172
CHAPTER 7:
Description of Experimental Systems
which have also provided additional confidence to the practicality of the proposed
conditioner.
A 150V scale model of a 30km traction system has been constructed using available
I
laboratory equipment. Two experimental inverters were also assembled for the TPQC, one being a conventional H-bridge and the other being a cascaded five-level
VSI. These were sufficient to confirm the performance of the T-PQC.
The T-PQC was controlled with a DSP controller and a hysteresis current regulator.
Major aspects of hardware and software pertaining to the DSP controller have been
presented, with particular emphasis given to illustrating how the analog continuous
time concepts assumed in Chapters 4 and 5 translate into realistic and low-cost fixedpoint digital implementations. The hysteresis current regulator used was an existing
experimental board designed to control three-level switcb'^3 of a conventional Hbridge.
Having clarified the experimental systems adopted, Chapter 8 presents the
experimental results obtained and a comparison of these results with the
corresponding simulation results.
i1
173
CHAPTER 8: SIMULATION AND
EXPERIMENTAL RESULTS
»*•**
jr*M*rw*x*r**jr-m*jr.*.4rM.rjrjrjr**WMM.wrjr*M.jr^.sr*jr-s,jr.jrMjrw-jrmjr***:jr.jrjrrjr-jrjr*.***:*.+rjr~.r**
+
The previous two chapters have described respectively the computer simulations, and
the hardware and software details of the experimental systems used to verify the
simulation work. In this chapter, simulation results are first presented to examine the
steady-state system performance for a representative 25kV railway system.
Corresponding experimental results are then presented and compared to confirm the
validity and practicality of the simulation studies. The experimental system is also
used to investigate the dynamic and transient interactions between the T-PQC and the
traction system. Finally, sensitivity studies are carried out to confirm the robustness
and generality of the proposed T-PQC and its associated control algorithms.
As noted in Chapter 7, not all simulation studies have been explored experimentally.
I
This was considered unnecessary, since the primary reasons for the experimental
investigations are to confirm the validity of the simulation processes, to make sure
nothing important has been neglected in the simulations, and to provide additional
confidence as to the practicality of the proposed traction power quality conditioner.
Hence only a two-level VSI and a cascaded five-level VSI have been investigated
experimentally for a selected range of loading conditions.
8.1
LABORATORY INSTRUMENTATION
Time varying plots of voltages and currents were captured using a LeCroy 9314L
300MHz Quad channel digital oscilloscope. These were recorded as HPGL graphics
files on floppy discs and subsequently read into the word processor for further minor
cosmetic touch-ups such as labelling of individual traces and scaling to fully occupy
plotted windows. Voltages were measured using SI-9000 high voltage differential
probes, whilst currents were measured with Tektronix A6302 Current Probes through
Tektronix AM53OA/B Current Probe Amplifiers. Both transducers have bandwidths
in excess of 20MHz, allowing all relevant details of the PWM systems to be captured
with high precision.
174
CHAPTER 8:
Simulation and Experimental Results
Harmonic spectra were measured using a Hewlett Packard 35665A Dynamic Signal
Analyser, which uses a Fast Fourier Transform algorithm. All measurements were
processed using a Hanning filter window, plotted as HPGL graphics files to a floppy
disc, and finally inserted into the word processor.
As closed-loop hysteresis modulation is asynchronous in nature, which means that the
switching harmonics will be slightly different from cycle to cycle, continuous
fluctuations can be expected in the harmonic spectrum displayed on the signal
analyser. To provide consistent results that can be compared against simulation
studies, the harmonic plots were captured with averaging over 20 fundamental cycles.
8.2
STEADY STATE PERFORMANCE
To investigate the performance of the proposed T-PQC on a railway system, 9 typical
loading conditions have been selected for simulation and experimental studies. They
are listed in Table 8.1. Unless otherwise indicated, the numbers in the table represent
the numbers of 2.5MW locomotive units operating at full DC load current with both
bridges at full conduction. Thus a '2' at a given node denotes a 5MW locomotive
connected to that node. Cases 1-6 represent varying degrees of load dispersion with a
total of 10MW load. Case 7 considers a heavily overloaded situation with a total of
Case
Node A
NodeB
NodeC
NodeD
1
0
2
0
2
2
2
0
2
0
3
0
0
2
2
4
2
0
0
2
5
0
0
0
4
6
1
1
1
1
7
1
1
2
2
8
0
0
2 (72°)
2 (90°)
9
0
2 (80%)
0
2 (80%)
Table 8.1: Loading conditions for the 30km feeder section (units of 2.5MW
locomotives at full load current unless indicated otherwise)
175
CHAPTER 8:
Simulation and Experimental Results
15MW traction load on a 30km feeder section. In case 8, the locomotives operate at
full DC current with 72° and 90° delay firing angles on the second thyristor bridges,
thus representing regime 2 operation. The delayed firing has a tendency to excite
harmonic overvoltages. Finally in case 9, the locomotive DC currents are at 80% of
the full value, representing regime 4 operation.
8.2.1
Simulation Results
PSCAD simulations have been carried out for the 9 loading cases shown in Table 8.1.
The width of the hysteresis current error band was adjusted to give an average
switching rate per switch of approximately 4kHz. The output of the PI stage in the
reactive power control loop was clamped at 297A to limit the rms fundamental
reactive current at 210A. A K = -0.2 (5Q termination) and coc = 10 rad/s for the
harmonic compensation loop were used. The voltage set point for the reactive power
compensation loop was set to the nominal system voltage of 25kV, so that the T-PQC
would attempt to boost the terminal voltage as close to 25kV as allowed by its current
limit.
Figure 8.1 and Figure 8.2 show the voltage and current waveforms for case 1 and case
8 respectively before any compensation is applied, which represent typical waveforms
for an uncompensated railway system. The pantograph voltage at node D is highly
distorted with low order harmonics, superimposed with a small amount of high
frequency oscillation at about 1.3kHz. In Figure 8.2, the high frequency oscillation is
more pronounced because of delayed firing, resulting in a higher crest value. Note
also the steps in the load currents ILc and ILU associated with delayed firing.
Figure 8.3 ~ Figure 8.5 show the waveforms for selected cases after compensation is
applied. With the T-PQC acting to mitigate the third, fifth and seventh harmonic
components, the low-order harmonic distortions of vd are no longer visible although
the characteristic high frequency resonance still remains, particularly in Figure 8.5.
Note the three-level output voltages Vjnv used for the two-level VSI.
176
CHAPTER 8:
Simulation and Experimental Results
,-S-Vd
0.07
0.03
0.04
0.05
0.06
0.07
Time (sec)
Figure 8.1: Simulated waveforms for case 1, before compensation - vd: voltage at the
end of feeder section. Is: feeder substation transformer current. ILB, ILD: various
traction load currents.
.-8-Vd
I
•°<S02
0.03
0.04
0.05
0.06
0.07
Time (sec)
Figure 8.2: Simulated waveforms for case 8, before comepnsation - v,j: voltage at the
end of feeder section. Is: feeder substation transformer current. ILC, ILD: various
traction load currents.
The performance and benefits gained from the installation of the T-PQC are most
evident when considering the effects on the feeder voltage form factor and rms value.
Figure 8.6 and Figure 8.7 compare the voltage form factor along the contact feeder for
cases 1-5 before and after the sapplication of T-PQC. For better clarity, results for
cases 6-9 are shown separately in Figure 8.8 and Figure 8.9. Without T-PQC
compensation, there are considerable low-order harmonic components present in the
feeder voltage and the voltage form factors are worst at the end of the feeder section.
However, as Figure 8.7 and Figure 8.9 indicate, by mitigating the voltage distortion
due to low order harmonics, the T-PQC is effective in keeping the voltage form
factors close to the ideal value of 1.11 throughout the entire length of the contact
feeder in all cases considered. As a result of form factor improvement alone, up to
10% more power is available to the locomotives.
177
f&'WPSi
CHAPTER 8:
Simulation and Experimental Results
At the same time, Figure 8.10 and Figure 8.11 clearly demonstrate the voltage
boosting effect of the T-PQC for cases 1-5. Again for clarity, results for cases 6-9 are
separately shown in Figure 8.12 and Figure 8.13. Without T-PQC compensation, the
voltage droops along the feeder and the minimum tolerable level of 17.5kV is reached
in some cases. However, the T-PQC is able to boost the voltage up to a more
acceptable operational level. In all cases, voltage increases at nodes A, B, C and D are
about 9%, 15%, 20% and 27% respectively. In particular, case 7 represents 15MW of
load on a 30km feeder section; this would have overloaded the system without the TPQC. By providing reactive power compensation, the T-PQC allows the system to run
under what would otherwise have been an overloaded system, without requiring any
major system upgrades.
.-a-vd
8?
0.07
I
0>
I
0.07
a>
0.07
1
3
0.03
0.04
0.05
0.06
0.07
Time (sec)
Figure 8.3: Simulated waveforms for case 1, after compensation with basic two-level
VSI - v,j: voltage at the end of feeder section. Vjnv: T-PQC inverter switched voltage.
Is: feeder substation transformer current. ILB, ILD: various traction load currents. Iinv:
T-PQC inverter current.
178
CHAPTER 8:
+50
Simulation and Experimental Results
-B-Vd
0.07
0.07
0.07
0.03
0.04
Time (sec)
0.05
0.06
0.07
Figure 8.4: Simulated waveforms for case 6, after compensation with basic two-level
VSI - vd: voltage at the end of feeder section. Vjnv: T-PQC inverter switched voltage.
Is: feeder substation transformer current. ILA, ILB, ILC, ILD: various traction load
currents. Ijnv: T-PQC inverter current.
.-S-Vd
0.08
0.08
0.08
0.032
0.044
Time (sec)
0.056
0.068
0.08
Figure 8.5: Simulated waveforms for case 8, after compensation with basic two-level
VSI - vd: voltage at the end of feeder section. vinv: T-PQC inverter switched voltage.
Is: feeder substation transformer current. ILC, ILD: various traction load currents. Iinv:
T-PQC inverter current.
179
im
CHAPTER 8:
Simulation and Experimental Results
1.29
— • - —Case 1
- • --Case 2
1.27-
....£. -•-Case
1.25-
I
— X—
-
1.23
3
Case 4
X • -Case 5
45
1.13
1.11
0
5
10
15
20
25
30
Feeder length (km)
Figure 8.6: Voltage form factor as a function of distance along feeder section for
cases 1-5, before compensation.
1.29
•—Case 1
--B--Case2
... . ± — Case w
1.25 - — X— Case 4
—X—Case 5
1.27
1.23
|
1.21
©
1.19
re
I
1.17
1.15
1.13
j
A
1.11
i
1
1
1
1
1
1
10
15
20
25
30
Feeder length (km)
Figure 8.7: Voltage form factor as a function of distance along feeder section for
cases 1-5, after compensation.
180
=*=Lisky**^™f^-"»^"3^^^
CHAPTER 8:
Simulation andExperimental Results
1.29
0
10
15
20
25
30
Feeder length (km)
Figure 8.8: Voltage form factor as a function of distance along feeder section for
cases 6-9, before compensation.
1.29 T
— * —Case 6
1.27-
--• -
- Case 7
....± • -•Cases
1.25-
— K — Case 9
|
1-2342
E 1.21 £
o 1.19O)
ra
|
1.17-1
1.15
1.13
1
. . - A •"•
L^^----- -;"'"-*"
,1.11
10
---..
15
20
25
30
Feeder length (km)
Figure 8.9: Voltage form factor as a function of distance along feeder section for
cases 6-9, after compensation.
181
CHAPTER 8:
Simulation and Experimental Results
25.0
10
15
20
25
30
Feeder Sength (km)
Figure 8.10: Feeder voltage as a function of distance along feeder section for cases 15, before compensation.
Case 1
--•--Case 2
• •-•A----Case3
Case 4
— X - -Case 5
0
10
15
20
25
30
Feeder length (km)
Figure 8.11: Feeder voltage as a function of distance along feeder section for cases 1 5, after compensation.
182
CHAPTER 8:
Simulation and Experimental Results
24.023.0;
~ 22.0 *
f 21.0 I 20.0 '
eo 19.0K
""•A
** ^. ^
18.017.G 16.0 -
-ii
—«—Case 6
--•--Case7
....^.. ..Case 8
— K— Case 9
15.0- . ... ., _, .... r ,. ,
,
,
,
.
10
15
20
25
l^dll
30
Feeder length (km)
Figure 8.12: Feeder voltage as a function of distance along feeder section for cases 69, before compensation.
25.0 q
Case 6
--•--Case 7
A-.--Case8
— X— Case 9
10
15
20
25
30
Feeder length (km)
Figure 8.13: Feeder voltage as a function of distance along feeder section for cases 69, after compensation.
183
^'fA>r;^i&£?j£i5i&3Jfr»rt<
CHAPTER 8:
Simulation and Experimental Results
The simulation studies also confirm that at full operating capacity, the total rms
inverter current is about 0.26kA, of which 0.1 kA is at harmonic frequencies and the
remaining 0.24kA is at the fundamental frequency. Note that the fundamental
frequency current component is about 15% larger than the limit imposed by the PI
stage mentioned earlier, because the resonant filters are not infinitely selective. Given
that the inverter voltage rating is taken to be the maximum allowable 27.5kV, the
inverter should be rated at no less than 7.2MVA, about 2.8MVA of which is used for
harmonic compensation and the remaining 6.6MVA used for reactive power
compensation.
8.2.2
Comparison of Simulation and Experimental Results
The experimental waveforms for case 1 before compensation are given in Figure 8.14,
which should be compared to Figure 8.1. Again, the uncompensated vD is rich in low
order harmonics with a small amount of high frequency component at around 1.3kHz.
As mentioned in Chapter 5, whilst a basic two-level VSI alone is useful in illustrating
the operational principles and performance of the T-PQC, it is more robust to employ
an additional passive high-pass filter to form a hybrid topology. This not only
eliminates any harmonic overvoltage problems but also allows a lower inverter
J1
ILD
z
Figure 8.14: Experimental waveforms for case 1, before compensation - VD: voltage
at the end of feeder section. vA: voltage at node A. iLo: traction load current at node
D. i s : feeder substation transformer current.
184
smi
CHAPTER 8:
Simulation and Experimental Results
switching frequency to be used and at same time producing less switching noise on
the pantograph voltage.
Figure 8.15 and Figure 8.16 show the simulated waveforms for cases 1 and 5
respectively when compensated by a hybrid two-level VSI (ie. passive damping filter
plus conventional H-bridge). Note that the voltage form factors and rms values remain
substantially the same compared to those given in Figure 8.7 and Figure 8.11
respectively. The obvious differences by adding the passive damping filter are the
much-reduced switching noise on VD and the absence of any 1.3kHz harmonic
overvoltages. This is despite the fact that the hysteresis error band width used has
been increased to reduce the switching rate per invsrter switch to about 2kHz. This
confirms the ability of the passive damping filter to absorb the switching harmonics
produced by the T-PQC, in addition to damping any possible resonances excited by
the traction load. The corresponding experimental waveforms are given in Figure 8.17
and Figure 8.18 for cases 1 and 5 respectively, which demonstrate close resemblance
to the simulation results.
Figure 8.19 compares the simulated and experimental harmonic spectra for vD in case
1 before compensation. Both plots show that vp is rich in low order harmonic content
(the 3rd harmonic is about 10% of fundamental component), and contains a small
resonant peak at around 1.3kHz. Simulated and experimental harmonic spectra for VD
after compensation are given in Figure 8.20, which highlights the suppressions of 3 rd ,
5th and 7th harmonics by the T-PQC. As only the lowest three harmonics are
compensated, a relatively high (by public power system's standard) compensated
THD of 10% is obtained. It should however be remembered from the discussion in
Chapter 2 that the THD is quite irrelevant in traction systems, and the voltage form
factor is a more useful measure of quality of supply. Once again, the closeness of
match between the two plots reaffirms the accuracy and validity of both simulation
and experimental studies.
185
CHAPTER 8:
Simulation and Experimental Results
0.04
Time (sec)
Figure 8.15: Simulated waveforms for case 1, after compensation with hybrid twolevel VSI - Vd: voltage at the end of feeder section. Vjnv: T-PQC inverter switched
voltage. Is: feeder substation transformer current. ILB, ILD: various traction load
currents. Iinv: T-PQC inverter current.
,-e-vd
0.07
0.07
1
0.04
Time (sec)
Figure 8.16: Simulated waveforms for case 5, after compensation with hybrid twolevel VSI - vd: voltage at the end of feeder section. vInv: T-PQC inverter switched
voltage. Is: feeder substation transformer current. ILD: traction load current at node D.
liny" T-PQC inverter current.
186
CHAPTER 8:
Simulation and Experimental Results
Figure 8.17: Experimental waveforms for case 1, after compensation with hybrid twolevel VSI - vD: voltage at the end of feeder section. v,nv: T-PQC inverter switched
voltage. JLD- traction load current at node D. ijnv: T-PQC inverter current.
vD
il
!
Figure 8.18: Experimental waveforms for case 5, after compensation with hybrid twolevel VSI - VQ: voltage at the end of feeder section. v,nv: T-PQC inverter switched
voltage. iLo: traction load current at node D. iinv: T-PQC inverter current.
187
I
CHAPTER 8:
Simulation and Experimental Results
(a)
10°
f KO (up:to:6j4kHzJ= 2817%:
-•3"lhannonic;
/
t*
£<*»
1
•a
o
to
10'2
10"3
3
Frequency (kHz)
(b)
10°
4
|Tf+D; (up;to;?J4kHz)f 29:7^:; ;j
I. . . ' l i ' l l II'. ' . ' i . i l l i ' l i . '
5" hamwrjlc
//"harmomc
!
System
rosonanco
10"'
c
D)
n
10 z
I
l
10-3
lifel/l
3
Frequency (kHz)
4
Figure 8.19: (a) Simulated and (b) Experimental vD harmonic spectra for case 1 before
compensation
1S8
CHAPTER 8:
Simulation and Experimental Results
(a)
::::::::::::fr^
iff1
•a
"£
10-
2
o
3
Frequency (kHz)
4
(b)
10°
:::::::::£
THD.(up{di6 4KHz)=TO:0^
•
td
3 . 5"*and 7*
10"1
:
;.. ...
/
"[';1
::::::::::Ljl:jj •:i"jiii"blJi:i::|.:::|::ii:
10"
Q)
in
O
10 3
•"1
i
:::::
1
1
3
4
Frequency (kHz)
Figure 8.20: (a) Simulated and (b) Experimental vD harmonic spectra for case 1 after
compensation
Table 8.2 provides quantitative comparisons of voltage rms values and form factors
obtained from simulations and experiments, for cases 1 and 5 before compensation.
Table 8.3 compares the results obtained after compensation. From both tables, it is
189
CHAPTER 8:
Simulation and Experimental Results
clear that the discrepancies between the form factors are all less than 1% whereas the
rms values can differ up to 5%. These discrepancies are most likely due to the
difficulty in accurately measuring the system inductors used, particularly those with
magnetic cores which have non-linear characteristics at harmonic frequencies.
Nevertheless, these are considered good matches and confirm the validity of the
simulation results presented in the previous subsection.
Casel
Case 5
Simulation
FA-periment
Simulation
Experiment
vARMS
22.0 kV
:o.9 kv
21.8 kV
20.7 kV
vBRMS
20.1 kV
9.4 kV
19.8 kV
19.2 kV
v c RMS
19.2 kV
18.6 kV
18.0kV
17.6 kV
v D RMS
18.3 kV
17.8 kV
16.2 kV
16.3 kV
vA F.F.
1.14
1.14
1.13
1.13
v B F.F.
1.17
1.17
1.15
1.16
v c F.F.
1.19
1.19
1.19
1.19
vD F.F.
1.22
1.21
1.24
1.25
Table 8.2: Comparison of simulation and experimental results for cases 1 and 5 before
compensation.
Case 5
Casel
Simulation
Experiment
Simulation
Experiment
vARMS
24.4 kV
23.7 kV
24.0 kV
23.5 kV
vBRMS
23.6 kV
23.4 kV
23.0 kV
23.1 kV
VcRMS
23.8 kV
23.6 kV
22.1 kV
22.4 kV
vDRMS
24.1 kV
23.9 kV
21.3 kV
22.1 kV
vA F.F.
1.12
1.12
1.12
1.12
F.F.
1.14
1.13
1.12
1.12
v c F.F.
1.13
1.13
1.13
1.12
vD F.F.
1.13
1.12
1.13
1.12
VB
I
Table 8.3: Comparison of simulation and experimental results for cases 1 and 5 after
compensation.
111
190
jf
CHAPTER 8:
8.2.3
Simulation and 2-cperimental Results
Comparison of Multilevel and Two-level VSI Compensations
To further reduce the switching noise and extend the maximum T-PQC rating for long
feeders, a hybrid multilevel T-PQC topology has been proposed in Chapter 5. A
hybrid multilevel T-PQC employing a reduced switch-count five-level inverter has
been simulated for case 1, as shown in Figure 8.21. The inner hysteresis band width
has been adjusted so that the IGBT switches in the three-level phase leg of the
reduced topology operate at an average switching rate of 2kHz. Again, the presence of
the passive high-pass filter allows operation at this relatively low switching rate
without any resonance complications. Whilst similar levels of voltage rms and form
factor improvements are achieved, it is clear :hat the switching noise on VQ is
significantly less than that shown in Figure 8.15. This is a direct consequence of the
five-level switching strategy adopted, and confirms the effectiveness of the proposed
current regulation strategy for the reduced topology, which is able to generate the
fundamental plus harmonic inverter current as demanded. For experimental
confirmation of multilevel operation, a cascaded five-level inverter is used, as
described in Chapter 7. Figure 8.22 shows the resulting experimental waveforms,
which are seen to match Figure 8.21 closely. This establishes the practicality of the
proposed current regulation strategy.
The performance improvement using a five-level inverter is further confirmed by
Figure 8.23, which compares the experimental VD harmonic spectra for case 1 using a
five-level T-PQC and a two-level T-PQC, both operating at full capacity. It is clear
that the five-level system generates significantly less high frequency switching noise
on vD compared to the conventional two-level VSI system. Further, since each of the
IGBTs of the five-level inverter (for both the ca caded and reduced switch-count
IS
topologies) now needs to block only half the DC bus voltage as opposed to the full
DC bus voltage for the H-bridge, the switching rate of the five-level inverter can be
increased to further optimise the harmonic performance whilst maintaining similar
switching stress on the switches. Figure 8.24 shows the experimental waveforms for
case 1 when the average device switching rate is increased to about 2.7kHz. The
improvement in vD switching ripple is obvious when compared to Figure 8.22.
I
191
CHAPTER 8:
Simulation and Experimental Results
,-B-Vd
CD
DO
TO
**
CD
00
I
0)
•3
°<S02
0.03
0.04
0.05
O.06
0.07
Time (sec)
Figure 8.21: Simulated waveforms for case 1, after compensation with reduced fivelevel VSI, favg ~ 2kHz - V<J: voltage at the end of feeder section. Vjnv: T-PQC inverter
switched voltage. Is: feeder substation transformer current. 1LB, ILD: various traction
load currents. Ijnv: T-PQC inverter current.
VD
Via
>LD
Figure 8,22: Experimental waveforms for case 1, after compensation with reduced
five-level VSI, favg ~ 2kIIz - vD: voltage at the end of feeder section. vinv: T-PQC
inverter switched voltage. iLD." traction load current at node D. ijnv: T-PQC inverter
current.
192
CHAPTER 8:
Simulation and Experimental Results
Frequency (kHz)
12.8
10°
Frequency (kHz)
12.8
Figure 8.23: Experimental vD harmonic spectrum for (a) Five-level inverter (b) Twolevel inverter (conventional H-bridge)
193
CHAPTER 8:
Simulation and Experimental Results
\
Vin
-vA
if1
ILD
Figure 8.24: Experimental waveforms for case 1, after compensation with reduced
five-level VSI, favg ~ 2.7kHz - VD: voltage at the end of feeder section. Vjnv: T-PQC
inverter switched voltage. iu> traction load current at node D. ijnv: T-PQC inverter
cuirent.
\
X
Vin
"At
\
ILD
*
\
m
J
k
Vi mm*
\
y
/ -
y
\
A w
Hi
H
y
—
\^—*
•
/
ws
/
Figure 8.25: Experimental waveforms for case 5, after compensation wilh reduced
five-level VSI, favg ~ 2kHz - vD: voltage at the end of feeder section. Vjnv: T-PQC
inverter switched voltage, ILD-' traction load current at node D. ijnv: T-PQC inverter
current.
Finally, Figure 8.25 shows the experimental waveforms for case 5, again switched at
around 2kHz. Note the load current i[.D is twice as large as that in Figure 8.22 (see
case definitions in Table 8.1). This confirms the proposed hybrid multilevel T-PQC is
practical under a range of operating conditions.
194
CHAPTER 8:
8.3
Simulation and Experimental Results
DYNAMIC PERFORMANCE
The T-PQC forms a feedback closed loop control system with the railway supply
system. The T-PQC controller measures the terminal voltage VD and uses it to
generate the harmonic current reference and reactive current reference, which are used
to improve various aspects of vD. As in any feedback system, system instability can
result if the controller is not properly designed. To ensure that the T-PQC control
system is stable, the terminal voltage VD is dynamically monitored for its fluctuation
levels. When working under a constant load, an acceptable level of VD rms fluctuation
has to be demonstrated, hi the experimental system, the DSP records the
instantaneous values of VD at a sampling rate of 10kHz over 22 fundamental cycles,
giving 4400 data points. These were then post-processed in Microsoft Excel
spreadsheets to calculate the instantaneous rms values using equation (6.3) by moving
across one sample point at a time.
Figure 8.26 shows the instantaneous vp rms values for case 1 over 22 fundamental
cycles when it has been compensated by the five-level T-PQC. The instantaneous rms
values have been normalised against their mean value (set to 100%) to highlight the
fluctuation levels. It is seen that the fluctuations are less than 0.6%, which indicates
the control system is siable and satisfactory for operation in railway systems.
For comparison, Figure 8.27 shows the VD rms values for the same condition as above
but with the resonant filters in the DSP controller implemented using the conventional
shift, operator rather than the delta operator (see Subsection 7.6.1). Fluctuations in
excess of 2% are observed when the shift operator is used. This is due to the much
poorer roundoff and coefficient quantisation properties of shift-based implementations
I
at a high sampling rate.
195
CHAPTER 8:
Simulation and Experimental Results
102
101.5 •
~-
101 •
©
OS
I
100.5 •
100- •--
8
99.5 4
o
9998.598
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Time (sec)
Figure 8.26: Experimental VD RMS values for case 1 over 22 fundamental cycles,
resonant filters implemented using delta operator
102
0.15
0.2
0.25
0.3
0.35
If
0.4
Time (sec)
Figure 8.27: Experimental vD RMS values for case 1 over 22 fundamental cycles,
resonant filters implemented using conventional shift operator
The poorer performance of the shift based resonant filter implementation is also
evident by comparing the VD waveforms for case 1 in Figure 8.28 and Figure 8.2e In
Figure 8.28 the delta compensated vD looks very much sinusoidal and its shape does
not change appreciably from ne cycle to another (except for the high frequency
switching components, since i^Jteresis switching is asynchronous). On the other
196
CHAPTER 8:
Simulation and Experimental Results
hand, the shift compensated vD waveform in Figure 8.29 varies from pointy to flat
from one cyclf? to another as the low frequency compensation struggles to settle to a
steady level, giving rise to fluctuations in the instantaneous rms values observed in
Figure 8.27.
A railv/ay system normally experiences large disturbances as locomotives are
frequently switched on and off from the overhead network, and locomotives can work
over a very wide voltage range from 19kV to 27.5kV. Therefore even the 2%
'LD
Figure 8.28: Experimental waveforms for case 1, resonant filters implemented using
delta operator
i
m
1LD
Figure 8.29: Experimental waveforms for case 1, resonant filters implemented using
conventional shift operator
197
CHAPTER 8:
Simulation and Experimental Results
fluctuations obtained from a shift-based implementation are likely to be acceptable.
However, there is no reason to settle for sub-optimal performance when significant
improvements are readily available for the same capital investment just by using
improved computational procedures.
8.4
TRANSIENT PERFORMANCE
A railway line typically consists of many feeder sections, each single-endedly fed
from a substation transformer. When a locomotive passes from one feeder section to
the next, it is seldom that the locomotive is gradually powe-ed down as it approaches
the track-sectioning cabin. The first feeder will thus experience a sudden loss of load.
This condition is shown in Figure 8.30 for case 1. Initially, two 5MW locomotives are
situated at Node B and D respectively, and the five-level TQPC is operating at full
harmonic and reactive power compensation capacity. The load ILD is then abruptly
interrupted. Figure 8.30 experimentally confirms that the proposed compensation
system is robust, and remains stable during and after such a big disturbance.
I
Figure 8.30: Sudden loss of iLD when T-PQC is operating, experimental waveforms vB: voltage at 10km point of feeder section. vD: voltage at end of feeder secrtion. iix>:
II
traction load current at node D. iinv: T-PQC inverter current.
'is
198
I
CHAPTER 8:
8.5
Simulation and Experimental Results
SYSTEM SENSITIVITY STUDIES
Thus far, the simulation and experimental results presented have shown that the
proposed T-PQC is effective on the particular railway system chosen under a wide
range of loading conditions. To demonstrate that the TQPC is in fact a robust system
that is applicable to more than just one particular 25.W railway system, sensitivity
studies have been performed. The railway system parameters are changed to show
that the T-PQC is still able to achieve similar performance benefits. Only simulations
are carried out iiere, since the accuracy and practicality of the simulation models have
already been established in the last few sections.
A total of 7 cases have been selected for sensitivity studies, as defined in Table 8.4.
Note that case 1 of Table 8.1 has been selected as the base case, ie. all sensitivity
studies assume two 5MW locomotives at node B and node D respectively. Cases SlS6 represent different combinations of variations in traction overhead transmission
line parameters. Case S7 examines the scenario when a 5MVAR power factor
correction (PFC) arm consisting of a series reactor and capacitor is installed at the
feeder substation. It is not uncommon in railway systems to employ PFC equipment at
feeding terminals to avoid the hefty penalties associated with a low power factor
imposed by the public supply companies [179].
Case
Changes
SI
Longitudinal inductance L increased by 20%
S2
Longitudinal resistance R increased by 20%
S3
Shunt capacitance C increased by 20%
S4
L, R and C all increased by 20%
S5
Longitudinal inductance L decreased by 20%
S6
L, R and C all decreased by 20%
S7
Installation of a 5MVAR PFC arm (tuned at 2.5th harmonic) at feeder
substation
H
I!
Table 8.4: Case definitions for sensitivity studies
V
r
?
i
199
CHAPTER 8:
Simulation and Experimental Results
The results of the sensitivity studies are summarised in Table 8.5 and Table 8.6 for
rms voltage and voltage form factor respectively. In all 7 cases considered, the
boosting of the rms voltages and reduction of form factors throughout the entire
feeder length are evident. This confirms that the excellent performance of the
proposed T-PQC is not sensitive to railway system parameter changes, and it
represents a robust and genera! solution to 25kV 50/60Hz AC railway systems.
8.6
SUMMARY
This chapter has presented simulation and experimental results to confirm the
effectiveness and practicality of the proposed T-PQC and its associated control
algorithm. A 7.2MVA T-PQC and a 30km realistic railway system, loaded with a total
of 10MW to 15MW locomotives arranged in 9 different conditions, have been
investigated in PSCAD. In all cases, the T-PQC has been effective in bringing the
voltage form factor close to 1.11 and boosting the feeder rms voltages by up to 30% at
the feeder end. These simulation findings have been closely matched by experimental
Case
NodeB
Node A
NodeC
NodeD
Before
After
Before
After
Before
After
Before
After
SI
21.85
24.30
19.67
23.47
18.61
23.79
17.60
24.23
S2
21.96
24.37
19.96
23.44
19.00
23.57
18.06
23.82
S3
21.95
24.41
20.08
23.63
19.19
23.85
18.3!
24.17
S4
21.89
24.29
19.62
23.30
18.53
23.53
17.48
23.89
S5
22.01
24.49
20.40
23.75
19.62
23.84
18.85
24.06
S6
21.98
24.51
20.49
23.93
19.76
24.08
19.04
24.38
S7
24.22
26.26
22.30
25.18
21.39
25.02
20.49
25.02
Table 8.5: RMS Voltage (kV) before and after compensation for sensitivity studies
Case
NodeB
Node A
NodeD
NodeC
Before
After
Before
After
Before
After
Before
After
SI
1.14
1.12
1.17
1.14
1.20
1.13
1.22
1.13
S2
1.14
1.12
i.17
1.13
1.19
1.13
1.22
1.13
S3
1.14
1.12
1.17
1.13
1.20
1.13
1.22
1.13
S4
1.14
1.12
1.18
1.14
1.20
1.13
1.23
1.13
S5
1.14
1.12
1.17
1.13
1.19
1.13
1.20
1.13
S6
1.14
1.12
1.17
1.13
1.19
1.13
1.20
1.13
S7
1.12
1.12
1.15
1.13
1.17
1.13
1.19
1.13
•'1
Table 8.6: Voltage form factor before and after compensation for sensitivity studies
200
CHAPTER 8:
Simulation and Experimental Results
results for T-PQCs employing both a conventional two-level VSI and a five-level
VSI. It has also been shown that, with careful software implementation of digital
filters, the rms voltage fluctuations can be brought to below 1% even with a low-cost
16-bit DSP. The proposed T-PQC has also been experimentally proven to be robust
against large disturbances such as a sudden loss of load, which is a common
occurrence in railway systems. Finally sensitivity studies have indicated that the TPQC is equally effective when applied to railway systems with different transmission
line parameters.
is
If
il
ii
I
201
il
CHAPTER 9i CONCLUSIONS
9.1
SUMMARY OF THE WORK
On many main line electrified railway systems that use single-phase 25kV industrial
frequency supplies, a significant proportion of the locomotives still employ phasecontrolled thyristor converters to feed the DC drive motors. The current drawn by this
type of older locomotives has a low displacement power factor and is also rich in
harmonic content. As a consequence, such systems typically suffer from low system
voltage, loss of average voltage, and harmonic overvoltage.
Low system voltage occurs at the end of a heavily loaded and long feeder section, and
results in excessive power loss in the feeder together with poor locomotive
performance. A separate problem, harmonic overvoltage, arises when the harmonic
current injected by the locomotive load excites one of the resonance modes (typically
around l-2kHz) of the overhead feeder transmission line, causing the feeder voltage
to have peak values significantly above the normal value. This may lead to premature
failures of equipment connected to the system. Finally, rectifier commutation may
result in significant notching in the voltage waveform and this produces a lower
i
(rectified) average value. Since locomotives are essentially rectifier loads, the power
output is proportional to the average voltage rather than the rms voltage. An accurate
measure of this phenomenon is the voltage form factor, which is defined as the ratio
of the rms value of the voltage waveform to the (rectified) average value. An
undistorted sine wave has an ideal form factor of 1.11, whereas the form factor of a
distorted traction feeder voltage can be as high as 1.25. Hence a raised form factor
results in lower available power to the loads.
M
Of the latest generation of power quality equipment based on self-commutated
semiconductor switches, STATCOMs and active power filters appear promising as
solutions to the above mentioned problems in 25kV railway systems. Both of these
use the basic VSI power stages, but are controlled differently for different purposes.
What is needed for railway systems is an equipment that is able to simultaneously
202
CHAPTER 9:
Conclusions
boost the system voltage and mitigate harmonics throughout the entire traction
overhead feeder.
Chapter 3 proceeded to survey STATCOMs and active power filters, and categorised
them according to the compensation objective and control strategy used. It was found
that the STATCOM is predominantly a fundamental frequency equipment, and is used
as a source of rapidly controllable fundamental reactive power for voltage boosting
and other related purposes. On the other hand, whilst many different control strategies
have been proposed for active power filters, they are mainly aimed at compensating
the harmonics and power factor of an identifiable nearby load. These are therefore not
suitable options for traction applications where the physical distance between the load
and the compensator is variable. An active power filter for compensating harmonics
throughout a feeder based on voltage detection is available, but it lacks reactive power
compensation capability and does not allow for selective harmonic compensation. In
short, although existing literature on STATCOMs and active power filters provides a
variety of approaches in controlling reactive power and harmonics, none of them
offers a single solution that exactly matches what is required in a railway system.
Once the limitations of existing STATCOMs and active power filters were identified,
a suitable VSI controller consisting of two major outer loops was proposed:
•
a PI control loop which generates a reactive current reference based on a system
voltage error, similar to that used in STATCOMs;
•
a harmonic compensation loop which generates a harmonic current reference
proportional to the detected voltage harmonic, similar to that used in voltage
detection based "xtive power filters.
This new controller integrates aspects of STATCOMs and active power filters to
produce a new type of single-phase shunt compensator and is referred to as the
Traction Power Quality Conditioner (T-PQC) in this thesis. The next concern was to
develop a suitable harmonic extraction circuit for the harmonic compensation loop, as
most reported active power filter implementations are three-phase and use the
203
5*1
Conclusions
synchronous frame for harmonic extraction. A selective harmonic extraction
nlgoritlun based on resonant filters was proposed, as it is able to achieve the
compensation objective with the least bandwidth requirements. Next, the effective
system harmonic impedances as seen by the locomotive loads at different positions
were evaluated to confirm that the T-PQC is effective in reducing selected harmonics
throughout the entire feeder. The issue of transmission line termination was also
investigated to ascertain that a low impedance termination, as adopted by the
proposed T-PQC, would never cause unexpected harmonic resonance for any realistic
railway lengths, unlike in longer line public power networks and where PFC
capacitors are heavily deployed.
With the groundwork on reactive power and harmonic compensation established,
efforts were made to improve the practicality and robustness and to extend the
capability of the basic T-PQC. A passive high-pass filter was added in parallel with
the VSI to form a hybrid arrangement. The passive filter damps any potential
harmonic overvoltages caused by the locomotives, and at the same tin.e absorbs
switching ripple from the T-PQC. This produces a cleaner pantograph voltage. In
addition, the use of multilevel VSI topologies were examined to further increase the
rating and harmonic performance of the T-PQC. As a result of this investigation, two
new and improved hysteresis current regulation strategies were developed for the
reduced switch-count and cascaded five-level inverter topology respectively.
Finally, the theoretical concepts and developments in this thesis were validated by
extensive simulation studies and experimental work. A 30km feeder section of a
realistic railway system consisting of 10-15MW of total load was used as the basis of
these investigations. Steady-state, dynamic and transient results all proved
encouraging, both in simulation and experiment. Sensitivity studies were also carried
out, which collectively establish the proposed T-PQC as a practical, robust and
general solution to 25kV railway systems.
9.2
CONCLUSIONS
This thesis presents a novel Traction Power Quality Conditioner (T-PQC) which
simultaneously addresses the low system voltage and low average voltage problems in
204
1
CHAPTER 9:
Conclusions
many single-phase 25kV railway systems. The controller for the T-PQC consists of
two outer control loops. The first loop injects a suitable amount of reactive current
based on the rms voltage error, whereas the second loop injects a suitable amount of
third, fifth and seventh harmonic current proportional to the measured voltage. Doing
so boosts the system voltage nearer to the nominal 25kV, and reduces the form factor
closer to the ideal 1.11. A passive high-pass filter to form a hybrid arrangement is also
recommended, allowing harmonic overvoltages to be minimised so that the T-PQC
can be switched at a much lower frequency and produce a cleaner pantograph voltage
at the same time. For additional capacity and harmonic performance, multilevel
inverter topologies are a practical and useful solution, particularly with the new
hysteresis current regulation strategies developed for the reduced and cascaded
topologies respectively.
The outcome of this research work is that with the T-PQC installed, locomotives
connected to the feeder are able to run up to 10% faster because of the improved form
factor, and the feeder system is able to handle increased load (perhaps to meet load
growth demand over several more years) because the voyage regulation has been
improved.
•A
' it
9.3
"I
SUGGESTIONS FOR FURTHER RESEARCH
Although the results presented in this thesis are encouraging, they represent only the
first steps towards commercial adoption, hi particular, it must be demonstrated that
the compensated system can be adequately protected against system faults. In power
systems, including railways systems, fault protection is normally achieved using
relays which act on abnormal current and voltage readings against some pre-set
threshold values. The presence of a T-PQC will have profound effects on the faulted
voltage and current values, and is an area requiring further research. Another related
area requiring attention is the failure modes of multilevel inverters, which is a
surprisingly uncharted area of research despite the enormous interests in multilevel
topologies in recent years. Optimum strategies for controlling a partially failed
multilevel inverter are of practical interest and importance if multilevel inverters are
to be used for the T-PQO.
205
CHAPTER 9:
Conclusions
This thesis has concentrated on the use of a single inverter, and in this case the end of
the feeder section seems to be the optimum location. A possible area for further
investigation would be to determine whether a distributed compensator solution will
produce a more effective and econciflx&l vC iution.
Finally, it would seem logical to explore the possibility of generalising the singlephase work in this thesis to other weak single-phase systems, such as single wire earth
return (SWER) systems. SWER lines are commonly found in rural Australia, and
harmonic distortion and voltage regulation repres-
*al and challenging problems to
be tackled. The T-PQC addresses these probltmrf directly, although the range of
compensated harmonics may need to be increased to minimise voltage THD as
opposed to the form factor.
9.4
CLOSURE
On many 25kV 50/60Hz electrified railway systems, the power quality can be
particularly poor when conventional thyristor locomotives are operating, and this
constrains the amount of power that can be delivered to the locomotives. Present
solutions either require major system upgrades or are ba^u on >lder generations of
power electronics devices with many performance limitations.
This thesis has presented a robust hybrid traction power quality conditioner, based on
the latest generation of self-commutated switches, that simultaneously mitigates low
order voltage harmonic distortion along the feeder, provides rms voltage support and
damps any harmonic overvoltages. The proposed compensator system significantly
increases traction system power transfer capacity with only a relatively minor capital
investment, allowing older thyristor based locomotives and increased traffic levels to
be supported without requiring a complete system upgrade.
206
APPENDIX A: DERIVATIONS OF
IMPORTANT RESULTS
"
m-jrjr.'w-jr.•*•-jr^AT.-ATJ* jr^jr
jrjrjr
fir
Jr. jr i r ^ — . — - . .f.,-.^.
— — . — ~
This appendix presents derivations of important results used in Chapter 4. Section A.I
presents the derivation of
( 4 .5),
the single-phase synchronous frame to stationary
frame filter transformation. Section A.2 presents the derivation of (4.18), the voltage
profile expression for a lossless transmission line terminated by a resistance. Lastly,
Section A 3 proves the assertion made in Subsection 4.2 4 that d\V{pc)\
dRL
is alwavs
y
positive for all values of 0 $ x < L provided L <—.
4
A.I
TRANSFORMATION FROM SYNCHRONOUS TO STATIONARY
FRAME
The single-phase equivalent synchronous reference frame filter is shown in Figure
A.l. The aim here is to express G AC (s), defined as ^fl, in terms of
GDC(S).
From
Figure A. 1,
g\(0 = v(0 cos & t
(A.1)
I
y(t)
I
1
Figure A.I: Single-phase equivalent synchronous reference frame filter
207
APPENDIX A:
Derivations of Important Results
(A.2)
}'\ (0 = /',(/) cos wj
(A.3)
(A.4)
Note that the cos and sin terms in (A.I), (A.2), (A.3) and (A.4) can be expressed i
terms of complex exponentials using the Euler's identities as
COS 0) t = -
(A.5)
eJa°'
sin*yo/ = -
-,
(A.6)
2j
wherey is the imaginary unit.
Applying Laplace transform to (A.I), and using (A.5), gives
= L{gl(t)}
eJ"'' + e~Ja>°'
dt
(A.7)
I
z
Applying LapJace transform to (A.2), and using (A.6), gives
id
APPENDIX A:
Derivations of Important Results
eJ ° — e
(A.8)
-dt
Similarly, (A3) and (A.4) give respectively
(A.9)
(A. 10)
Now, it is clear from Figure A. 1 that
(A.11)
(A.12)
•I
Substituting (A. 11), followed by (A.7), into (A.9) gives
- Ja>o ) G \ (s - J
(s + j(oo
•Ml
1
(s + y£»0) - [V(s) + V(s + jcao
Similarly substituting (A.12), followed by (A.8), into (A.10) gives
- Jc°0)-GDC(s
+ ja)o)G2(s + jaoj\
(A. 14)
209
$»i&<it>MI)^J^ri*^
APPENDIX A:
Derivations of Important Results
Therefore,
- J6>0 ) + GDC (S + JQ)0 )} • V(S)
(A. 15)
and hence the result,
Y(s) G
= AC CO = GDC (s - jo)o) + GDC (s + jco0)
V(s)
A.2
(A.16)
VOLTAGE PROFILE ON A LOSSLESS TRANSMISSION LINE
Consider a simple lossless transmission line of length L terminated in a resistive load
RL at one end and fed by a sinusoidal voltage source Vs of a certain frequency at the
other end, as shown in Figure A.2. It is shown in [149] that the voltage phasor at any
point along the transmission line is given by
V(x) = VL cos J3x + jILRo sin fie
(A. 17)
where position x is measured from the load end, and Ro and p are the transmission
,,*a|
line characteristics as defined in (4.13) and (4.14) respectively. VL and I I are the
voltage and current magnitudes at the load end, and are related by
(A.18)
JC
K
=0
-H
/.e
V(x)
Figure A.2: Lossless transmission line terminated in a resistive load RL
210
APPENDIX A:
Derivations of Important Results
The aim here is to re-express V(x) in (A.17) in terms of the constant source voltage
Vs Z9, rather than the load end voltage and current. Substituting (A.18) into (A.17)
gives
V(x) = ILRL cos fk + jILRo sin J3x
(A.19)
At x = L,
(A.2O)
Equating real and imaginary parts of (A.20) produces
(A.21 a)
(A.21b)
I
Squaring both sides of (A.21) and adding,
v
s
=
pL + K2 sin2 PL)
I
(A.22)
Rearranging (A.22),
(A.23)
Finally, substituting (A.23) into (A. 19),
V(x) = fa+ RO sin2 J3L
L cospx
+ jRo si
(A.24)
The voltage profile (magnitude) along the simple lossless transmission line is thus
given by
'4
211
APPENDIX A:
Derivations of Important Results
(Ro/RLf sin2 fix (A.25)
sin22 fiL
cos2fiL+ R 2 2 sin
which is the result required.
A.3
DERIVATIVE OF | V(X)| WITH RESPECT TO R L
The objective here is to show that the derivative of |V(x)j with respect to RL is always
positive for all values of x in the interval [0, L], provided L<~,
where X is the
wavelength of the voltage. The derivative is given by
d\V{x)\
Ro2\RL\(cos2 fix - cos 2 fiL)
2
fix + R0 ]-W
2
2
(A.26)
- V ) c o s fiL+ R ]
It is obvious that all factors in (A.26) except (cos2 fix - cos2 fih) are always positive.
This means that
dRL
(A.27)
§
(A.28)
I
if and only if
i'Bi
M
Thus to ensure (A.27) is true, we must have
cos2fix> cos2 fiL
(A.29)
for every x in the interval [0,L]. From Figure A.3, this can only be true if
5
212
Derivations ofImportantResults
APPENDIX A:
Figure A.3: Graph of cos2 9
(A.30)
But since for lossless transmission line [149]
(A.31)
and substituting into (A.30) gives
(A.32)
d\v(x)\
which is the necessary and sufficient condition for —'
- to be positive for all
dRL
0<x<L.
213
APPENDIXB: MATLAB M-FlLES
'
*
•
*
*
*
*
.
*
•
*
•
*
*
*
•
*
•
'
*
.
*
*
•
*
*
*
•
*
*
*
•
*
*
*
*
*
*
*
*
-
*
•
*
*
*
*
*
*
*
.
*
*
•
•
*
.
*
*
*
.
*
*
•
*
*
*
*
*
•
*
.
*
•
*
*
.
*
*
.
•
*
•
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*jrr.r*
This appendix contains listings of m-files written in MATLAB used to generate some
of the figures in Chapter 4. These files are:
•
'IMP6.M' - File used to calculate the system impedance as a function of
frequency, with locomotive position as parameter (Figure 4.7 and Figure 5.4);
•
'GAIN2.M' - File used to calculate the system impedance as a function of
locomotive position, with frequency as parameter (Figures 4.8 ~ 4.10);
•
'STANDWAVE.M' - File used to calculate the voltage profile of a lossless
transmission line with different resistive terminations based on (4.18) (Figure
4.12);
•
'HARPROP.M' - File used to calculate harmonic voltage profiles along the entire
m
feeder section due to a single harmonic current source (Figures 4.13 ~ 4.15).
1
B.I
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
JSTING OF 1MP6.M'
File name: imp6.m
Creator: Pee-Chin Tan
This program calculates the harmonic voltage at the point of
injected harmonic current source using distributed parameter model.
It is assumed a harmonic current source is located at position LI
from the origin. Source impedance at origin is Zs (Ls // Rs) and
an equivalent impedance of Zaf (representing APF) is located
at the end of the feeder of length LT.
This program calculates and plots the magnitude of the resulting
voltage at the current source as a function of harmonic
frequency. If the injected current has amplitude of 1, then this
effectively gives the system impedance at the point of current source
This program has same function as 'imp5.m'
However, it calculates the impedance at x=Ll directly using
expression for impedances in hyperbolic functions
LI = 30; %location of harmonic current source in km
LT = 30;
%total length of feeder in km
•a
%System parameters
R = 0.169; % ohm/km
L = 1.38e-3; % H/km
C = 0.011e-6; % F/km
G = 0;
Ls = 27.le-3;
%source inductance in H
Rs = 1000;
%oource resistance in ohms (paralle)
214
APPENDIX B:
MATLAB M-Files
%2nd order Passive damping filter parameters
Rp = 344;
Cp = 0.84e-6;
Jjp = 385e-3;
%frequency range for plot
f = [10:1:10000];
w = 2*pi*f;
%APF transfer function
K = -0.2;
we = 5; %in rad/s
num3 = '" we 0] ;
den' - [1 2*wc (2*pi*150)~2];
sys = tf(num3,den3);
nuraS = [2*wc 0] ,den5 = [1 2*wc (2*pi*250) A2] ;
sys5 = tf(num5,den5),
num7 = [2*wc 0 ] ;
den7 = [1 2*wc (2*pi*350) *2] ;
sys7 = tf(nura7,den7);
%lst order low pass (anti-aliasing) filter used in DSP
numlp = [1];
denlp = [5e-5 1 ] ;
syslp =tf(numlp,denlp);
syst = -K * (sys3 + sys5 + sys7 ) ;
systfr = freqresp(syst, w ) ;
systfr = systfr (:).',Zapf = 1 ./ systfr ;
%2nd order RLC damping filter
numpf = [Rp*Lp*Cp Lp Rp];
denpf = [Lp*Cp Rp*Cp 0];
syspf = tf(numpf,denpf);
syspffr = freqresp(syspf,w);
Zpf = syspffr(:).';
%Combine APF and PPF, ie. to get total TF for hybrid compensator
Zaf = (Zapf .* Zpf) ./ (Zapf + Zpf); %parallel connection
%Zaf = Zapf;
%Zaf=Zpf;
%Zaf=1000000;
%Distributed line model calculation
Zo = sqrt( (R+j*w*L) ./ (G+j*w*C)
gm = sqrt( (R+j*w*L) .* (G+j*w*C)
%Zsl = l/(j*w*1.8e-5)+j*w*0.092;
Zs = j*w*Ls*Rs ./ (j*w*Ls+Rs);
%ZS = Zsl * Zs2 /(Zsl + Zs2);
%power factor correction arm
Zl = Zo .* (Zs .* cosh(gm*Ll)+Zo .* sinh(gm*Ll)) ./ (Zo .* cosh(gr,i*Ll)+Zs .*
sinh(gm*Ll) ) ;
Z2 = Zo .* (Zaf .* cosh(gm*(LT-Ll))+Zo .* sinhtgm*(LT-L1))) ./ (Zc .* cosh(gm*(LTLl))+Zaf .* sinh(gm*(LT-Ll)));
ZT = Zl .* Z2 ./(Z1+Z2);
r-4
semilogx(f,20*loglO(abs(ZT)));
B.2
LISTING OF 'GAIN2.M'
% File name: gain2.m
% Creator: Pee-Chin Tan
% This program has same function as 'gain.m1
% However, it calculates using the distributed parameter line model
% rather than approximating with longitudint. inductance only
215
APPENDIX B:
Ll = rO:30];
LT = 30;
MATLAB M-Files
%total length of feeder in km
%System parameters
R = 0.169; % ohm/km
L = 1.38e-3; % H/km
C = 0.011e-G; % F/km
G = 0;
Ls = 27.1e-3;
%source inductance in H
Rs = 1000;
%source resistance in ohms (paralle)
%2nd
Rp =
Cp =
Lp =
order Passive damping filter parameters
3'4;
0.84e-6;
200e-3;
%evaluate at only one frequency
w = 2*pi*3S0;
%APF transfer function
K = -0.2;
we = 5; %in r a d / s
num3 * [2*wc 0] ;
den3 = [1 2*wc ( 2 * p i * 1 5 0 ) * 2 ] ;
sys3 = tf(num3,den3);
num5 = [2*wc 0] ;
denS = [1 2*wc (2*pi*250)"2};
sysS = tf(numS,den5);
num7 = [2*wc 0] ;
den7 = [1 2*wc (2*pi*350)"2];
sys7 = tf(num7,den7);
%lst order low pass (anti-aliasing) filter used in DSP
numlp = [1] ;
denlp = [5e-5 1 ] ;
syslp =tf(numlp,denlp);
syst =
systfr
systfr
Zapf =
-K * (sys3 + sys5 + sys7 ) ;
= freqresp(syst, w ) ;
= systfr(:).';
1 ./ systfr ;
%2nd order RLC damping filter
numpf = [Rp*Lp*Cp Lp Rp] ;
denpf = [Lp*Cp Rp*Cp 0 ] ;
syspf = tf(numpf,denpf);
syspffr = freqresp(syspf,w);
Zpf = syspffr(:).;;
III
%Combine APF and PPF, ie. to get total TF for hybrid compensator
%Zaf •• -Zapf .* Zpf) ./ (Zapf + Zpf); %parallel connection
Za *
" ipf;
%Z ir "pf;
%Zaf=1000000;
%Distributed line model calculation
Zo = sqrt( (R+j*w*L) / (G+j*w*C) ) ;
gm = sqrt( (R+j*w*L) * (G+j*w*C) ) ;
%Zsl = l/(j*w*1.8e-5)+j*w*0.092;
Zs = j*w*Ls*Rs / (j*w*Ls+Rs),
%Zs = Zsl * Zs2 /(ZBl + Zs2);
%power factor correction arm
Zl = Zo * (Zs * cosh(gm*Ll)+Zo * sinh(gm*Ll)) ./ (Zo * cosh(gm*Ll)+Zs * sinh(gm*Ll));
Z2 = Zo * (Zaf * cosh (gin* (LT-Ll) )+Zo * sinhtgm* (LT-L1))) ./ (Zo * cosh (gm* (LT-L1)) +Zaf
* sinh(gm*(LT-Ll)));
ZT = Zl .* Z2 ./(Z1+Z2);
plot(Ll,abs(ZT));
216
APPENDIX B:
B.3
%
%
%
%
%
MATLAB M-Files
LISTING OF 'STAMDWAVE.M'
File name: atandwave.m
Creator: Pee-Chin Tan
This program calculates the standing wave voltage profile along
a simple lossless transmission line terminated by different resistances
hold off
b = 1;
Ro = 1;
Rl = Ie6 * Ro;
L = 7;
2 = [0:0.01:L];
VL = Rl / (sqrt((Rl*cos(b*L))A2+(Ro*sin(b*L) ) A2)) ;
V=VL*sqrt((cos(b*z)).A2+((Ro/Rl)"2) * (sin(b*z)).A2) ;
plot(z,V);
axis([0 L 0 max(V')*l.2]);
hold
Rl = le-6 * Ro;
VL = Rl / (sqrt ((Rl*cos(b*L)) A 2+(Ro*sin(b*D) A2)) ;
V=VL*sqrt((cos(b*z)).A2+((Ro/Rl)"2)*(sin(b*z)).A2) ;
plot(2,V);
Rl = Ro;
VL = Rl / (sqrt((Rl*cos(b*L))A2+(Ro*sin(b*L))A2));
V=VL*sqrt((cos(b*z)).A2+((Ro/Rl)A2)*(sin(b*z)).A2);
pl0t(2,V);
Rl = 2 * RO;
VL = Rl / (sqrt((Rl*cos(b*Ij)) A 2+(Ro*sin(b*D) A2)) ;
V=VL*sqrt ((cos(b*z) ) . A 2+( (K.O/R1) A 2) * (sin(b*z)) . A 2) ;
plot(z,V);
Rl = 0.5 * Ro;
VL = Rl / (sqrt((Rl*cos(b*L))A2+(Ro*sin(b*L))*2));
V=VL*sqrt((cos(b*z)).A2+((Ro/Rl)A2)*(sin(b*z)).A2);
plot(z.V);
B.4
%
%
%
%
%
%
%
%
%
%
%
LISTING OF 'HARPROP.M'
File name: harprop.m
Creator: Pee-Chin Tan
This program performs harmonic study on a transmission line using
distributed parameter model.
It is assumed a harmonic current source is located at position LI
from the origin. Source impedance at origin is Zs (Ls // Rs) and
an equivalent impedance of Zaf (representing APF) is located
at the end of the feeder of length LT.
This program calculates and plots the magnitude of the resulting
voltage along the entire length of feeder at some chosen freqeuncy.
w = 2*pi*3S0; %frequsncy to study
LI = 10; %location of harmonic current source in km
LT = 30;
%total length of feeder in km
ilh = 1; %harmonic current source phasor
dx = 1;
%Ccilculation interval in km
R = 0 .169; % ohm/km
L = 1 .38e-3; % H/km
C = 0 .Olle-6; % F/km
G = 0
Ls = 27.1e-3;
Rs = 1000;
Zo = sqrt( (R+j*w*L) / (G+j*w*C)
gm = sqrt( (R+j*w*L) * (G+j*w*C)
%Zsl = l/(j*w*1.8e-5)+j*w*0.092;
Zs = j*w*Ls*Rs / (j*w*Ls+Rs);
%power factor correction arm
217
APPENDIX B:
MATLAB M-Files
%Zs = Zsl * Zs2 /(Zsl + Zs2);
Zaf = 5;
Zaf = Ie6 ;
%Zaf = 350;
clear V;
clear Vs;
clear x;
vl
v2
v3
v4
vS
v6
= (Zs-Zo)/(Zo+Zs);
= (Zo+Zaf)/(Zaf-Zo);
= exp(gm*Ll);
= exp(gm*LT);
= exp(2*gm*Ll);
= exp(2*gm*LT);
v7 = (v5 + v6 * V2) / (vS + vl) ;
v8 = (v7 * (vl - vS)) - (v6 * v2 - v5);
B2 = Zo * v3 * ilh / v8;
ril = B2 * v7;
Al = Bl * vl;
A2 = B2 * v6 * V2;
X = [0:dx:LT];
no_pts = floor (LT / dx) + 1 ;
% no of points calculated
for k = l:no_pts
if (x(k) <= LI)
V(k) = Al * exp(-gm*x(k)) + Bl * exp(gm*x(k));
else
V(k) = A2 * exp(-gm*x(k)) + B2 • exp(gm*x(k));
end
end
%simplified calculations using longitudinal inductance only
%il = ilh* ( (Zaf + j*w*L*(LT-Ll)) / (Zs + Zaf + j*w*L*LT) )
%i2 = ilh* ( (Zs + j*w*L*Ll) / (Zs + Zaf + j*w*L*LT) ) ;
%for k = l:no_pts
%
if (x(k) <= LI)
%
Vs(k) = -il * (Zs + j*w*L*x(k));
%
else
%
Vs(k) = -(Zs + j*w*L*Ll) * il + i2*j*w*L*(x(k)-LI);
%
end
%end
%err = abs(abs(V)-abs(Vs))./aba(V) * 100;
plot(x,abs(V)) ;
%plot(x.abs(V) , x, abs(Vs));
%plot(x.err)
ill
218
APPENDIX C: PSCAD CUSTOM MODEL
FORTRAN SOURCE CODES
This appendix contains the FORTRAN source codes written for the PSCAD custom
models used in the simulation investigations. The two files listed are:
1
•
'RMSAVG.F' - File contains routines for calculating rms and average values
respectively based on the running window algorithm described in Chapter 6;
1
»
'DIGCTRL5.F' - File contains routines for DC bus control, harmonic
compensation and reactive power compensation.
C.I
LISTING OF 'RMSAVG.F'
! File name: rmsavg.f
! Creator: Pee-Chin Tan
i
Subroutine Rms(In, freq, N, RMS_out, Navg)
! Include Files
INCLUDE "nd.h1
INCLUDE 'emtstor.h'
INCLUDE 'sl.h'
REAL In, RMS_OUt
INTEGER MY_NSTO1'I, MY_NSTORF, Count, N, I, New, Last, freq, Navg, Newsum,
•n
I
Lastsum
MY_NSTORF = NSTORF
NSTORF = NSTORF + N + 2 + Navg + 2
MY_NSTORI = NSTORI
NSTORI = NSTORI + S
!N = no. of samples per fundamental cycle
!freq = fundamental frequency
!Number of simulation time step per sampling period
Count = nint( 1/(N*freq*delt) )
!Initialisation at t = 0
If (Timezero) then
STORI(MY NSTORI) = Count
!Counter, initialise to sample at t=0
Do 10 I = 1, (N+l)
STORF(MY NSTORF + I) = 0
!(N+l) storage for N sq samples
10
Do 20 I = (N+2), (N+2+Navg)
STORF(MY_NSTORF + I) = 0
!(Navg+1) storage for Navg rms samples
20
!Sum of N squares
STORF(MY_NSTORF)
!Sum of Navg rms
STORF(MY_NSTORF + N + 2 + Navg + 1) = 0
STORI(MY_NSTORI + 1) = 1
STORI(MY_NSTORI + 2) = 2
219
APPENDIX C:
PSCAD Custom Model FORTRAN Source Codes
SPORI(MY_NSTORI + 3) = N+2
OTORKMY NSTORI + 4) = N+3
Endif
If (STORI(MY_NSTORI) .eq. count) then
STORI(MY_NSTORI) = 0
New = STORI(MY_NSTORI + 1)
Last = STORI(MY_NSTORI + 2)
Newsura = STORI(MY_NSTORI + 3)
Lastsum = STORI(MY_NSTORI + 4)
lAlgorithms for processing sum of squares
STORF(MY_NSTORF + New) = In**2
STORF(MY_NSTORF) = STORF(MY_NSTORF) + STORF(MYJJSTORF + New)
STORF(MY_NSTORF + Last)
If (New .It. (N+l)) then
New = New + 1
Else
New = 1
Endif
If (Last .It. (N+D) then
Last = Last + 1
Else
Last = 1
Endif
lAlgorithms for processing sum of rms for averaging
!Perform moving window averaging of last Navg samples
!Navg = 1 for no averaging
STORF(MY_NSTORF + Newsum) = sqrt(STORF(MY_NSTORF)/N)
STORF(MYJJSTORF + N + 2 + Navg + 1) = STORF(MYJJSTORF + N + 2 + Navg +
1) + STORF(MYJJSTORF + Newsum) - STORF(MYJJSTORF + Lastsum)
If (Newsum .It. (N+2+Navg)) then
Newsura = Newsum + 1
Else
Newsum = N+2
Endif
If (Lastsum .It. (N+2+Navg)) then
Lastsum = Lastsum + 1
Else
Lastsum = N+2
Endif
!store values
STORI(MY_NSTORI + 1) = New
STORI(MYJJSTORI + 2) = Last
STORI(MYJJSTORI + 3) = Newsum
STORI(MYJJSTORI + 4) = Lastsum
Endif
STORI(MY_NSTORI) = STORI(MY_NSTORI) + 1
RMS_OUt = STORF(MYJJSTORF + N + 2 + Navg + 1 ) / Navg
Return
End
Subroutine Avgdn, frtq, N, Avg_out, Navg)
! Include Files
:i
220
E^WK^^^
APPENDIX C:
PSCAD Custom Model FORTRAN Source Codes
INCLUDE 'nd.h'
INCLUDE 'emtstor.h1
INCLUDE 'sl.h'
REAL In, AVG_out
INTEGER MY_NSTORI, MY_NSTORF, Count, N, I, New, Last, freq, Navg, Newsum,
Lastsum
MY_NSTORF = NSTORF
NSTORF = NSTORF + N + 2
floating storage used
+ Navg + 2
! (N+2) is the total no. of
MYJJSTORI = NSTORI
NSTORI = NSTORI + 5
!N = no. of samples per fundamental cycle
!freg = fundamental frequency
JNumber of simulation time step per sampling period
Count = nint( 1/(N*freg*delt) )
!Initialisation at t = 0
If (Timezero) then
STORKMY NSTORI)
Count
10
DO 10 I = 1, (N+l)
STORF(MY_NSTORF + I) = 0
20
Do 20 I = (N+2), (N+2+Navg)
STORF(MY NSTORF + I) = 0
!Counter, initialise to sample at t=0
! (Navg+1) stor?-;e for Navg avg samples
STORF(MY_NST0RF) = 0
STORF (MY_NSTORF 4- N + 2 + Navg + 1) = 0
!Sum of abs values
!Sum of Navg avg
STORI(MY_NSTORI + 1) = 1
STORI(MY_NSTORI + 2) = 2
STORI(MY_NSTORI + 3) = N+2
STORKMY NSTORI + 4) = N+3
Endif
If (STORI(MY_NST0RI) .eq. count) then
STORI(MY_NSTORI) = 0
New = STORI(MY_NSTORI + 1)
Last = STORI(MY_NST0RI + 2)
Newsum = STORI(MY_NSTORI + 3 )
Lastsum = STORI(MY_NSTORI + 4)
!Algorithms for processing abs values
STORF(MY_NSTORF + New) = abs(In)
STORF(MY_NSTORF) = STORF(MY_NSTORF) + STORF(MY_NSTORF + New)
STORF(MY_NSTORF + Last)
If (New .It. (N+l)) then
New = New + 1
Else
New = 1
Endif
If (Last .It. (N+l)) then
Last = Last + 1
Else
Last = 1
Endif
\\
!Algorithms for processing sum of avgs
!Perform moving window averaging of last Navg samples
JNavg = 1 for no averaging
STORF(MY_NSTORF + Newsum) = STORF(MY_NSTORF)/N
STORF(MY_NSTORF + N + 2 + Navg + 1) = STORF(MY_NST0RF + N + 2 + Navg +
1) + STORF(MY_NST0RF + Newsum) - STORF(MY_NSTORF + Lastsum)
221
APPENDIX C:
PSCAD Custom Model FORTRAN Source Codes
If (Newsum .It. (N+2+Navg)) then
Newsum = Newsum + 1
Else
Newsum = N+2
Endif
If (Lastsum .It. (N+2+Navg)) then
Lastsum = Lastsum + 1
Else
Lastsum = N+2
Endif
I
!Store values
STORI(MY_NSTORI
STORI(MY_NSTORI
STORI(MY_NSTORI
STORI(MY_NSTOR1
+1) =
4 2)=
+3) =
+ 4) =
New
Last
Newsum
Lastsum
Endif
STORI(MY_NSTORI) = STORI(MY_NSTORI) + 1
AVG_out = STORF(MY_NSTORF + N + 2 + Navg + 1) / Navg
Return
End
C.2
LISTING OF 'DIGCTRL5.F'
! File name: digctrlS.f
! Creator: Pee-Chin Tan
! DC bus control routine, called by DC bus controller block
Subroutine DigPKDcref, Vdc, Out, Sinln, DACOut)
! Include Files
INCLUDE 'nd.h'
INCLUDE 'emtstor.h'
INCLUDE 'sl.h1
REAL
Dcref, Vdc, Out, Sinln, DACOut
INTEGER MY_NSTORI, Count, Vdc_err, DACIn, Vdc_err_prop
MY_NSTORI = NSTORI
NSTORI = NSTORI + 1 0
(Digital Controller interrupt sampling period = 0.0001s = lOOus (2*5kHz = 10kHz)
(Number of simulation time step per sampling period
Count = nint(0.0001/delt)
(Initialisation at t = 0
If (Timezero) then
STORI(MY_NSTORI) = Count
STORI (MYJJSTORI + 1) = 1 0
interrupt
STORI(MY_NSTORI +
STORI(MY_NSTORI +
STORI(MYJJSTORI +
STORI<MY_NSTORI +
STORI(MY_NSTORI +
STORI(MY_NSTORI +
Vdc_err_prop = 0
3)
4)
5)
6)
7)
8)
=
=
=
=
=
=
0
0
0
0
0
0
II
(Counter, initialise to sample at t=0
•update PI controller every 10th
!(i) y2 = Vdc_sum
!(i) output
(Sine input
! (i-1) Vdc
!Vdc low pass filtered
Endif
:i
(Only updates Sine output every interrupt, period
222
APPENDIX C:
PSCAD Custom Model FORTRAN Source Codes
If (STORI(MY_NSTORI) .eq. count) then
STORI(MY_NSTORI) * 0
STORI(MY_NSTORI + 5) = nint(Sinln * 32767)
IDC Bus PI controller is updated every 10th cycle of interrupt
JController effective running at lOOOHz or sampling period of 0.001s
If (STORI(M¥_NSTORI + 1) .eq. 10) then
STORI(MY NSTORI + 1) = 0
!reset counter
!STORI(MYJJSTORI + 7) = floor( (993* nint(Vdc) * 64 + 993 *
STORI(MY_NSTORI + 6 ) * 64 + 30782 * STORI(MYJJSTORI + 7) + 16384) / 32768.0 )
!Vdc_err = STORI(MY_NSTORI + 7) - 64* nint(Dcref)
Vdc_err = 64* (nint(Vdc) - nint(Dcref))
If (Vdc_err .ge. 1280) then
Vdc_err = 1280
Else if (Vdc_err .le. -1280) then
Vdc err = -1280
Endif
STORI(MY NSTORI + 3) =
(Vdc err/8)+ STORI(MY NSTORI + 3)
If ( STORI(MY_NSTORI + 3) .gt. 5000 ) then
STORI(MY_NST0RI ^ 3) = 5000
Else if ( STORI(MY_NSTORI + 3) .It. -5000 ) then
STORI(MY_NST0RI + 3) = -5000
Endif
!If (iabs(Vdc_err) .gt. 1) then
!
STORI(MY NSTORI + 4) = 200 * Vdc err + STORI(MY NSTORI +
3)
iElse
STORI(MY NSTORI + 4) = Vdc err +
STORI(MY NSTORI + 3)
/2
!Endif
!If ( (Vdc_err .gt. 250) .or. (Vdc_err .It. -250) ) then
!
Vdc_err_prop = Vdc_err
!Endif
STORI(MY_NST0RI + 4 ) = (16 * Vdc_err) + STORI(MY_NST0RI + 3)
!STORI(MY NSTORI + 4) = floor( STORI(MY NSTORI + 4) * 28924 /
4096.0 + 0.5)
If ( STORI(MY_NSTORI + 4) .gt. 32000 ) then
STORI(MY_NSTORI + 4) = 320O0
Else if ( STORI(MY_NSTORI + 4 ) .It. -32000 ) then
STORI (MY_NSTOKI + 4) = -32000
Endif
STORI(MY NSTORI + 6) = nint(Vdc)
• store Vdc
Endif
If ( (Vdc_err .It. 100) .and. (Vdc_err .gt. -100) ) then
If ( abs(STORI(MY NSTORI +5)) .It. 500) then
STORI(MY_NSTORI + 8) = STORI(MY_NSTORI + 4)
Endif
Else
STORI(MY_NSTORI + 8) = STORI(MY_NSTORI + 4)
Endif
STORI(MY_NSTORI + 1) = STORI(MY_NSTORI + 1) + 1
Endif
STORI(MY_NSTORI) = STORI(MY_NSTORI) + 1
Out = STORI(MY_NSTORI + 4)
DACIn = floor( (Out * STORI(MY_NSTORI + 5)) / 524288.0 )
!Integer input to
DAC
223
APPENDIX C:
PSCAD Custom Model FORTRAN Source Codes
DACOut = DACIn * 10.0 / 2048.0
output from DAC
Out = STORI(MY_NSTORI + 8)
JReal
Return
End
•***
IHarmonic compensation routine, called by 'Digital Controller' block
i * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Subroutine DigCtrl(Vaclreal, Switch, DACOut, Out)
! Include Files
INCLUDE 'nd.h'
INCLUDE 'emtstor.h'
INCLUDE 'sl.h'
REAL
Switch, DACOut, Vaclreal, Out
INTEGER Vacl, Vacloldl, Vaclold2, wloldl, w2oldl, zloldl, z2oldl, hloldl,
h2oldl
INTEGER
INTEGER
INTEGER
INTEGER
y3, y5, y7, ytoldl, ytold2, w3oldl, w4oldl, ybs, yt, DACIn
yll, z3oldl, z4oldl, h3oldl, h4oldl
wl, w2, w3, w4, zl, %2, z3, z4, hi, h2, h3, h4
MY NSTORI, Count
MY_NSTORI = NSTORI
NSTORI = NSTORI + 2 0
IDigital Controller interrupt sampling period = 0.0001s = lOOus (2*5kHz = 10kHz)
iNumber of simulation time step per sampling period
Count = nint(0.0001/delt)
!Initialisation at t = 0
If (Timezero) then
STORI(MY_NSTORI + 1) = 0
STORI(MY_NSTORI + 2) = 0
STORI(MY NSTORI + 3) = 1
STORI(MY_NSTORI + 4) = 0
STORI(MY_NSTORI + 5) = 0
STORI(MY NSTORI + 6) = 0
STORI(MY_NSTORI + 7) = 0
STORI(MY_NSTORI + 8) = 0
STORI(MY NSTORI + 9) = 0
STORI(MY_NSTORI + 10) = 0
STORI(MY_NSTORI + I D = 0
STORI(MY_NSTORI + 12) = 0
STORI (MY]]NSTORI + 13) = 0
STORI(MY_NSTORI + 14) = 0
STORI (MY]]NSTORI + 15) = 0
STORI(MY NSTORI + 16) a 0
STORI(MY_NSTORI + 17) = 0
STORI(MY~NSTORI + 18) = 0
STORI(MY~NSTORI + 19) = 0
STORI(MY NSTORI) = Count
! (i-1)
! (i-2)
!
!
!
!
!
input
input
j
!
!
j
!
!
!
!
j
I
!
j
!Counter, in
End if
If (Switch .ge. 0.5) then
If (STORI(MY_NSTORI) -eq. count) then
STORI(MY_NSTORI) = 0
Vacloldl
Vaclold2
w2oldl =
wloldl =
z2oldl =
zloldl =
h2oldl =
= STORI(MY_NSTORI
= STORI(MY_NSTORI
STORI(MY NSTORI +
STORI(MY_NSTORI +
STORI(MY_NSTORI +
STORI(MY~NSTORI +
STORI(MY NSTORI +
+ 1)
+ 2)
3)
4)
5)
6)
7)
224
APPENDIX C:
PSCAB Custom Model FORTRAN Source Codes
hloldl
ytoldl
ytold2
w4oldl
w3oldl
z4oldl
z3oldl
h4oldJ
h3oldl
STORI(MY NSTORI
STORI (MY"NSTORI
STORI (MY*NSTORI
STORI (MY_ NSTORI
STORI (MY]NSTORI
STORI (MY]NSTORI
STORI (MY]NSTORI
STORI (MY" NSTORI
STORI (MY' NSTORI
+
+
+
+
8)
9)
10)
11)
12)
13)
14)
16)
15)
IVacl = nint(Vaclreal)
Vacl = isha( -9039 * nint (Vaclreal) + 256, -3)
13rd harmonic resonant filter, Wcut = 15 rad/s, d = 1/16
w4
w2
y3
y3
w3
w3
Wl
wl
=
=
=
=
=
=
=
=
(w3oldl / 16) + w4oldl
(wloldl / 16)+ w2oldl
3136 * Vacl
(isha(y3 + 1048576, -21) + W4)
100364 * Vacl - 397750 * y3
isha(w3 + 1048576, -21) + w2
-2379089 * y3
isha(wl + 524288, -20)
II
!5th
z4 =
Z2 =
y5 =
yS =
z3 =
z3 =
zl =
zl =
harmonic resonant filter, Wcut = 15 rad/s, d = 1/16
(z3oldl / 16) + z4oldl
(zloldl / 16) + Z2oldl
3128 * Vacl
(isha(y5 + 1048576, -21) + z4)
100100 * Vacl - 925089 * y5
isha(z3 + 1048576, -21) + z2
-6599913 * y5
isha(zl + 524288, -20)
!7th
h4 =
h2 =
y7 =
y7 =
h3 =
h3 =
hi =
hi =
harmonic resonant filter, Wcut
(h3oldl / 16) + h4oldl
(hloldl / 16) + h2oldl
3116 * Vacl
(isha(y7 + 1048576, -21) + h4)
99706 * Vacl - 1713503 * y7
isha(h3 + 1048576, -21) + h2
-12910380 * y7
ishafhl + 524288, -20)
yt =
!yt
y3
y3
y5
y5
IS rad/s, d = 1/16
y7 + i3ha(950 * Vacl + 32768, -16)
y7
!update and store values for use in next interrupt
2)
Vacloldl
STORI(MY_NSTORI
1) = Vacl
STORI(MY_NSTORI
4) = wl
STORI(MY_NSTORI
3) = w2
STORI(MY_NST0RI
6) = si
STORI(MY_NSTORI
5) = z2
STORI(MY_NSTORI
STORI(MY_NSTORI
8) = hi
STORI(MY_NSTORI
7) = h2
STORI(MY_NSTOHX
10) = ytoldi
STORI(MY_NSTORI
9) =
STORI(MY_NSTORI
12)
w3
STORI(MY_NSTORI
11)
W4
STORI(MY_NSTORI + 14) = z3
STORI(MYJJSTORI + 13) = z4
STORI(MY_NSTORI + 15) = h3
STORI(MY~NSTORI + 16) = h4
STORI(MY NSTORI + 17) =
STORI(MY_NSTORI + 1 8 ) = y5
STORI(MY_NSTORI + 19) = y7
Endif
STORI(MY NSTORI) = STORI(MY_NSTORI) + 1
225
APPENDIX C:
PSCAD Custom Model FORTRAN Source Codes
2 * STORKMY NSTORI + 9)
IInteger
input to DAC
DACOut = DACIn * 10.0 / 204 8.0
output from DAC
Out = STORI(MY NSTCRI + 9)
Else
IReal
lharmonic compensation switched off
DACOut = 0
End if
!***********************•******•**************************•*#********************
!Reactive power compensation routine, called by 'Reactive Power Controller' Block
j***********«*t************************4r* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Subroutine RPCont(Dcref, Vaclreal, Switch, Sinln, Out, DACOut)
! Include Files
INCLUDE 'nd.h'
INCLUDE 'emtstor.h'
INCLUDE 'sl.h'
REAL
Dcref, Vaclreal, Switch, Out, Sinln, DACOut
INTEGER MY_NSTORI, Count, Vac_err, DACIn, Vac_sum, I, Vacl
INTEGER Next_pt, Oldestjpt, Sumsq, Nextsq, Oldestsq, yrp, index
MYJJSTORI = NSTORI
NSTORI = NSTORI + 1234
iDigital Controller interrupt sampling period = 0.0001s = ICOus (2*5kHz = 10kHz)
!Number of simulation time step per sampling period
Count = nint(0.0001/delt)
!Initialisation at t = 0
If (Timezero) then
STORI(MY_NSTORI) = Count
!Counter, initialise to sample at t=0
STORI(MY_NST0RI + 1) = 4
!Pointer to next location
STORI(MY_NSTORI + 2 ) = 5
!Pointer to oldest location
STORI(MYJJSTORI + 3) = 0
!Sum of volt squares
Do 10 I = 4, 204
!201 Storage for 200 volt squares,
RMS calculation
10
STORI(MY_NST0RI + I) = 0
STORI(MY_NSTORI + 205) = 0
!sample for sine wave input
STORI(MY_NSTORI + 206) = 0
lyrp
STORI (MYJJSTORI + 207) = 0
!Vac_sum
STORI(MYJJSTORI + 208 > = °
!Vac_err
Do 20 I = 209, 1233
11024 storage for sqrt look up table
STORI(MYJJSTORI + I) = nint(sqrt( (1-209)*1S384 + 3.7e6 ) )
20
Endif
I Only updates Sine output every interrupt period
If (Switch .ge. 0.5) then
If (STORI(MYJJSTORI) .eq. count) then
STORI(MY_NSTORI) = 0
STORI(MY_NSTORI + 205) = nint(Sinln * 32767)
Next_pt = STORI(MY_NSTORI + 1)
Oldest_pt = STORI(MY_NST0RI + 2)
Sumsq = STORI(MY_NSTORI + 3)
yrp = STORI(MY_NSTORI + 206)
Vac_sum = STORI(MY_NSTORI +207)
!determine latest pointer locations
If (Next^pt .It. 204) then
Next_pt = Next_pt + 1
Else
Next_pt = 4
Endif
ii
226
APPENDIX C:
PSCAD Custom Model FORTRAN Source Codes
If (Oldest_pt .It. 204) then
01dest_pt = Oldestjpt + 1
Else
Oldestjpt = 4
Endif
Oldestsq = STORI(MYJJSTORI + Oldest_pt)
!'RMS' calculation
Vacl = nint(Vaclreal)
Nextsq = Vacl**2
Sumsg = Sumsq + Nextsg - OMestsg
index = isha(sumsq-3700000 + 8192, -14)
if (index .It. 0) then
index = 0
Else if (index .gt. 1024) then
inctex = 1024
Endif
Jcalculate index to use sqrt look up table
index = index + 209
Vac_err =
nint(aqrt(200.0)*1.4791111*DCref) - STORIIMYJJSTORI +
index)
!Vac_err = nint (sqrt (200. 0) *1.4791111*DCref) - sqrt (Sutnsq*! .0)
!limits error signal
If (Vac_err .ge. 1050) then
~Vac_err = 1050
Else if (Vac_err .le. -1050) then
Vac_err = -1050
Endif
i1
!PI regulator
Vac sum = isha(Vac err+16, -5) + Vac sum
If ( Vac_sum .gt. 7520 ) then
Vac_sum = 7520
Else if ( Vac_sum .It. -7520 ) then
Vao_sum = -7520
Endif
yrp = Vac_sum + isha(47*Vac_err + 1 , -1)
If ( yrp .gt. 7520 ) then
yrp = 7520
Else if ( yrp .It. -7520 ) then
yrp = -7520
Endif
yrp = yrp * 2
!storing values
STORI(MY_NSTORI
STORI(MYJJSTORI
STORI(MY_NSTORI
STORI(MYJJSTORI
STORI(MY_NSTORI
STORI(MY_NSTORI
STORI(MYJJSTORI
for next function call
+ 3) = Sumsq
+ Next_pt) = Nextsq
+ 1) = Nextjpt
+ 2) = Oldest_pt
+ 206) = yrp
+ 207) = Vac_sum
+ 208) = Vac_err
Endif
STORI{MYJJSTORI) = STORI(MYJJSTORI) + 1
Out - STORI(MYJJSTORI +206)
DACIn = floor! (Out * STORI(MYJJSTORI + 205)) / 524288.0 )
llnteger
input to DAC
227
APPENDIX C:
DACOut = DACIn * 10.0 / 2048.0
I Real output from DAC
Else
I Reactive power compenaation awitched off
Out a STORI(MY_KSTORI + 206)
DACOut = 0
Endif
Cat = STORI(MY NSTORI + 206)
lOut =. sqrt(STORI(MY_NSTORI + 3)/200.0)/I.4791111
Return
End
i
228
APPENDIX C:
DACOut = DACIn * 10.0 / 2048.0
IReal output from DAC
Else
!Reactive power compensation switched off
Out = STORI(MY NSTORI +206)
DACOut = 0
~
Endif
Cut = STORI(MY_NSTORI + 20G)
!Out = sqrt(STORI(MY_NSTORI + 3J/2O0.0)/I.4791111
Return
End
1
m
m
228
APPENDIX D:
DSP Source Codes
APPENDIXD: DSP SOURCE CODES
This appendix contains listings of the DSP software (written in C) developed for the
experimental T-PQC described in Chapter 7. The following files are listed:
•
'HYS.H' - File contains T-PQC definitions and constants;
•
'HYSMAIN.C - File contains T-PQC background routines;
•
'HYSINT.C - File contains T-PQC interrupt routines.
D.I
LISTING O F 'HYS.H'
Application: T-PQC definitions
Developed By: Monash University
Author:
Pee-Chin Tan
Pile:
hys.h
Rev:
l.O
* History:
Derived from PCR code
#define TRUE
#define FALSE
1
0
^define ADC_ZERO
512
#define TABLE SIZE
1024
ml
/* for sine and sqrt look-up tables */
l
ml
/* handy factors for the PWM timing and scaling •/
#define CPU_FREQ
200000001
20 MHz */
#define PERIOD_2
1000
odd number better */
#define PERIOD
(PERI0D_2*2)
#define SW_FREQ
(CPU_FREQ/(2*i>ERIOD))
/* 5kHz */
/* the /2 is because the timer is set for up down counting so the time for
* a complete switching cycle is 2*PERIOD. Also assumes a clock prescaler
* of /I (ie clock tick is 50ns) */
#define PHASE_STEP_SC
#define FUND_FREQ
#define PHASE STEP
(S5536/SW_FREQ/2)
50~
(PHASE STEP SC*FUND FREQ)
/* deadband in nanoseconds */
#define DEADBAND
2000
/* converted to clock counts */
tfdefine DEADCNT
( (int) (DEADBAND*le-S)*C,PU_FREQ))
/* minimum pulse width in nanoseconds */
#define MINPULSETIME 1000
/* converted to clock counts */
#define MINPULSECNT
((int)(MINPULSETIME*le-9*CPU_FREQ))
#define MAX TIME
1
i
(PERIOD 2 - DEADCNT"- MINPULSECNT)
229
ii iXst^jfi•'Aii—^a' Hr&'LlrHi**
APPENDIX D:
i-'Jf^Mi'-
DSP Source Codes
/* upper limit on the amount of deadband compensation that can be added */
fldefine MAX_COMP
(2*DEADCNT)
#define MAX REF DIFF
100
/* analog input scaling factors */
/* scaling of dc link voltage : Vdc[V] = V_DC_SC*V_DC[ADC] */
#define V_DC_SC ((10.0/512 .0) * (510/10.0) ) /* 0.99i~l */
/* scaling of analog voltage input : Emf[V] = E_AC SC*Emf[ADC]
#define E_AC_SC ((10.0/512.0) * (450/10. 0) ) /* 0.878s"0625 */
/* scaling of analog current input : I[A] = I_AC_SC* I [ADC] */
#define I_AC_SC ((5.0/1024.0)*(2.2/10)*200.0/18.0) /* 0.011936
/* PCR constants
#define L
#define DT
#define Vdc_MIN
#define Vdc_MAX
#define MIN DVDT
(0.005)
/* filter inductance in Henrys */
(( (double)PERIOD)/((double)CPU_FREQ)) /* delta t lOOus */
100
330
1
/* minimum Vdc in volta */
/* maximum Vdc in volts */
/* point where Vdc is charged thro bleed R */
/ E_AC_SC is divided by 3 to account for the transformation of the measured
* line-to-line voltages to line voltages */
/* 4.074 */
#define I_SCALE
( (I_AC_SC/(E AC_SC/3))*(L/DT) )
/* 1305.56 */
#define V_SCALE ( 2*PERIOD_2*(E_AC_SC/3)/V_DC_SC )
/* minimum allowable DC bus voltage (in adc) */
#define V_DC_MIN
((int)(Vdc_MIN/V_DC_SC + 1))
/* maximum allowable DC bus voltage (in adc) */
Sdefine V_DC_MAX
({int)(Vdc_MAX/V_DC_SC))
I.
/* number of saturation switching intervals to cause loss of supply fault */
tfdefine SAT_LIMIT
((int) (7e-3*2*SW_FREQ))
#define MAG_MAX
#define MAG_SCALE
/* fault bits */
#define NO FAULT
#define GATE_FAULT
#define LC_VDC1
#define LC I MOD
#define LOST_SYNC
#define LOST_SUPPLY
#define LOW_DC_VOLTS
#define SCALE_ERROR
#define DC_CHARGE_FAULT
Sdefine CONTACT_FAULT
#define OVERJi'EMP FAULT
#define MISC~FAULT
#define ALL_FAULTS
32000
8
0x0000
0x0001
0x0002
0x0004
0x0008
0x0010
0x0020
0x0040
I
0x0080
0x0100
0x0200
0x8000
Oxffff
/* CS-IIB LEDs */
#define LED..4
#define LED..2
#define LED11
fldefine LED10
#define LED8
fldefine LED7
tfdefine LEDS
#define LED4
0x0001
0x0002
0x0004
0x0008
0x0010
0x0020
0x0040
0x0080
/* CS-IIB DIP switches */
#define DIP1
#define DIP2
#define DIP3
#define DIP4
#define DIP5
#define DIPS
#define DIP7
0x0001
0x0002
0x0004
0X0008
0x0010
0x0020
0x0040
I
230
APPENDIX D:
DSP Source Codes
#define DIP8
0x0080
/* timer 1 macros */
/* enable timer bit in TxCON
#define TENABLE
tfdefine Timerl_start()
Sdefine Titnerl_stop ()
0x0040
{ reg(TlCON) = 0xa842; }
{ reg(TlCON) = 0xa802; }
/* PWM macros: the PWM_start is a clunky function since the deadband unit is
buggy. Leaving the timer running and just changing ACTR and SACTR stuffs up
the deadband, so starting the PWM involves re-initializing the timer. */
#define PWM_stop()
{ reg(SACTR) = 0x0000; \
reg(ACTR) = 0x0000; \
is_modulating = FALSE; }
#define PWM_freq(_db_)
\
\
dead_band = _db_; \
/* operating modes */
tfdefine MODE_V_SRC
#define MODE_V_SYNC
tfdefine MODE_V_MATCH
#define MODE_I_SRC
#define MODE_I~SYNC
#define MODE_I_VDC
/* zero
#define
#define
#define
#define
#define
Sdefine
#define
0
1
2
3
4
5
/*
/*
/*
/*
/*
/*
VSI
VSI
VSI
PCR
PCR
PCR
voltage source */
sync to Emf
*/
match Emf
*/
current source */
sync current source */
rectifier with Vdc control */
corssing states */
ZX_LOST
ZX_EST
ZX_SYNC
ZX_PHASE
3
ZX_FREQ
ZX_L0CK
ZX MISC
I
/* analog definitions - for use with a_val[]
#define AVAL_VAC1
3
tfdefine AVAL_APOT2
9
#define AVAL VDC1
0
/* shared variables between the vsi .interrupt and the rest of the world. */
/* defined in PCRINT.C so that they are explicitly stored in the fast on-chip
* RAM. */
extern unsigned int
£>.dc_Vdc,
Vdc_ref,
Vac_ref,
phase_step,
phi,
dead_band,
is_tnodulating,
in_sync,
is_sync,
is_AF,
is_tnag,
is_RPC,
op_mode,
fault;
/* bits set indicate faults */
I
i
extern signed int
Vdc_sum,
af_factor,
mag_bak,
mag;
/* defined in pcr_main.c */
extern unsigned int
a val [16] ;
/• latest analog values */
231
I7*SSn«* .jj»u>»)j.*»*w.i*"- »
APPENDIX D:
DSP Source Codes
/* shared for debug only
extern unsigned int
phase,
ZX__in_sync,
ZX~state,
81,32,33,34,85,86,
/* magic shift numbers */
/* calculated scale factor for voltage to time */
v_scale_int;
extern signed int
i_max_err,
maximum current error for accurate scaling */
v_max_err,
maximum intermediate voltage value */
v_max_err,
i_scale_int;
/* calculated scale factor for current: to voltage (L/dt) */
tfdefine GRAB_READY
#define GRAB~GO
idefine GRAB_DONE
fldefine GRAB~PAUSE
tfdefine G_COUNT
#define G SIZE
extern
extern
extern
extern
extern
extern
extern
signed
signed
signed
signed
signed
signed
signed
int
int
int
int
int
int
int
0
l
2
3
4400
g_con;
g_a;
g_b;
g_c;
g_d;
g_idx;
g_max[ll];
/* defined in pcrmain */
extern signed int g[G_COUNT][G_SIZE]
extern long sumsq, Vacl_sq[201];
/* sets up timer and PWM registers, but with PWM outputs off */
void PWM_Init(void);
/* currently just like PWM_init except that the PWM outputs are turned on */
void PWM_Start(void);
/* sets up level comparison interrupt */
void Fault_init(unsigned int fault);
/* clears the faults and checks that they have cleared, returns fault status */
unsigned int check_faults(unsigned int fault_mask);
/* the interrupts */
interrupt void XINT2_int(void);
interrupt void XINT3_int(void);
interrupt void INT2Service(void);
interrupt void INT4Service(void);
i
m
I
D.2
LISTING OF 'HYSMAIN.C'
Application: T-PQC background routines
Developed By: Monash University
Author:
Pee-Chin Tan
File:
hysmain.c
Rev:
1.0.IIB
History:
Derived from PCR code
#include
Sdefine
#include
#include
#include
#include
#include
#include
frinclude
#include
<c240.h>
miniDSPpcb
<mu_pcb.h>
<stdlib.h>
<conio.h>
<adc.h>
<intrpt.h>
<iospace.h>
<math.h>
232
APPENDIX D:
DSP Source Codes
#include "hys.h"
#include "timer.h"
/* digital inputs */
#define DIG_START
^define DIG_STOP
#define DIG~CONTCLOSE
DIPS
DIP6
DIPS
tfdefine StartPressed()
#define StopPressedO
^define ContClosed()
(is_started)
(!is_started)
(digin&DIG_CONTCLOSE)
/* digital outputs */
^define DIG0UT1
#define DIG0UT2
tfdefine DIG0OT3
0x0020 /* Maybe one day these will make it */
0x0040 /* into mu_pcb.h
*/
0x0080
#define DIG_CONT
Sdefine DIG AUX CONT
DIGOUT2
DIGOUT3
#define ContactorOpen (_c_)
#define ContactorClose(_c_)
set_digout(_c_,CLEAR)
set_digout(_c_,SET)
#define LAMP_FAULT
#define IAMP_READY
#define LAMP_0N
LED14
LED12
tfdefine SetLajap(_l_,_s_)
WriteDigoutLatch(_l_,_s_)
/* dip switches */
^define DIP_AUTO
#define DIP MAG
#define DIP_SYNC
#define DIP PCR
LED11
DIP4
DIP3
DIP2
DIP1
/* heatsink temperature scaling factors */
#define RTD_ZER0
53
#define RTD~SCALE
0.1428
#define RTD TRIP
(45*(1«S))
I
1
double
rectavgl, rectavg2, rectavg3, rectavg4,
rmsl, rms2, rms3, rms4,
ffl, ff2, ff3, ff4;
long
sumsql, sumsq2, sumsq3, sumsq4,
sumabsl, sumabs2, sumabso, sumabs4;
signed int
hs_temp = 0,
Idemand,
la = 0,
mod_depth,
Vdc = 0,
oldJVdc = 0,
mag_bak;
/*
/*
/*
/*
/*
/*
/*
heatsink temp in 64ths of a degC */
demanded current in 256th of an amp */
measured current in 256th of an amp */
mod depth in 8ths of a percent */
dc bus voltage in volts */
32ms old dc bus voltage for charge control
background level magnitude reference */
unsigned int
tnaxjpoints,
Oxffff,/* dead time compensation level */
dead_band_comp
/* switching frequency */
sw_freq = 0,
/* operating mode */
op_mode,
/* temporary variable */
temp,
/* peak measured current in 256th of an amp */
Ipeak,
Old_fault = N0_FAULT /* known faults */
/* fundamental frequency */
freq,
/* mirror of the digital inputs */
digin,
/* latest analog values */
a_val[16] = {0},
/* which faults are tested for */
tested_faults,
/* initialised to TRUE to pass thro stop pressed
is started = TRUE;
check in charge state */
timerNumber
onesec timer,
P
/* times out seconds */
233
APPENDIX D:
fault_timer;
DSP Source Codes
/ * timer for fault clearing • /
/* used in hysint.c but too large to fit in the on-chip RAM */
long
sumsq = 0 ,
/* sum of squares for rms calculation */
Vacl_sq[201] ;
/* used for rms calculation */
/* assume 200 samples per cycle, so need 201 storage */
signed int
g[G_C0UNT][G_SIZE]; /* grab data */
/• state stuff */
typedef void (* funcPtr)(void);
typedef struct
{
funcPtr f;
int first;
} StateType;
StateType state;
^define NextState(_s_,_f_)
{ _s_.f = &_f_; \
Jtdefine IsFirstState(_s_)
#>ief ine DoneFirstState(_s_)
#define IsLastState(_s_)
Sdefine DoState(_s_)
#define IsCurrentState(_s_,_f_) (
(_s_.first == 1)
_s_.first = 0
(_s .first == 1)
_s_.first = 1; }
U*7_s_.f)) 0 )
f == & f )
void Statelnit(void);
void StateRestart(void);
void StateCharge(void);
void StateCloseWait (void) ;
void StateOpenWait(void);
void StateSync(void);
void StateStop (void) ,void StateRun(void);
void StateRampUp(void);
void StateRampDown(void);
void StateFault(void);
void CheckFault(void); /* fault detection - uses tested_faults */
/* serial port display of variables */
void init_display(void);
void display(char c ) ;
void display_fault(unsigned int fault);
void display_state(StateType state);
void display_sync_state(unsigned int state);
int keyboard(void); /* serial input handling : returns quit status */
void scale_adcs(void); /* scales analog values to real units (ie V and A) */
void onesec_events(void); /* performs one second events */
void get_variables(void); /* asks user for relevant parameters */
void set_variables(void); /* sets the parameters with default values */
void putl(signed long int value);
void putdbl2(double d, char pi, char p2);
/* ramp macro */
\
#define ramp(_var_,_targ_)
{\
\
if (_var_ < _targ_) _var_++; \
else if (_var_ > _targ_) _var_--; \
int mainO
char
c,
quit = 0;
signed int
autostart = FALSE,
count = 0,
freq_scale,
234
^
APPENDIX D:
DSP Source Codes
mag_scale;
unsigned int i ;
/ * standard i n i t i a l i z a t i o n for the board • /
iait_pcb();
ii
EnablePowerRelayO ;
puts(»\n\n\tPCR/VSI controller\n\n");
/ * set up interrupt vectors
set_SISR_jump();
set_SISR_vector(RTI_int,WDINT);
set_SISR_vector(XINT2_int,XINT2_ISR);
set_SISR_vector(XINT3_int,XINT3_ISR);
set_GISR_vector(RTI_int,INT1);
set_GISR_vector(lNT2Service,INT2);
set_GlSR_vector(lNT4Service,INT4)•
/* set up registers for ADC measurements */
reg(ADCTRLl) = ADCEMULATOR|ADC1EN|ADC2EN|ADCINTFLAG|ADC_VAC1|ADC_APOT2;
reg(ADCTRL2) = ADCEVSOC| ADCPSCAL.E; /*0x0403;*/
/* test for auto start */
if (~ReadDigIn()&DIP_AUTO) /* autostart, DIPSW inverted in h/w */
autostart = TRUE;
set_variables();
}
else
{
get_variables();
}
sw_freq = (CPU_FREQ/2/PERIOD_2 + l)/2;
puts("Switching frequency is " ) ; putu(sw_freq);
puts("Hz\nhalfjperiod is " ) ; putu(PERI0D_2); puts("\n");
putsC'Deadband compensation is: " ) ; putu(dead_band_comp*50); puts("ns\n"),
if (autostart == FALSE)
{
puts("\nPress any key to start\n");
getc() ;
freg_scale = (50*163841 + sw_freq/2)/sw_freq;
/* initialize state machine */
Statelnit();
/* initialise display stuff */
c = ' •;
init_display() ;
while (quit != 1)
{
CheckFaultO;
DoState(state);
digin = -ReadDigln();
q
keyboard(
quit = keyboard();
TimerFuncPoll();
scale_adC8(
display(0);
/* check for faults */
/* call state function */
/* read digital
dii
inputs - inverted in hardware */
/* handle keyboard input */
/* run any queued timer functions */
/* scale adc measurements */
/* serial port display */
DisablePowerRelay();
return 0;
} /* end main */
/* it is the background process1 task to clear the flags */
void onesec_events(void)
235
I
APPENDIX D:
DSP Source Codes
ReloadTimer(onesec_timer, 1000 tnSEC);
/* check for low speed faults */
if (hs_temp > RTDJTRIP)
{
/* fault |= OVERJTEMP; */ /* No temperature sensor as of yet */
if (IsCurrentState(state,StateFault))
display_fault(faultttested_faults);
display(1);
} /* end onesec_events */
/* serial port display of variables */
void display(char c)
static unsigned int step = 0;
if (c == TRUE)
step = 1;
putsC \ r " ) ;
else if (step > 0)
{
step++;
switch(step)
case
case
case
case
case
case
case
case
case
case
case
case
case
case
case
•;ase
case
case
case
case
case
1: putu(i-req); break;
2: putsC ") ; break;
3: display_state(state); break;
4: puts(" ") ; break;
S: putd(Vdc); break;
6: puts(" " ) ; break;
7: putu(a_val[AVAL_AP0T2]); break;
8: puts(" " ) ; break;
9: putd(af_factor); break;
10: puts(" " ) ; break;
11: putdbl2(ffl, 3, 4 ) ; break;
12: puts(" " ) ; break;
13: putdbl2(ff2, 3, 4); break;
14: puts(" " ) ; break;
15: putdbl2(ff3, 3. 4); break;
16: puts(" ") ; break;
17: putdbl2(f£4, 3, 4 ) ; break;
18: puts(" " ) ; break;
19: display_sync_state(ZX_state); break;
20: puts(" " ) ; break;
21: putu(Vac_ref); break;
1
default: step = 0;
} /* end display */
/* scales analog values to real units (ie V and A) */
void scale_adcs(void)
signed int
temp;
unsigned int
count;
if (is_mag) /* magnitude control */
mag_bak =
/*
/*
/*
(a_val[AVAL_APOT2]-ADC_ZERO)*MAG_SCALE;
else if (op_mode == HODE_I_VDC)*/ /* Vdc control instead */
{*/
/* NOTE - negative since dec mag -> inc Vdc */
Vdc_err = a_val [AVAIi_VDC] - a_val [AVAL_POT1] ;
Vdc sum += (Vdc err<<l);*/
236
APPENDIX D:
DSP Source Codes
/* clamp integrator sum */
if (Vdc sum > 30000)
{
Vdc sum = 30000;
}
else if (Vdc sum < -30000)
{
Vdc sum = -30000;
}
mag_bak = (Vdc_err<<l) + Vdc_sum;
if ( (op_mode == M0DE_V_SRC)||(op_mode == MODE_V_SYNC) )
temp = 1001*(1<<5);
mod_depth = ((long)tnagjbak* (long) temp) >>16;
}
else
{
temp = I_AC_SC*(11«18) ;
Idemand = ((long)mag_bak*(long)temp)>>16;
/* 8 bits after the point */
freq = (int)( (((long)phase_step)*2*sw_freq)/655361);
temp = (int)(RTD_SCALE*(11<<16));
hs_temp = ( (long) (((signed) a_val [AVAL_RTD] - RTD_ZERO)«6)
* (long)temp )>>16; */
/* 6 bits after the point */
old_Vdc = Vdc;
temp = V_DC_SC*(11«14) ; / * l ( l o n g ) s h i f t l e f t by 14 * /
Vdc = ((long) ( ((signed) a_val [AVAL_VDC1] -ADC_ZERO) « 2 ) * (long) temp) » 1 6 ;
/*Vac = (int)(((long)((signed)a_val[ADC_V1MOD]-512)*(E_AC_SC*1024l))/lO24l);*/
/ * l a = (int) (((long) ((signed)a_val[AVAL_I1MOD]-512)*(I_AC_SC*1024l))/41);
/* only calculate rms and average after each set of grab */
if (g_con == GRAB_DONE)
/ * m a x _ p o i n t s = ( 6 5 5 3 6 1 * (CPU_FREQ / PERIOD) / 2 / s w _ f r e q /
g[0][0])
max_points = 200;
sumsql = 0;
sumsq2 = 0;
sumsq3 = 0;
sumsq4 = 0;
sumabsl = 0;
sumabs2 = 0;
sumabs3 = 0;
sumabs4 = 0;
I
I
for (count = 0; count < (max_points); count++ )
sumsql
sumsq2
sumsq3
sumsq4
+=
+=
+=
+=
(long) g [count] [1] * (long) g [count] [1]
(long) g [count] [2] * (long) g [count] [2]
(long) g [count] [3] * (long) g [count] [3]
(long) g [count] [4] * (long) g [count] [4]
if (g[count] [1] < 0)
sumabsl -= g [count] [1] ;
}
else
I
{
sumabsl += g [count] [1] ;
if
i
(g[count] [2] < 0)
4
aumabs2 -= g [count] [2] ;
237
APPENDIX D:
DSP Source Codes
else
{
if
{
sumabs2 += g [count] [2] ;
(g[count] [3] < 0)
sumats3 -= g [count] [3] ;
}
else
{
sumabs3 += g[count] [3] ;
if
(g[count] [4] < 0)
sumabs4 -= g [count] [4] ;
else
sumabs4 += g[count] [4];
}
rrasl = sqrt((double)sumsql / max_points);
rectavgl = (double)sumabsl / max_points;
rras2 = sqrt((double)sumsq2 / max_points);
rectavg2 = (double)sumabs2 / max_points;
rms3 = sqrt((double)sumsq3 / max_pointa);
rectavg3 = (double) sumabs3 / max_points;
rms4 = sqrt((double)sumsq4 / max_points);
rectavg4 = (double)sumabs4 / max_points;
f£l
ff2
ff3
ff4
= rmsl/rectavgl;
= rms2/rectavg2;
= ras3/rectavg3;
= rms4/rectavg4;
g_ccn = GRAB_READY;
} /* end scale_adcs */
•Si
/* fault detection - uses tested_faults */
void CheckFault(void)
1
{
if
I
((fault&tested_faults)&&(!lsCurrentState(state,StateFault)))
{
}
PWM_stop() ;
ContactorOpen(DIG_CONT|DIG_AUX_CONT);
old_fault = fault;
NextState(state,StateFault);
is_started = TRUE;
/* wait for stop pressed in fault state */
display_fault(old fault);
} /* end CheckFault */
/* prepares everything for state machine */
void Statelnit(void)
{
phase_step = PHASE_STEP;
PWM_freq(dead_band_comp);
t e s t e d _ f a u l t s = GATE_FAULT|LC_VDC1|LC_I_MOD|LOW_DC_VOLTS;
i f (is_sync==TRUE) t e s t e d _ f a u l t s
Fault_init(tested_faults);
PWM_Init();
EnablelntsO ;
|= (LOST_SYNC|LOST_SUPPLY);
Timerlnit();
/* start timer for background processes */
onesec_timer = GetTimer(); /* for ticking off 1 sec events */
StartTimer(onesec_tia?r. X0O0 mSEC, &onesec_events);
238
APPENDIX D:
DSP Source Codes
fault_timer = GetTimerO; /* for fault clearing */
NextState(state,StateRestart);
tested_faults = ALL_FAULTS&-(LOW_DC_V0LTS|L0ST_SUPPLY|L0ST_SYNC);
SetLamp(LAMPJ3N|LAMP_READY|LAMP_FAULT,CLEAR);
} /* end Statelnit *? •
/* restart everything either after a fault or on start up. */
void StateRestart(void)
mag = 0;
NextState(state,StateCharge);
tested faults = ALL_FAULTS&-(LOW_DC_VOLTS|LOST_SUPPLY|LOST_SYNC);
SetLamp(LAMP_READY,SET);
is_started = TRUE;
/* to pass thro stop press check in charge state */
} /* end StateRestart */
/* closes the charge contactor and waits for the DC bus to charge */
void StateCharge(void)
static int maxla = 0, oldmaxla = 0;
static timerNumber peak_timer;
/* timer for peak la measurement */
static timerNumber charge_timer;/* timer for dc bus charging */
if (IsFirstState(state))
DoneFirstState(state);
maxla = 0; /* clear max la before starting to wait */
oldmaxla = 0;
ContactorClose(DIG_AUX_CONT);
peak_timer = GetTimerO; /* timer for the peak meas. */
charge_timer = GetTimerO; /* timer for the charge delay */
StartTimer(charge_timer, 10000 mSEC, NULL);
StartTimer(peak_timer, 1000 mSEC, NULL);
if (StopPressedO)
NextState(state,StateRestart) ;
ContactorOpen(DIG_AUX_CONT);
else if (IsTimerFinished(charge_timer))
{ /* if still drawing >lAmp after 10 seconds > fault */
if (oldmaxla > (1.0*256)) /* Ipk > 1A */
fault |= DC_CHARGE_FAULT;
NextState(state,StateFault);
puts("\nln Charge Fault Part\n\n");
ContactorOpen(DIG_AUX_CONT);
else /* no fault, so keep charging */
StartTimer(charge_timer, 10000 mSEC, NULL);
oldmaxla = C.
maxla = 0 ;
}
/* ca]c max(la) */
if (la > maxla) maxla = la;
else if (-la > maxla) maxla = -la;
Ipeak = maxla;
/* test for charged DC bus */
if (IsTimerFinished(peak_timer))
/*
if ((maxla > 77)||(Vdc < Vdc_MIN-50)) /* Ipk > 0.3A (0.3*256=77) */
{ /* not charged yet, wait further */
ScartTitner (peak_timer, 100 mSEC, NULL);
oldmaxla = maxla;
maxla = 0;
puts(«\n");
putu(oldmaxla); puts(" ") ;
putu(la); puts(" ") ;
putu (a_val fAVAL_HMOD]); puts ("
putu(Vdc); put s ( " " ) ;
") ;
putu(Vdc_MIN+5); */
else /* charged: */
239
APPENDIX D:
DSP Source Codes
/•NextState(state,StateCloseWait);*/
NextState(state,StateSync);
fault &= -LOW_DC_VOLTS; /* clear fault flag */
tested_faults |= LOW_DC_VOLTS; /* enable low Vdc fault checking
f-.to ("\nEntering Sync State. \n") ;
if (IsLastState(state))
FreeTimer(peak_timer);
FreeTimer(charge_timer);
} /* end StateCharge */
/* closes the main contactor and waits fox it to close */
void StateCloaeWait(void)
static timerNumber cont_timer;
if (isFirstState(state))
/* contactor closing delay */
DoneFirstState(state);
ContactorClose(DIG_CONT);
cont_timer = GetTimerO; /* the contactor closing delay */
StartTimer(cont_timer, 500 mSEC, NULL);
if (StopPressedO)
NextState(state,StaceOpenWait);
else if (IsTimerFinished (cont_titner))
if (Coi-tClosedO)
ContactorOpen (DIG_AUX_CONT);
if (is_sync)
/* next state depends on op. mode */
NextState(state,StateSync);
else
{
NextState(state,StateStop);
}
}
else
{
fault |= CONTACT_FAULT;
ContactorOpen(DIG_CONT|DIG_AUX_CONT);
old_fault = fault;
NextState(state,StateFault);
display_fault(old_fault);
StartTimer(fault_timer, 10000 mSEC, NULL); /* delay befre retry
"I
}
if (IsLastState(state))
{
}
FreeTimer(cont_timer);
} /* end StateCloseWait */
/* waits for main contactor to open */
void StateOnenWait(void)
{
static timerNumber cont_timer;
if (IsFirstState(state))
/* contactor opening delay */
DoneFirstState(state);
ContactorOpen(DIG_CONT|DIG_AUX_CONT);
cont_timer = GetTimer(); /* the contactor opening delay */
StartTimer(cont_timer, 500 mSEC, NULL);
}
if (lsTimerFinished(cont_timer))
{
if (!ContClosed(>)
240
APPENDIX D:
DSP Source Codes
{
}
NextState.state,StateRestart);
else
{
fault |= CONTACT_FAUIJT;
old_fault = fault;
NextState(state,StateFault);
display_fault(old_fault);
StartTimer(fault_timer, 10000 mSEC, NULL); /* delay befre retry
V
if (IsLastState(state))
FreeTiraer(cont_timer);
} /* end StateOpenWait */
/* waits until sync is achieved */
void StateSync(void)
/* time to achieve sync */
static timerNumber sync_timer;
if (IsFirstState(state))
DoneFirstState(state);
sync_timer = GetTimer();
StartTimer(sync_timer, 10000 mSEC, NULL); /* 10 sec to sync in */
}
if (StopPressedO )
NextState(state,StateRestart);
PWM_stop();
ContactorOpen(DIG_CONT|DIG_AUX_CONT);
else if (in_sync)
fault &= ~(LOST_SUPPLY|LOST_SYNC); /* clear these faults */
NextState(stateTstateStop);
tested_faults |= (L0ST_SUPPLY|LOST_SYNC);
is_started = FALSE;
/* wait in stop state until start pressed */
}
else if (is_sync==FAljSE)
NextState(sta^e.StateStop) ,is_started = FALSE;
/* wait in stop state until start pressed */
else if (IsTitnerFinished(sync_timer)) /* failed to sync */
fault |= LOST_SYNC;
PWM_stop();
ContactorOpen(DIG_CONT|DIG_AUX_CONT);
old_fault = fault;
NextState(state,StateFault);
display_fault(old_fault);
if (IsLastState(state))
I
FreeTimer(sync_timer);
} /' end StateSync *,
/* state for when the inverter isn't running */
void StateStop(void)
{
mag = 0;
if (StartPressedO )
{
}
NextState(state,StateRampUp);
PWM_Start();
Vdc_sum = 0;
SetLamp(LAMP ON,SET);
} /* end StateStop */
241
APPENDIX D:
DSP Source Codes
/* state for ramping the magnitude up to i;he reference */
void StateRampUp(void)
if (StopPressedO)
NextState(state,StateRampDown);
else if ( (mag>mag_bak-10)&&(mag<mag_bak+10) ) /* ramping finished */
NextState(state,StateRun);
else
ramp (mag,mag_bak) ;
ramp(Vdc_ref,a_val[AVAL_APOT2]);
} /* end StateRampUp */
/* state for having the inverter run */
void StateRun(void)
if (StopPressedO)
NextState(state,StateRampDown);
else if (op_mode != MODE_I_VDC)
{
mag = mag_bak;
}
else
{
i n t temp;
temp = (a_val[AVAL_AP0T2] - Vdc_ref)
;
/* provides hysteresis to ignore noise on pot reference */
if ( (temp > 1 ) || (temp < -1) ) Vdc_ref = a_val[AVAL_AP0T2];
} /* end StateRun */
/* state for ramping the magnitude down to zero before turning off */
void StateRampDown(void)
if (StartPressedO)
NextState(state,StateRampUp);
else if (mag == 0) /* ramping finished */
PWM_Stop() ;
NexEstate(state, StateStop);
SetLamp(LAMP_ON,CLEAR);
}
else
{
ramp(mag,0);
ramp(Vdc_ref,0);
} /* end StateRampDown */
/* state for handling faults */
void StateFault(void)
{
static unsigned int fault_stafe = 0;
if (IsFirstState(state))
' {
DoneFirstState (state) ,•
PWM_stop() ;
ContactorOpen (DIG_C0NT,' niG_AUX_CONT) ;
SetLamp (LAMP_0N| LAMP_READY, CLEAR) ;
SetLamp(LAMP_FAULT,SET);
}
testeci_faults &= -LOW_DC_VOLTS; /* open contactor, so low Vdc i-3 likely */
if
== NO_FAULT)&&(fault_state == 0))
f ((check_faults(tested_faults)
puts("\nFaults cleared - press stop to continue\n");
fault state = 1;
242
APPENDIX D:
if
DSP Source Codes
((StopPressedO)&&(fault_state == 1))
StartTimer(fault_timer, 1000 mSEC, NULL); / * delay * /
fault_state = 2;
puta("XnRestarting...\n");
if
((fault_state == 2) &&(IsTimerFinished(fault_tiineir)))
NextState(state,StateRestart);
fault_state = 0;
SetLamp (LAMP_FAULT, CLEAR) ;
} /* end State Fault */
/* handles serial port input */
int keyboard(void)
char c, i, j;
int ret_val = 0;
if (kbhitO)
c = getcO ;
switch(c)
case 'q': /* quit •/
PWM_stop();
ContactorOpen (DIG_C0N? | DIG_AUX_CONT) ;
DisablelntsO ;
ret_val = 1;
puts("\n\n\tQuitting\n\n") ;
break;
case 'h 1 : /* help */
puts("\tq\tquit\n")•
puts("\tf\tdisplay fault status\n");
puts("\ts\tdisplay the scaling factors\n");
puts("\tl\tincrease phase offset\n");
puts(n\t2\tdecrease phase offset\n");
puts("\tc\treset grab system\n");
puts("\td\tdisplay grabbed results\n");
puts("\tm\tdisplay misc data\n");
puts("\tg\tstart grab\n");
puts("\t3\tstart switching\n");
puts("\t4\tstop switching\n");
puts("\t5\tstart reactive power compenaation\n");
puts("\tG\tstop reactive power compensation\n");
puts("\t<\tDecrease the % Harmonic Compensation\n")
puts("\t>\tlncrease the % Harmonic Compensation\n")
putg("\t[\tDecrease the AC RMS Voltage\n");
puts("\t]\tlncroase the AC RMS Voltage\n");
break;
case
puts("\nScaling factors\n\tsl
);
putu(sl);
puts("\n\ts2 = " ) ;
putu(s2);
puts("\n\ts3 = " ) ;
putu(s3);
puts("\n\ts4 = " ) ;
putu(s4);
puts("\n\ts5 = " ) ;
putu(s5);
puts("\n\ts6 = " ) ;
putu(s6);
puts("\n\tv_scale_int = " ) ;
putu(v_scale_int);
puts("\n\ti_scale_int = " ) ;
putu(i_scale_int);
puts("\n\ti_max_err = " ) ;
putu(i_max_err);
puts("\n\tv_max_err = " ) ;
putu(v_max_err);
puts("\n\n");
break;
'it,
i
I
1
243
APPENDIX D:
DSP Source Codes
case '£'-. /* display current faults */
if (fault==NO_FAULT)
{
puts("\nNo faults\n");
puts("\n")
else
display_fault(fault);
}
break;
case '1':
phi += 16;
break;
case '2 ' :
phi -= 16;
break;
case '!' :
phi += 256;
break;
case '®':
phi -= 256;
break;
case 'c 1 : /* clear grab code */
g_idx = 0;
g_con = GRAB_READY;
puts("Grab cleared\n");
break;
case ' g ' : / * s t a r t grab now * /
puts("Grab started\n");
g_idx = 0;
g_con = GRAB_GO;
break;
case ' d ' : / * display grabbed data * /
puts( r '\n\ni\tadc_Vacl\ty3\ty5\ty7\tyt\tybs\tadc_Vdc\tVdc_err\tlref\t");
puts("phase_step\tmag\tVdc_fl\n");
for (i=0; i<G_COUNT; i++)
putd(i);
for (j=0; j<G_SIZE; j++)
putc('
');
putd(gii] [j]) ;
putc('\n•);
break;
case 'm1: /* display misc data */
putS("\n\nRMSl\tRMS2\tRMS3\tRMS4\n");
putdbl2(rmsl, 3,
puts(" ") ;
putdbl2(rms2, 3,
puts (" ") ;
putdbl2(rms3, 3,
puts(" ") ;
putdbl2(rms4, 3,
puts (" ") ;
putu(max_points);
puts(" ") ;
putc('\n');
4);
4);
4);
4);
break;
case '3': /* start switching */
is started = TRUE;
'4 1
/* stop switching */
J3_started = FALSE;
break;
•>': /* Increase % harmonics to be filtered */
if(af_factor < 32700)
{
af_factor += 32760;
244
APPENDIX D:
DSP Source Codes
break;
case '<•: /* Decrease % harmonics to be filtered */
if(af_factor > -32700)
af_factor -= 32760;
break;
case '5': /* Start reactive power compensation */
is_RPC = TRUE;
puts("\nReactive Power Compensation Enabled\n");
break;
case '6 1 : /* Stop reactive power compensation */
is_RPC = FALSE;
puts("\nReactive Power Compensation Disabled\n");
break;
case '[': /*Decrease AC RMS Voltage reference */
if(Vac ref > 0)
Vac_ref -= 1;
break;
case ' ] ' : /*Increase AC RMS Voltage reference */
if(Vac ref < 200)
{
Vac_ref += 1;
)
break;
}
return ret_val;
} /* end keyboard */
/* initializes the serial display */
void init display(void)
{
puts("\n\nmod
freq
} /* end init_display */
state
VDC
P0T2
ZX\n")
void display_'fault (unsigned int fault)
if (fault!=NO_FAULT)
puts("\nFault detected :\n");
if (fault&GATE FAULT)
puts("\tGate - O/C - O/V fault\n");
putx(get_fault 0 } ; */
puts("\n");*/
/*
/*
}
if
if
if
if
if
if
if
if
if
if
(£ault&LC_VDCl) puts("\tDC over voltage fault\n");
(fault&LC_I_MOD) puts("\tOver current fault\n");
(fault&LOST_SYNC) puts("\tLoss of sync fault\n");
(faulttLOST_SUPPLY) puts("\tLoss of supply\n");
(fault&LOW_DC_VOLTS) puts("\tLow DC volts\n");
(fault&MISC_FAULT) puts("\tMisc fault\n");
(fault&SCALE_ERROR) puts("\tScale error\n");
(fault&DC_CHARGE_FAULT) puts("\tDC bus charge fault\n");
(fault&CONTACT_FAULT) puts("\tContactor fault\n");
(fault&OVER_TEMP_FAULT) puts("\tHeatsink over temp fault\n");
} /* end display_fault */
void display_state(StateType state)
puts("Init
if (state.f == &StateInit)
puts("Restart");
else if (state, f == SStateRestart)
puts("Charging");
else if (state. f == &StateCharge)
else if (state, f == SStateCloseWait) putsC'CloseWt") ;
else if (state, f == &StateOpenWaiL,> putsC'OpenWt ") ;
puts("Sync " ) ;
else if (state, f == &StateSync)
puts("Stop
" ) ;
else if (state, f == SStateStop)
putsC'RampUp ") ;
else if (state, f == SStateRampUp)
puts("Run
else if (state, f == SStateRun)
else if (state, f == &StateRampDown) puts("RampDwn");
puts("Fault " ) ;
else if (state, f == &StateFault)
else
•1
245
^^^
APPENDIX D:
DSP Source Codes
putxxf(unsigned int)state.f);
putc (•?•);
) /* end display_state */
void display_sync_state(unsigned int state)
if (state == ZX_LOST)
else if (state == ZX_EST)
else if (state == ZX_SYNC)
else if (state == ZX_PHASE)
else if (state == ZX_FREQ)
else if (state == ZX_LOCK)
else if (state == ZX_MISC)
else
puts("ZX
putaC'ZX
put s("ZX
puts("ZX
puts("ZX
puts("ZX
puts("ZX
Lost");
Estimating");
in Sync");
Phase");
Nudging Frequency");
Lock");
Reallocation Period");
putxxf(unsigned int)state);
putc('?•);
} /* end display_sync_state */
/* asks the operator for various parameters before starting up \
void get_variables(void)
char str[10];
/* switching frequency is currently fixed */
sw_freq = 5000;
is_RPC = FALSE;
puts("\nEnter parameters\n");
dead_band_comp = MAX_COMP + 1;
while (dead__band_comp>MAX_COMP)
puts("Enter deadband compensation in units of 50ns : " ) ;
safe_gets(str,10),dead_band_comp = ato.i(str);
is_sync = 7;
while ((is_sync!=TRUE)&&(is_sync!=FALSE))
puts("Synchronize to external voltage signal? (y/n)\n");
switch (getcO)
case 'y' : is_sync = TRUE; puts("Synchronizing\n"); break;
case 'n' : is_sync = FALSE; puts("Running free\n"); break;
is_mag = 7;
while ((is_mag!=TRUE)&&(is_mag!=FALSE))
puts("Current control (c) or Vdc control (v)?\n");
switch (getcO)
case 'c' : is_mag = TRUE; puts("Using current control\n");
break;
case 'v' : is_mag = FALSE; puts("Using Vdc control\n"); break;
switch (is_mag*4+is_syac*2)
case
case
case
case
case
case
case
0:
1:
2 .3: op_mode
4: op_mode
5: op_mode
6: op_mode
=
=
=
=
M0DE__I_VDC; break;
M0DE_V_SRC; break;
MODE_I_SRC; break;
MODE_V_SVNC; break;
246
APPENDIX D:
DSP Source Codes
case 7: op_mode = MODE_I_SYNC; break;
} /* end get_variables */
/* sets the relevant parameters using default values */
void set_variables(void)
puts("\nAutostarting with values given on DIP switches\n");
sw_freq = 5000;
is_RPC = FALSE;
dead_band_comp = DEADCNT;
switch (-ReadDigIn()&(DIP_PCR|DIP_SYNC|DIP_MAG))
case 0:
/* DIP(0)=OFF DIP(1)=OFF DIP(2)=OFF*/
is_AF = TRUE;
is_sync = TRUE;
is_mag = FALSE;
op_mode = MODE_I_VDC;
puts("Running as Hysteresis based Shunt Active Filter\n");
break;
case 1:
/* DIP(0)=0N
DIP(l)=OFF DIP(2)=OFF */
case 2:
/* DIP(0)=0FF DIP(l)=ON
DIP(2)=OFF */
case 3:
/* DIP(0)=0N
DIP(l)=ON
DIP(2)=OFF */
is_AF = FALSE;
is_sync = TRUE;
is_mag = FALSE;
opjmode = MODE_I_VDC;
puts("Running as Hysteresis rectifier with Vdc control\n");
break;
case 4:
/* DIP(0)=OFF DIP(1)=OFF DIP(2)=0N */
is_AF = FALSE;
is_sync = FALSE;
is_mag = TRUE;
op_mode = MODE_V_SRC;
pjts("XXXXXX\n");
break;
case 5:
/* DIP(0)=ON
DIP(1)=OFF DIP(2)=ON */
is_AF = FALSE;
is_sync = FALSE;
is_mag = TRUE;
op_mode = MODE_I_SRC;
puts("Running as hysteresis inverter with magnitude and
frequency control\n");
break;
case 6
/* DIP(0)=OFF DIP(1)=ON
DIP(2)=ON */
is_AF = FALSE;
is_sync = TRUE;
is_mag = TRUE;
op_mode = MODE_V_SYNC;
puts("XXXXXX\n");
break;
case 7:
/* DIP(0)=ON
DIP(1)=ON
DIP(2)=ON */
is_AF = FALSE;
is_sync = TRUE;
is_mag = TRUE;
op_mode = MODE_I_SYNC;
puts("Running as Hysteresis rectifier with current magnitude
control\n");
break;
} /* end set_variables */
/ • * • * * • * * * * * * • • . * * * * * * . * * * * * * * * * * * * * . * * * /
/* This function displays a signed long int out the serial port. Note that
passing an unsigned long int to this function will work fine for a value less
than 2147483S48 and display value-4294967296 for 2147483648 or more. The
compiler probably will not pick this up for you. */
void putl(signed long int value)
signed char
i;
char
digit [12] ;
unsigned long
temp;
247
APPENDIX D:
if
DSP Source Codes
(value < 0)
putc(•-');
temp = -value;
}
else
temp = value;
for (i = 9 ; i >= 0 ; i--)
digit [i] = (temp % 10L) + ' 0' ;
temp = temp / 10L;
digit [10] = '\0';
i = 0;
while ((digit[i] == '0') && (i < 10))
if (i == 10)
putcCO');
while (i < 10) {
putc(digit[i++]);
} /* end putl */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* This function displays a double precision floating point number out the
serial port using standard notation. The argument pl is the minimum number of
characters (either ' ' or [0-9]) to display before the decimal point. The
argument p2 is the number of places to display after the decimal point. */
void putdbl2(double d, char pl, char p2)
signed char
double 1;
1;
if ( (d < le-25) && (d > -le-25) )
for (i=l; i<pl; i++) putc(' ' ) ;
putc ('0');
if (p2 > 0) putcC .') ;
for (i=0; i<p2; i++) rutc('O');
return;
1 =
logio(fabs(d));
if (d <0)
d =
-d;
for (i=(l>0)?((signed char)floor(1)+2):2; i < pl; i++) putcC
putcC-') ;
');
for (i=(l>0)?((signed char)floor(1)+1):l; i < pl; i++) putcC
');
else
putl((signed long int)floor(d));
d -= floor(d) ;
putc('.');
for
(i=0; i<p2;
d =
(d - floor(d))*10;
putd((int)floor(d));
}
} /* end putdbl2 */
D.3
*
*
*
*
*
LISTING OF 'HYSINT.C
Application: T-PQC interrupt routine
Developed By: Monash University
Author:
Pee-Chin Tan
File:
hysint.c
History:
Derived from PCR code
248
VSV1*-^
APPENDIX D:
#include
tfdefine
^include
#include
#include
#include
#include
#include
#include
^include
DSP Source Codes
<c240.h>
miniDSPpcb
<mu_pcb.h>
<fastdiv.h>
<adc.h>
<pwmjutnp.h>
<minibus.h>
"hys.h"
"sqrttab.h"
ioport unsigned char portc040;
ioport unsigned char portc041;
#define MINI_DAC_DATA portc040
#define MINI_DACTADDR portc041
/* zero crossing constants */
ZX_MAX_COUNT is found from
/*
*/
/*
/*
/*
/*
/*
/*
/*
sync lost if no ZX in -3.5 cycles */
number of cycles for frequency estimate */
number of cycles in sync */
-2.2 degrees */
-5.5 degrees - maximum sync phase error */
persistent phase error for freq change */
magic number to trim phase */
unsigned m t
adc_Vdc,
Vdc_ref,
Vac_ref=150,
phase step,
phi,
fault,
dead_band,
is_inodulating,
in_sync,
is PCR,
is_AF,
is_sync,
is_mag,
is_RPC;
/*
/•
/*
/*
/*
/*
/•
/*
/*
/*
/*
/*
/*
/*
DC link voltage [adc units] */
DC Voltage Reference value */
AC RMS Voltage Reference for reactive power comp */
change in phase angle in half a switching cycle */
phase angle offset for power factor control */
bits set indicate faults */
level of compensation for deadband in clock cycles */
flag set if the PWM outputs are active */
flag to indicate that sync is achieved */
run as PCR, not VSI */
run as an Active Filter */
sync to ZX */
magnitude control */
reactive power compensation */
signed int
mag;
/* scaled magnitude reference •/
(3.5 *2 *SW_FREQ/MIN_FUK
#define ZX_MAX_COUNT
#define ZX_CYCL2_AVG
tfdefine ZX_SYNC_LIMIT
fldefine ZX_BIG_ERR
#define 2X_PHASE_ERR
#define ZX_FREQ_ERR
#define ZX OFFSET
)_FREQ)
1750
64
10
400
32767
200
8430
/* shared variables */
/* Active Filter Variables */
signed int
y3=l, y5=0, y7=0,
/* outputs of 3rd, 5th and 7th resonant filters
y3oldl=0, y3old2=0,
/* past resonant filter outputs
*/
y5oldl=0, y5old2=0,
y7oldl=0, y7old2=0,
yll=0,
ylloldl=0, yllold2=0,
yt=0, ybs=O,
ytoldl=0, ytold2=0,
ybsoldl=0, ybsold2=0,
yrp=0,
wl=0, w2=0 w3=0, w4=0,
zl=0, 22=0 z3=0, z4=0,
hl=0, h2=0 h3=0, h4=0,
wloldl=0 w2oldl=0,
w3oldl=0 w4oldl=0,
zloldl=0 z2oldl=0,
z3oldl=0 z4oldl=0,
nloldl=0 h2oldl=0,
h3oldl=0 h4oldl=0.
/* phase load currents after filtering
iaf,
249
APPENDIX D:
DSP Source Codes
/* reactive current reference
signed int
del = 28924,
dc2',
dc3 = 1986,
dc4 = 30782;
/* DC bus Constants
/* shared for debug only */
unsigned int
phase,
/* current phase angle 0..65535 == 0..360deg */
2X_in_sync,
/* > ZX_SYNC_LIMIT means that sync has been achieved */
ZX_state,
/* state of the zero crossing synchronization process */
sl,s2,s3,s4,s5,s6,
/* magic shift numbers */
v_scale_int;
/* calculated scale factor for voltage to time */
signed int
i_max_err,
/* maximum current error for accurate scaling */
v_max_err,
/* maximum intermediate voltage value */
i_scale_int;
/* calculated scale factor for current to voltage (L/dt) */
signed int
g_con = GRAB_READY,
/* grab control variable */
g_a = o,
/* grab variables */
g_b = 0,
g_c = 0,
g_d = 0,
g_idx = 0 ;
/* PCRINT.C only variables */
unsigned int
adc_index = 0, /* for cyclic readii"* of misc analog values */
Vdc_sc,
/* scaled DC
\k voltage */
Vscale,
/* voltage sc,
factor */
Vdc_count ,
/* Count variable to slow down Vdc PI Loc^
*/
ii-tl_vect ,
/* specific interrupt vector for interrupt
*/
int2_vect ,
/* specific interrupt vector for interrupt
*/
int4_vect ,
/* specific interrupt vector for interrupt 2 */
index,
/* mapping of phase to sine tables */
int!sx3,
/* mapping of phase to sine tables for 3rd */
index90,
/* corresponding sine table index for 90deg leading */
Potl_ref,
/* Reference value from Pot a */
ZX_count,
/* the number of switching cycles between ZX interrupts
ZX_seen,
ZX_cyclea,
ZX_sum,
Vdc32=0, Vdc32_old =0,
Vdc_fl=0,
next_pt = 0, oldest_pt
signed int
sqrt_index,
sparel.
Vdc_err = 0,
Vdc_err_meas
Vdc_sum,
Vac_sum,
af_factor.
0,
/* set to TRUE when a zero crossing is detected
/• count of number of ZXs during averaging */
/* running sum for average */
=1;
/*
/*
/*
/*
/*
/*
/*
/* pointers for running windows rms calculation
index to fcr use with sgrt LUT */
dummy variable */
DC Voltage Error Reference */
true DC Voltage Error reference */
DC Voltage Integrator Sum */
AC RMS Voltage Integrator Sum •/
% of harmonics attempted to be filtered (x32768) */
/* demanded current [adc units] */
Iref,
/* measured currents [adc units] */
ImeasA, imeasB,
/* phase voltage switching times [time units]
V,
/* measured line voltages */
adc_Vacl adc_Vac2,
adc_Vac3 adc Vac4,
/* rms voltage error */
Vac_err,
/* scaled line voltage [adc units] */
Vacl,
/* previous line voltages [adc units] */
Vacloldl Vaclold2,
/* offset for third harmonic injection [time units] */
Voff,
/* calculated 3rd I for deadband comp. [adc units] */
IcalcC,
/* = 65536/3 to trick compiler */
Vthird,
/* time of captured ZX in timer units */
ZX_time,
ZX_time_phase, I time of captured ZX in phase units */
/* scale factor between timer and phase units */
ZX_phase_scale,
250
J ^
APPENDIX D:
-,
DSP Source Codes
ZX_jphase_err, /• difference in phase units (2*16 == 3S0deg) */
ZX_err_sum,
/* integral for frequency control */
A_sat, B_sat, C_sat; /* counters to detect loss of supply */
/* sine tables in tables.c */
extern signed int sin_table_A[TABLE_SIZE];
extern signed int sin_table_B[TABLE_SIZE];
/* sqrt tables in tables.c */
extern signed int sqrt_table_A[TABLE_SIZE];
/it***************************************************************************/
/* calculates log(x) in base 2, returning the floored integer */
unsigned int Iog2(unsigned long int x ) ;
/***************************************************•************************/
/* int2 interrupt
* - EV timer interrupts and pdpint
* - pwm calculations and loading compare registers */
interrupt void iNT2Service(void)
{
int2_vect = reg(EVlVRA); /* reading this register seems to clear it */
/*
reg(PBDATDIF) |= 0x0008; */
/* Set ICB3 High - Debugging */
#if 1
/* Set I0B2 High - Debugging */
reg(PBDATDIR) |= 0x0004;
/* Set I0B2 Low - Debugging */
reg(PBDATDIR) &- OxFFFB;
#endif
/*
reg(PBDATDIR) |= 0x0004; */
if (reg(EVIFRA)&PDPINT)
/* Set I0B2 High - Debugging */
{
PWM_stop();
fault |= GATE_FAULT;
/* second ADC conversion starts when first finishes */
reg(ADCTRLl) = ADCEMULATOR|ADCIEN|ADC_VDCl|ADCSTART|ADC2EN| ADC_VAC2;
/* zero crossing processing */
if (ZX_count > ZX_MAX_COUNT)
if (is_sync
>• TRUE)
/* zero crossing signal lost */
/- only use ZX if need to */
PWM_ ^t>();
fault -,= LOST_SYNC;
ZX_state = ZX_LOST;
ZX_in_sync = 0;
ZX_count = 0;
/* halt modulation */
/* restart searching for sync */
}
if (ZX_state == ZX_LOST)
/* no idea of anything : start freq est.*/
if (is_sync == TRUE) fault |= L0ST_SYNC;
it (ZX_seen == TRUE)
ZX_cycles = 0;
ZX_sum = 0;
ZX_count = 0;
ZX_seen = FALSE;
if (is_sync == TRUE) ZX_state = ZX_EST;
else if (ZX_state == ZX_EST)
/* roughly measure period and average */
if (ZX seen == TRUE)
251
APPENDIX D:
DSP Source Codes
ZX_cycles++;
ZX_sum += ZX_count;
ZX_count = 0;
ZX_seen = FALSE;
/* reset counter */
if (ZX_cycles >= ZX_CYCLE__AVG)
ZX_sum = ZX_sum/ZX_CYCLE_AVG;
phase_step = Oxffff/ZX_sum;
/* approximate frequency */
ZX_sum -= ZX_sum/32;
/* also use for glitch filter */
phase = phase_step + ZX_OFFSET;
/* within phase_step */
ZX_state = ZX_MISC;
/* calculate ZX_phase_scale first
else if (ZX_state == ZX_SYNC) /* accurately measure phase error */
if (ZX seen == TRUE)
ZX_seen = FALSE;
if (ZX_count > ZX sum)
/* ignore glitches */
{
ZX_count = 0;
/* rescale to phase units */
ZX_time_phase = ZX_OFFSET +
(ZX_time>>2)*ZX_phase_scale))»3) ;
/* calculate phase error captured time */
ZX_p:;ase_err = phase - ZX_time_phase;
/* limit size of phase change */
if (ZX_phase_err > ZX_BIG_ERR)
phase -= ZX_BIG_EKX:;
ZX_err_sum = (ZX_err_sum+ZX_BIG_ERR):
integrate phase errors */
else if (ZXjphase_err < -ZX_BIG_ERR)
phase += ZX_BIG_ERR;
ZX_err_sum = (ZX_err_sum-ZX_BIG_ERR)
}
else
{
phase -= ZX_phase_err;
ZX_err_sum = (ZX_err_sum+ZX_phase_err)
ZX_state = ZX_FRE;Q ;
else if (2X_state == ZX_FREQ) /* nudge frequency if needed */
/* if too large, nudge treq (phase_step) */
if (ZX_err_sum > ZX_FREQ_ERR)
phase_step--;
else if (ZX_arr_sum < -ZX_.FREO_ERR)
phase_step++ ;
ZX_State = ZX_LOCK;
else if (ZX_state == ZX_LOCK) /* test to see if still in sync */
if (ZX_in_sync >= ZX_SYNC_LIMIT)
if ((ZX_phase_err>(ZX_PHASE_ERR))||(ZX_phase_err<(ZX_PHASE_ERR)) I
{
/• gone out of sync
*/
PWM_stop();
ZX_in_sync = 0;
in_sync = FALSS;
fault | = LOST_SY17C;
/* could switch to ZX_LOST here for maximum protection
252
APPENDIX D:
DSP Source Codes
}
else
{
}
in_sync = TRUE;
else if ((ZX_phase_err<ZX_PHASE_ERR)&&(ZX_phase_err>-ZX_PHASE_ERR))
{
/* in sync this
cycle */
ZX_in sync++;
else
{
ZX_in_sync = 0;
}
ZX_state = ZX_MISC;
else if (ZX_state == ZX_MISC)
/* THIS IS SLOW!! (-5us) */
ZX_phase_scale = (phase_step«5)/PERIOD;
ZX_state = ZX_SYNC;
/* update phase angle */
phase += phase_step;
index = (phase+phi) » 6 ;
index90 = (phase+phi+16384)>>6;
index3 = (3*phase+phi) >> 6;
/* shuffle old measurements */
Vaclold2 = Vacloldl; Vacloldl = Vacl;
y3old2 = y3oldl; y3oldl = y3;
y5old2 = ySoldl; y5oldl = yS;
y7old2 = y7oldl; y7oldl = y7;
yllold2 = ylloldl; ylloldl = yll;
ytold2 = ytoldl; ytoldl = yt;
ybsold2 = ybsoldl; ybaoldl = ybs;*/
wloldl
w3oldl
zloldl
z3oldl
hloldl
h3oldl
=
=
=
=
=
=
wl;
w3;
zl;
z3;
hi;
h3;
w2oldl
w4oldl
z2oldl
z4oldl
h2oldl
h4oldl
=
=
=
=
=
=
w2;
w4;
z2;
z4;
h2;
h4;
#if 0
/* calculate DC voltage scaling factor */
Vdc_sc = adc_Vdo>s2;
if (adc_vdc < V_DC_MIN -50) /* test for low volts */
{
Vscale = 32767;
fault |= LOW_DC_V0LTS;
PWM_stop();
}
#endif
if (adc_Vdc > (V DC_MAX-S)) /* test for high volts */
{
Vscale = 32767;
fault |= HISC_FAULT;
PWM_StOp();
e}lse
Vscale = fastdivu(v_scale_int,Vdc_sc)<<sl;
/*
reg(PBDATDIR) &= OxFFFB; */
Debugging */
/* Set IOB2 Low -
253
APPENDIX D:
DSP Source Codes
/* read first ADC rssult : should be ready by now */
/*
while ( !((reg(ADCTRL2)6SADCFIF01) == 0x0008) ) ; */ /* Wait until conversion
is complete */
adc_Vacl = ADC_ZERO - get_ADCl();
Potl_ref = get_ADC2();
/* Store ADC_APOT2 */
a_val[AVAL_APOT2] = Potl_ref;
/* third ADC conversion starts when second finishes */
reg (ADCTRL1) = ADCEMULATOR | ADCIEN | ADC_VAC3 | ADCSTART | ADC2 EN | ADC_VAC4 ;
Vdo_count++;
if (op_mode == MODE I_VDC && Vdc_count >9) /* Vdc control instead */
{
Vdc_count = 0;
/* Ramp DC Reference Voltage */
if (Potl_ref > Vdc_ref) Vdc_ref++;
if (Potl_ref < Vdc_ref) Vdc_ref--;*/
/* '
/* NOTE - negative since dec mag -> inc Vdc */
Vdc32 = (adc_Vdc « 5 ) ;
Vdc32_old = (Vdc32 + Vdc32_old);
asm("
SPM 1");
Vdc_fl = ( ((Iong)dc3 * Vdc32_old + (Iong)dc4 * Vdc_fl) >> 16 ),asmT"
SPM 0");
Vdc_err = Vdc_fl - (Vdc_ref << 6) ;
Vdc32_old = Vdc32;
/* Vdc_err = (adc_Vdc - Vdc_ref) << 6;
*/
if (Vdc_err >= 1280)
{
Vdc_err = 1280;
}
else if (Vdc_err <= -1280)
{
Vdc_err = -1280;
Vdc_sum += (Vdc_err » 3 ) ;
if ( (Vdc_err_meas > 4) || (Vdc_err_meas < -4) )
Vdc err = Vdc err meas;
}
*/
"
~
/* clamp integrator sum */
if (Vdc_sum > 5000)
{
Vdc sum = 5000;
}
else if (Vdc sum < -5000)
{
Vdc sum = -5000;
}
/*if ( (Vdc_err > 1) || (Vdc_err < -1) )
dc2 = (200 * Vdc err +• Vdc sum);
}
else
{
dc2 = (Vdc err + Vdc sum) ;
}*/
mag_bak = (Vdc_err<<4) + (Vdc_sum);
/* asm(" SPM 2");
*//* auto left shift product by 4 */
/* magjbak = ((Iong)dc2 * (long)dcl) » 16;
254
APPENDIX D:
DSP Source Codes
asm{"
SPM 0") ;*/
/* disable auto left shift */
/* Ramp Current Reference */
if (mag_bak > (mag+4)) mag+=4;
if (magjbak < (mag-4)) mag-=4;*/
mag = mag_bak;
/* clamp magnitude */
if (mag > MAG_MAX)
mag = MAG MAX;
}
else if (mag < -MAG_MAX)
mag = -MAG_MAX;
}
/*
);
•/
Vacl = ( ((sin_table_A[index] + 4L) » 3 )+ ((sin_table_A[index3] + 32L) >> 6)
Vacl = (-9039L * adc_Vacl + 128L) » 8;
1
%
if (af_factor > 0)
I
/*3rd harmonic resonant filter */
W4 = ( (w3oldl + 3 ) » 4) + w4oldl;
w2 = ( (wloldl + 8 ) » 4) + w2oldl;
y3 = ( (3136 * Vacl + 1048576) >> 21 ) + w4;
W3 = ( (100364L * Vacl - 397750L * y3 + 1048576L) » 21 ) + w2;
Wl - (-2379089L * y3 + 524288L) » 20;
;.j;
/*5th harmonic resonant filter */
z4 = ( (z3oldl + 8) » 4) + z4oldl;
z2 = ( (zloldl + S) >> 4) + z2oldl;
y5 = ( (3128 * Vacl + 1048576) » 21 ) + z4;
z3 = ( (100100L * Vacl - 925089L * yS + 1048576L) >> 21 ) + z2;
zl = (-6599913L * y5 + 524288L) » 20;
/*7th harmonic resonant filter */
h4 = ( (h3oldl + 8) >> 4) + h4oldl;
h2 = ( (hloidl + 8) >> 4) + h2oldl;
y7 = ! (3116 * Vacl + 1048576) » 21 ) + h4;
h3 = ( (99706L * Vacl - 1713503L * y7 + 1048576L) »
hi = (-12910380L * y7 + 524288L) » 20;
21 ) + h2;
/* resonant filters */
/*
y3 = (1046L * (Vacl - Vaclold2) + 2085762L * y3oldl 524288L) » 20;
y5 = (2046L * (Vacl - Vaclold2) + 4138544L * y5oldl 1048576L) » 21;
y7 = (20V8IJ * (Vacl - Vaclold2) + 4089235L * y7oldl 1048576L) » 21;
yll = (4103L * (Vacl - Vaclold2) + 393861SL * ylloldl
1048576L) » 21;
*/
104 64 84L * y3old2 +
2092979L * y5old2 +
2092996L * y7old2 +
- 2088945L * yllold2 +
/* resonant filters with lead compensation */
/*
y3 = (2040L * Vacl - 35L*Vacloldl - 2075L*Vaclold2 + 2083684L * y3oldl 1044396L * y3old2 + 524288L) » 20;
y5 = (3S95L * Vacl - 190L*Vacloldl - 4085L*Vaclold2 + 4134430L * y5oldl 2088814L * y5old2 + 1048576L) » 21;
y7 = (3G25L * Vacl - 365L*Vacloldl - 3991L*Vaclold2 + 4085187L * y7oldl 2088847L * y7old2 + 1048576L) » 21;
V
yt = y3 + y5 + y7 + {(950L * Vacl +32768) » 16);
yt = y3 +• y5 * y7 ;
255
ybs = (522G46L * (yt + ytold2) + 10447771, * (ybsoldl - ytoldl) - 521005L •
ybsold2 + 2S2144L) » 19;
*/
reg(PBDATDIR) |= 0x0004;
/* Set IOB2 High - Debugging */
while ( !((reg(ADCTRL2)iSADCFIF01) == 0x0008) ),/* Wait until conversion
is complete */
reg(PBDATDIR) &= OxFFFB;
/* Set IOB2 Low - Debugging •/
/* read second ADC result : should be ready by now */
adc_Vdc = get_ADCl() - ADC_ZERO;
a_val[AVAL_VDC1] = adc_Vdc + ADC_ZKRO;
adc_Vac2 = ADC_ZERO - get_ADC2() ;
/* calculate phase current references */
Iref = (int) (((long)sin_table_A[index]*(long)mag)>>16);
Iref = Iref >> 3;
#if 1
Iref = 0;
/*disable DC bus control for multilevel */
#endif
/* Reactive Power Compensation */
if iis_RPC)
|
if (nextjpt < 200)
t
I
{
next_pt++;
}
•-jv
else
{
next_pt = 0;
}
if (oldest_pt < 200)
oldest_pt++;
}
else
{
oldest_pt = 0;
}
Vacl_sq[next_pt] = adc_Vacl * adc_Vacl;
sumsq = sumsq + Vacl_sq[next_pt] - Vacl_sq[oldest_pt];
sqrt_index = (sumsq - 370O0O0L + 8192L) >> 14;
if (sqrt_index >= TABLE_SIZE)
sqrt_iudex = TABLE_SIZE - 1;
else if (sqrt_index < 0)
sqrt_index = 0 ;
Vac_err = ((5355L * Vac_ref) >> 8) - sqrt_table_A[sqrt_index]
if (Vac_err >= 1050)
{
Vac_err = 1050;
}
else if (Vac_err <= -1050)
{
Vac_err = -1050;
}
Vac_sum += (Vac_err +16L)>>5
;
256
APPENDIX D:
DSP Source Codes
if (Vac sum > 7520)
{
Vac sum = 7520;
}
else if (Vac sum < -7520)
{
Vac sum = -7520;
}
yrp = Vac_sum +• ((47L * Vac_err + ID
if
»
1);
(yxp > 7520)
yrp = 7520;
else if
(yrp < -7520)
yrp = -7520;
yrp = (yrp «
1);
iq = (int) (((long)sin_table_A[index90]*(long)yrp)»16);
iq = iq >> 3;
Iref -= iq;
/* note subtraction due to current ref direction */
/* Factor the % demanded harmonic compensation */
iaf = ( ((long)af_factor* (long)yt) » 1 ••! ;
1
if (is_AF)
{
Iref += iaf;
I
/* output to DAC channel 0 */
/* sampling frequency is 2 times the switching frequency since there's
two interrupts per switching period */
V = Iref + DAC_ZER0;
if (is_modulating)
load_DAC(DAC0,V);
else
load_DAC(DACO,DAC_ZERO);
update_DACS();
/ * read third ADC result : should be ready by now * /
adc_Vac3 = ADC_ZER0 - get_ADC2 () ,adc_Vac4 = ADC_ZER0 - get_ADCl();
if (g_con == GRAB_GO)
if (g_idx < G_C0UNT)
/*g[g_idx][0]=phase_step;*/ / * need phase-step t o calc rms * /
g[g_idx][0]=yrp;
g (g_idx] tl] =adc_Vacl;
g[g_idx][2]=adc_Vac2;
g tg_idJ-0 [3] =adc_Vac3;
g [g_idx] [4] =adc_Vac4 ;
I
APPENDIX D:
DSP Source Codes
g[g_idx] [2]=yS;
g[g_idx][3]=y7;
g[g_idx] [4] =yt;
g[g_idx] [5]=wl;
glg_idx] [6]=w2;
g[g__idx] [7]=w3;
g[g_idx] [8]=w4;
glg_idx][5]=ybs ;
g [g_idx] [5] =sumsq»14 ;
g [g_idx] [6] =sumsq - (((long)g[g_idx] [4]
g [g_idx] [7] =Vac_err;
g [g_idx] [8] =Vac_sum;
g[g_idx] [9] =yrp;
g[g_idx][io]=ig;
g[g_idx][ll]=lref;
*/
g [g__idx] [6]=adc_Vdc;
g [g_idx] [7]=Vdc err;
g[g idx] [8]=lref;
g [g_idx] [10]=mag,g [g_idx] [ll]=Vdc_fl;
g_idx++;
else
g_con = GRAB
g idx = 0 ;
DONE;
#if 0
/* Sudden increase in AC reference voltage
if (g idx == 1000)
{
Vac_ref += 15;
#endif
/* ready for next interrupt */
reg(ADCTRLl) = ADCEMULATOR|ADClEN|ADC2EN|ADC_VACl|ADC_AP0T2;
#if 1
/* Set IOB2 High - Debugging */
reg(PBDATDIR) |= 0x0004;
/* Set IOB2 Low - Debugging */
reg(PBDATDIR) &= OxFFFB;
#endif
/* Set IOB3 Low - Debugging */
/*
reg(PBDATDIR> &* 0xFFF7; */
} /* end timerl interrupt */
/* zero crossing capture interrupt */
interrupt void INT4Service(void)
{
/*
/*
int4_vect = regtEVIVRC);
reg(PBDATDIR) |= 0x0004; */
ZX_seen = TRUE;
ZX_time = PERIOD - reg(CAP3FIFO);
reg(PBDATDIR) t= OxFFFB; */
/*ZX_tiitie = PERIOD - reg(CAP2FIFO) ;
/* Set IOB2 High - Debugging */
/* ZX from VAB Crossing */
/* Set IOB2 Low - Debugging */
ZX from V_AUX * /
} / * end INT4Service * /
/* sets up registers for PWM */
/* need to initialize period_2,raax_time,dead_band before calling */
void PWM Init(void)
258
APPENDIX D:
DSP Source Codes
int i;
reg(EVIFRA) = PDPINT;
ADC_clear();
reg(ADCTRL1) = ADCEMULATOR| ADC1EN|ADC2EN| ADC_VACl| ADC_AP0T2;
reg(ADCTRL2) = ADCEVSOC|ADCPSCALE; /*0x0403;*/
reg(COMCON) = 0x2bl7; /* disable full compare - un-shadows registers */
reg(TlCON) = 0xa80g; /* stop timer */
reg(SACTR) = 0x0000;
reg(ACTR) = 0x0000;
reg(CAPFIFO) = OxOOff; /* clear the fito capture inputs */
ImeasA
ImeasB
IcalcC
0;
0;
0;
/* calculate sin tables */
nton_sin_table (sin_table_A,TABLE_SIZE, 32767, 0, 0) ; /* i n pwmjump.h *./
mon_sin_table(sin_table_B,TABLE_SIZE, 32767,-21845,0);
/* calculate sqrt tables */
sqrt_table(sqrt_table_A,TABLE_SIZE,3700000L,(1L «
24)); /* in sqrttab.h */
reg(GPTCON) = 0x047a; /* 000 00 10 00 1 11 10 10 */
/* timer control
|
| | | | j | +- T1CMPR active high
| | | | +- T2CMPR active high
j I j +- T3CMPR forced high
| J +-- compare output enable
j \- TltoADC
+- T2toADC starts on period
|
+- T3toADC
+- time? status *Ai.ts */
/* action control register */
reg(ACTR) = 0x0000; /* 0 000 00 00 00 00 00 00 */
/*
I
I
I II II I
*
I I +--+--+--+--+--+- all pwm pins forced low
*
| +- space vector bits
*
+- space vector disabled */
/* simple action control register */
reg(SACTR) = 0x0000; /* n^00 0000 00 00 00 00 */
/*
\ / I I I
*
\
/
| +--+- all pwm pins forced low
*
\/
+- sample and hold active high
*
- reserved */
/* deadband timer control */
reg(DBTCON) = OxO0e0|(DEADCNT<<8); /* xxxx xxxx 111 00 000 */
+- reserved
\
/ j +- prescaler
\ /
+- enabled all pins
+- deadband time */
/*
I
reg(CMPRl) = PERI0D_2;
reg(CMPR2) = PERIOD_2;
reg(CMPR3) = PERIOD_2;
reg(SCMPRl) = 0;
reg(SCMPR2) = 0;
reg(SCMPR3) = 0;
/* compare control register */
reg(COMCON) = 0x2bl7; /* 0 01 0 10 1 1 0 00 10 111 */
,- reg(COMCON) = 0xabl7; */ /• 1 01 r 10 1 1 0 00 10 111 */
I I | |
| +- pins in pwm mode
j I j j +- reload SACTR immediately
j j I +- reload SCMPRx on zero or period
| I +- use timerl
| +- simple compare enabled
j j +- full compare enabled
j +- reload ACTR immediately
+- space vector mode disabled
+- CMPRx reload on zero or period
259
reg(T2PR) = PERIOD-1;
reg(T2CNT) = 0;
reg(T2CHPR) = 3*PERIOD/4;
•reg(T2CON) = 0x9082; /* 10 010 000 1 0 00 00 1 0 */
/* timer 2
||
I I +- reserved
| j I +- timer compare enable
j I +- timer compare reload on zero
j +- clock source - internal
+- timer enable
|
+- enable on timer 1 enable
+- input clock prescaler
+- count mode selection - continuous up mode
+- emulation control bits - timer continues */
reg(TlPR) = PERIOD;
reg(TlCNT) = 0;
/* NOTE: must start timer the first time, and load the various registers
* which are shadowed and only reload on timer overflow */
reg(TlCON) = Oxa8O2; /* 10 101 000 0 0 00 00 1 0 */
/* timer 1
| | | | +- reserved
I I j +- timer compare enable
j I +- timer compare reload on zero
I +- clock scarce - internal
+- timer enable
+- reserved
+- input clock prescaler
+- count mode selection - continuous up mode
+- emulation control bits - timer continues */
/* enable timer 1 period and undeflow interrupt
reg(EVIFRA) = (TIPINT|T1UFINT);
reg(EVIMRA) |= (TIPINT|TIUFINT);
reg(EVIMRB) = 0;
/* enable INT2 interrupt */
reg(IFR) |= ENABLE_INT2;
reg(IMR) j= ENABLE_INT2;
/* start timer 1 */
reg(TlCON) = 0xa842; /* 10 101 000 0 1 00 00 1 0 */
/* timer 1
||
| | +- reserved
| | | +- timer compare enable
| | +- timer compare reload on zero
I +- clock source - internal
+- timer enable
|
+- reserved
+- input clock prescaler
+- count mode selection - continuous up mode
+- emulation control bits - timer continues */
reg(CAPCON) = 0x900a;
/* capture control
/* 1 00 1 0 0 0 0 00 00 10 10 */
| | | | j | | | | +--+- negative edge (negation on
IIB)
| I I I I I +--+- no edge detection
I j I j | +- cap4 starts adc
I I j +-+- cap 34/12 use timer 2
j +-+- enable cap 3, disable cap 4
+- disable cap 12 / disable QEP
+- don't reset capture unit */
if (is_sync == TRUE) /* don't need ZX interrupt if running as current source */
reg(OCRB* |= 0x0040; /* select CAP3 over dig I/O */
reg(EVIFRC) = OxOOOf; /* reset capture input flags */
/* enable capture 3 input interrupt
reg(EVIMRC) = CAP3INT;
/*reg(EVi;iRC) = CAP2INT; *//* enable capture 2 input interrupt */
/* enable interrupt 4 */
reo(IFR) |= ENABLE_INT4;
reg(IMR) |= ENABLE_INT4;
phase
0;
phi = 0;
260
»-*.-=— _ '.
APPENDIX D:
DSP Source Codes
phase_step = PHASE_STEP;
index = 0;
mag = 0;
Vdc_ref = 0;
ZX_state = ZX_LOST;
ZX_count = 0;
ZX_in_sync = 0;
ZX_seeO = FALSE;
ZX_cycles = 0;
ZX_gum = 0;
ZX_phase_err = 0 ;
ZX_err_sum = 0;
in_aync = FALSE;
A_sat = 0;
B_sat = 0;
C_sat = 0;
af_factor = 0;
is_modulating = FALSE;
g[0] [0] = 328;
/* RMS & average calculation needs this oth.-... wise
will crash system */
sumsq = 0;
for (i=0; i < 201;
{
Vacl sq[i] = 0;
}
next_pt = 0;
oldest_pt = 1;
55 = Iog2((long)(32767/I_3CALE+0.5));
56 = Iog2((long)(65535/V_SCALE+0.5));
v_scale_int = (unsigned int) (V_SCALE* (l«sS)+0. 5) ;
i_scale2int = (signed int) (I_SCALE* (I«s5)+0. 5) ;
52 = Iog2((long)(Vdc_MAX/25O.O/V_DC_SC+0.S));
si = Iog2((long)(Vdc_MIN*32O00.0/(V_DC_SC*v_scaIe_int)+0.5))
53 = 16 - si - s2 - 36;
s4 = 14 - s5;
i_max_err =
v_max_err =
;
if ( (s3 > 4) | | ((Sl*s2*s3*s4*s5*s6) < 0))
- s2;
{
fault |= SCALE_ERROR;
}
} /* end PWM_init */
/* starts modulation */
/* due to deadband/ACT",
void PKM_Start(void)
- re-initializes the entire PWM timers stuff */
{
unsigned int. iu v
int_mask = reg(EVlnRA);
reg(EVIMRA) &= ~(TIPINT|TIUFINT); /* disable PWM interrupt */
/* force PWM outputs low before initializing them */
reg(COMCON) = 0x2bl7; /* disable full compare outputs */
reg(TlCON) = 0xa806; /* stop timer */
reg(SACTR) = 0x0000;
reg(ACTR) = OxGOOO;
reg(GPTCON) = 0x047a; /• 000 00 10 00 1 11 10 10 */
reg(ACTR) = 0x0666; /* 0 000 01 10 01 10 01 10 */'
reg(SACTR) = 0x0020; /* 0000 0000 00 10 00 00 */
reg(DBTCON) = 0x00e0| (DEADCNT«8) ; /* xxxx xxxx 111 00 000 */
reg(CMPRl) = PSRIOD_2;
reg(CMPR2) ~ PERIOD_2;
reg(CMPR3) - PERIOD~2;
reg(SCMPRl) = 0;
reg(SCMPR2) = 0;
reg(SCMPR3) = 0;
/* compare control register */
261
APPENDIX D:
DSP Source Codes
reg(COMCON) = 0x2bl7; /* 0 01 0 10 1 1 0 00 10 111 */
/•reg(COMCON) = 0xabl7; */ /• 1 01 0 10 1 1 0 00 10 111 */
reg(T2PR) = PERIOD-1;
/* <<< stop timer 1 & 2 */
reg(TJCON) = 0xa802r /* "*0 101 000 0 0 00 00 i 0 */
reg(T?CNT) = 0;
reg(T2CMPR) = 3*PERIOD/4;
reg(T2C0N} = 0x9082; /* 10 010 000 1 0 00 00 1 0 */
reg(TlPR) = PERIOD;
reg(TlCNT) = 0;
reg(TlCON) = 0xa802; /* 10 101 000 0 0 00 00 1 O */
reg(TlCON) = 0xa842; /* 10 101 000 0 1 00 00 1 0 */
mag = 0;
Vdc_ref = 0;
Vthird = (65S3S1/3);
ia_modulating = TRUE;
A_sat = 0;
B_sat = 0;
C_sat = 0;
/* set up registersfor ADC measurements */
reg(ADCTRL1) = ADCEMULATOR|ADCIEN|ADC2EN|ADC_VAC1|ADC_APOT2;
reg(ADCTRL2) = ADCEVSOC|ADCPSCALE; /*0x0403;*/
/* re-enable interrupts */
reg(EVIFRA) = (T1PINT|T1UFINT);
reg(EVIMRA) = int_mask;
} /* end PWM_start */
/*************•*•************************************************************/
/* sets up level comparison interrupt */
void Fault_init(unsigned int fault_tnask)
{
fault = NO_FAULT;
/* on IIB, LC_VDC1 uses XINT1 and LC_I_MOD uses PDPINT.
*/
#if 0
/* initialize the level comparison interrupts */
if (fault_mask&LC_VDCl)
reg(XINT2) = 0x8004; /* clear interrupt flag, rising edge triggered */
if (fault_mask&LC_I_MOD)
reg(XINT3) = 0x8004; /* clear interrupt flag, rising edge triggered */
}
/* enable INT1 interrupt */
if (fault_mask&(LC_VDC1|LC_I_MOD))
reg(IFR) |= ENABLE_INT1;
reg(IMR) j= ENABLE_INT1;
if (fault_mask&LC_VDCl)
reg(XINT2) |= 0x0001; /* enable interrupt
*/
if (fault_mask£cLC_I_MOD) reg(XINT3) |= 0x0001; /* enable interrupt */
#endif
} /* end Fault_init */
/* services the XINT2 and XINT3 interrupts driven by level comparisons */
interrupt void XlNT2_int(void)
PWM_stop();
fault |= LC_VDC1;
} /* end XINT2_int */
262
APPENDIX D:
DSP Source Codes
interrupt void XINT3_int(void1
PWM_stop();
f a u l t |= LC I_MOD;
} /* end XINT3_int~*/
/***********•*•***,********•<
•**************•********•**«*************««****«/
/* clears the faults and checks that they have cleared, returns fault status */
unsigned int check_faults(unsigned int fault_mosk)
unsigned int val = NO_FAULT;
if (fault_mask&GATE FAULT)
{
reg(EVIFRA) = 0x0001; /* clear and test for return */
val = (reg(EVIFRA)&0x0001)?GATE_FAULT:O; /* for PDPINT */
/*
/* test LC__VDC1 pin (XINT2) */
if (fault tnask&LC VDC1)
{
val |= (reg(XINT2)&Ox0040)?LC VDC1:O;
} */
/*
/* test LC_I_MOD pin (XINT3) */
if (fault mask&LC I MOD)
{
W
val |= (reg(XINT3)&0x0O4O)?LC I MOD:0;
/* test level of ZX_in_sync for re-synchronization */
if (fault_mask&LOST SYNC)
{
val |= (ZX_in_sync<ZX_SYNC_LIMIT)?LOST_SYNC:0;
/* clear X_sat counters for lost supply */
if (fault_mask&LOST_SUPPLY)
A_sat = 0;
B_sat = 0;
C_sat = 0;
/* test DC voltage */
if (fault_mask&LOW_DC_VOLTS)
val
(adc_Vdc<=V_DC_MIN)?LOW_DC_VOLTS:0;
fault = val;
return val&fault_mask;
} /* end check_faults */
I
/* calculates log(x) in base 2, returning the floored integer */
unsigned int Iog2(unsigned long int x)
I
unsigned int i = 0;
while (x > 1)
X »=
1;
return i;
} /* end Iog2 */
263
BIBLIOGRAPHY
[I]
D. J. Marsden, "Variable-Voltage Diode Convenor Rolling-Stock
Transformers to Control DC Traction Motors", IEE Proceedings-B, Vol. 139,
No. 3, pp. 197-208, May 1992.
[2]
R. S. Hill, "Electric Railway Traction - Part 3 Traction Power Supplies",
Power Engineering Journal, pp. 275-286, Dec 1994.
[3]
C. Courtois, "Why the 2 x 25kV Alternative?" in Conf. Rec. IEE Colloquium
on SOW Autotramformer Traction Supply Systems - the French Experience,
pp. 1/1-1/4, 1993.
[4]
A. J. Griffin, "Methods of Improving the Voltage Regulation on 25kV Electric
Railways", in Conf. Rec. International Conference on Main Line Railway
Electrification, pp. 252-259, 1989.
[5]
R. E. Morrison, K. Warburton, D. J. Young, and D. Hackwell, "The Use of
Static Shunt Compensation to Upgrade Existing Electrified Railways", in
Conf. Rec. International Conference on Main Line Railway Electrification, pp.
232-235,1989.
[6]
J. J. Burke, A. P. Engel, S. R. Gilligan, and N. A. Mincer, "Increasing the
Power System Capacity of the 50kV Black Mesa and Lake Powell Railroad
through Harmonic Filtering and Series Compensation", IEEE Transactions on
Power Apparatus and Systems, Vol. PAS-98, No. 4, pp. 1268-1274, Jul/Aug
1979.
[7]
R. E. Morrison, K. Warburton, A. Singh, and D. J. Young, "The Application
of Shunt Compensation on AC Railways", in Conf. Rec. IEE International
Conference on Electric Railway Systems for a New Century, pp. 119-125,
1987.
[8]
R. E. Morrison, "Parameters that Influence Power Quality on Industrial
Frequency AC Traction Systems", in Conf. Rec. IEEE Power Engineeing
Society Summer Meeting, 2001.
[9]
R. E. Morrison and J. C. W. Corcoran, 'Specification of an Overvoltage
Damping Filter for the National Railways of Zimbabwe", IEE Proceedings-B,
Vol. 136, No. 6, pp. 249-256, Nov 1989.
[10]
P. J. Donnison, "The Design and Development cf the Class 91 Locomotive",
in Conf. Rec. International Conference on Main Line Railway Electrification,
pp. 294-298,1989.
[II]
P. C. Bennett, "Aspects of the Design, Construction and Testing of BRB's
Class 90 and 91 Locomotive Transformers", in Conf. Rec. International
Conference on Main Line Railway Electrification, pp. 279-283,1989.
264
Bibliography
[12]
A. S. King, "25kV A.C. Locomotives", in Conf. Rec. IEE International
Conference on Electric Railway Systems for a New Century, pp. 78-80, 1987.
[13]
P. J. Donnison, "Power Factor and Harmonic Aspects of AC Supplied DC
Drives for Traction", in Conf. Rec. IEE International Conference on Electric
Railway Systems for a New Century, yip. 132-136, 1987.
[14]
D. J. Marsden, "Fixed-Voltage Thyristor Converter Rolling-Stock
Transformers to Control DC Traction Motors", IEE Proceedings-B, Vol. 139,
No. 3, pp. 197-208, May 1992.
[15]
R. J. Hill, "Electric Railway Traction - Part 1 Electric Traction and DC
Traction Motor Drives", Power Engineering Journal, pp. 47-56, Feb 1994.
[16]
R. E. Morrison, "Electric Traction System Design", Centre for Electrical
Power Engineering, Monash University, 1999.
[17]
A. M. Walczyna and R. E. Phillpotts, "Simulation of AC/DC Traction
Converters and Drives for the Calculation of Input Power Characteristics", in
Conf Rec. International Conference on Main Line Railway Electrification, pp.
373-377,1989.
[18]
W. S. Chan, B. Mellitt, and N. B. Rambukwella, "Whole System Simulator for
AC Railways", in Conf. Rec. International Conference on Main Line Railway
Electrification, pp. 368-372,1989.
[19]
R. Graf, "Problems Associated with the Phase-Angle Control of Locomotives
in Contact Wire Networks", Brown Boveri Review, Vol. 64, No. 12, pp. 761766, 1977.
[20]
R. E. Morrison and M. J. Barlow, "Continuous Overvoltages on A.C. Traction
Systems", IEEE Transactions on Power Apparatus and Systems, Vol. PAS102, No. 5, pp. 1211-1217, May 1983.
[21]
T. Petersson and M. Eitzmann, "Railway System Oscillatory Overvoltages", in
Conf. Rec. IEE International Conference on Electric Railway Systems for a
New Century, pp. 194-198,1987.
[22]
"Seminar on Electrification ", Japan International Cooperation Agency, 1982.
[23]
L. Gyugyi, "Power Electronics in Electric Utilities: Static Var Compensators",
Proceedings of the IEEE, Vol. 76, No. 4, pp. 483-494, Apr 1988.
[24]
L. Hu, "The Application of Reactive Power Compensation to AC Electrified
Railway Systems", PhD Thesis, Staffordshire University, 1995
[25]
L. Hu, R. E. Morrison, and D. J. Young, "Reduction of Harmonic Distortion
and Improvement of Voltage Form Factor in Compensated Railway Systems
by Means of a Single Arm Filter", in Conf. Rec. IEEE International
Conference on Harmonics in Power Systems, pp. 83-88,1992.
265
Bibliography
[26]
L. Hu and R. E. Morrison, "Comparison of Physical and Digital Modelling
Techniques for a Compensated Railway System", Advances in Engineering
Software, Vol. 19, pp. 61-67,1994.
[27]
L. Hu and R. E. Morrison, "Digital Simulation Models of Electrical
Locomotives", in Conf. Rec. 29th Universities Power Engineering
Conference, pp. 696-699, 1994.
[28]
L. Hu, R. E. Morrison, K. Schipman, and J. J. Price, "The Effects of Distortion
Due to 25kV Locomotive Having PWM Converters to Condition the Input
Current Waveform", in Conf. Rec. IEEE Conference on Harmonics and Power
Quality,??. 128-132,1996.
[29]
P. Cesario, G. Sciutto, C. Rossi, and B. Mellitt, "Digital Simulation for
Solution of Oscillatory Overvoltage Problems in AC Railroad Electrification",
in Conf. Rec. International Conference on Main Line Railway Electrification,
pp. 356-362, 1989.
[30]
R. E. Morrison, L. Hu, S. B. Tennakoon, P. Verde, and P. Caramia,
"Measurement of Voltage Distortion due to AC Locomotives Having PWM
Input Converters", in Conf Rec. 10th IMEKO, TC-4 Developments in digital
measuring instrumentation, 1998.
[31]
J. Holtz and H. J. Klein, "The Propagation of Harmonic Currents Generated by
Inverter-Fed Locomotives in the Distributed Overhead Supply System", IEEE
Transactions on Power Electronics, Vol. 4, No. 2, pp. 168-174, Apr 1989.
[32]
R. Granell, "Substation for Feeding the 60Hz Contact Wire of the Korean
State Railways", Brown Boveri Review, Vol. 64, No. 12, pp. 755-760, 1977.
[33]
B. Mellitt, J. Allan, Z. Y. Shao, W. B. Johnston, A. Hooper, and M. R.
Denley, "Harmonic Characteristics of Traction Loads on New Zealand's
Newly Electrified North Island Line", in Conf Rec. 10th Internation
Conference on Electricity Distribution, pp. 392-396, 1989.
[34]
N. G. Hingorani, "Role of FACTS in a Deregulated Market", in Conf. Rec.
IEEE Power Engineering Society Summer Meeting, pp. 1463-1467, 2000.
[35]
N. G. Hingorani, "Introducing custom power", IEEE Spectrum, Vol. 32, No. 6,
pp. 41-48, Jun 1995.
[36]
N. Hingorani, "Flexible AC Transmission", IEEE Spectrum, Vol. 30, No. 4,
pp. 40-45, Apr 1993.
[37]
L. Gyugyi, "Dynamic Compensation of AC Transmission Lines by Solid-State
Synchronous Voltage Sources", IEEE Transactions on Power Delivery, Vol.
9, No. 2, pp. 904-911, Apr 1994.
[38]
A. Edris, "FACTS Technology Development: An Update", IEEE Power
Engineering Review, Vol. 20, No. 3, pp. 4-9, Mar 2000.
266
Bibliography
i:
[39]
D. J. Hanson, M. L. Woodhouse, C. Horwil, D. R. Monkhouse, and M. M.
Osborne, "STATCOM: A New Era of Reactive Compensation", Power
Engineering Journal, Vol. 16, No. 3, pp. 151-160, Jun 2002.
[40]
C. Schauder, M. Gernhardt, E. Stacey, T. Lemak, L. Gyugyi, T. W. Cease, and
A. Edris, "Operation of+/-100 MVAR TVA STATCON", IEEE Transactions
on Power Delivery, Vol. 12, No. 4, pp. 1805-1811, Oct 1997.
[41]
S. Mori, K. Matsuno, T. Hasegawa, S. Ohnishi, M. Takeda, M. Seto, S.
Murakami, and F. Ishiguro, "Development of A Large Static VAr Generator
Using Self-Commutated Inverters for Improving Power System Stability",
IEEE Transactions on Power Systems, Vol. 8, No. 1, pp. 371-377, Feb 1993.
[42]
A.-A. Edris, S. Zelingher, L. Gyugyi, and L. J. Kovalsky, "Squeezing More
Power from the Grid", IEEE Power Engineering Review, Vol. 22, No. 6, pp.
4-6, Jun 2002.
[43]
L. Gyugyi, N. G. Hingorani, P. R. Nannery, and N. Tai, "Advanced Static VAr
Compensator Using Gate Turn-Off Thyristors for Utility Applications", in
Conf. Rec. CIGRE International Conference on Large High Voltage Electric
Systems, pp. 23-203,1990.
[44]
C. W. Edwards, K. E. Mattern, E. J. Stacey, P. R. Nannery, and J. Gubemick,
"Advanced State VAr Generator Employing GTO Thyristors", IEEE
Transactions on Power Delivery, Vol. 3, No. 4, pp. 1622-1627, Oct 1988.
[45]
K. K. Sen, "STATCOM - STATic synchronous COMpensator: Theory,
Modeling, and Applications", in Conf. Rec. IEEE Power Engineering Society
Winter Meeting, pp. 1177-1183,1999.
[46]
D. R. Trainer, S. B. Tennakoon, and R. E. Morrison, "Analysis of GTO-Based
Static VAr Compensators", IEE Proceedings. Electric Power Applications,
Vol. 141, No. 6, pp. 293-302, Nov 1994.
[47]
D. Soto and T. C. Green, "A Comparison of High-Power Converter
Topologies for the Implementation of FACTS Controllers", IEEE
Transactions on Industrial Electronics, Vol. 49, No. 5, pp. 1072-1080, Oct
2002.
[48]
D. J. Hanson, C. Horwill, B. D. Gemmell, and D. R. Monkhouse, "A
STATCOM-Based Relocatable SVC Project in the UK for National Grid", in
Conf. Rec. IEEE Power Engineering Society Winter Meeting, pp. 532-537,
2002.
[49]
J. D. Ainsworth, M. Davies, P. J. Fitz, K. E. Owen, and D. R. Trainer, "Static
VAr Compensator (STATCOM) Based on Single-Phase Chain Circuit
Converters", IEE Proceedings. Generation, Transmission & Distribution, Vol.
145, No. 4, pp. 381-386, Jul 1998.
[50]
L. Xu, V. G. Agelidis, and E. Acha, "Development Considerations of DSPControlled PWM VSC-Based STATCOM", IEE Proceedings. Electric Power
Applications, Vol. 148, No. 5, pp. 449-455, Sep 2001.
267
Bibliography
[51]
0. Anaya-Lara and E. Acha, "Modeling and Analysis of Custom Power
Systems by PSCAD/EMTDC", IEEE Transactions on Power Delivery, Vol.
17, No. 1, pp. 266-272, Jan 2002.
[52]
L. H. Wa?ker, "10-MW GTO Converter for Battery Peaking Service", IEEE
Transactions on Industry Applications, Vol. 26, No. 1, pp. 63-72, Jan/Feb
1990.
[53]
S. R. Bowes, "Novel Approach to the Analysis and Synthesis of Modulation
Processes in Power Convertors", IEE Proceedings, Vol. 122, No. 5, pp. 507513, May 1975.
[54]
D. G. Holmes, "A General Analytical Method for Determining the Theoretical
Harmonic Components of Carrier Based PWM Strategies", in Conf. Rec. IEEE
Industry Applications Conference, pp. 1207-1214,1998.
[55]
S.-Y. Jung, T.-H. Kim, S.-I. Moon, and B.-M. Han, "Analysis and Control of
DSTATCOM for a Line Voltage Regulation", in Conf. Rec. IEEE Power
Engineering Society Winter Meeting, pp. 729-734,2002.
[56]
P. S. Sensarma, K. R. Padiyar, and V. Ramanarayanan, "A STATCOM for
Composite Power Line Conditioning", in Conf. Rec. IEEE International
Conference on Industrial Technology 2000, pp. 542-547, 2000.
[57]
D. Sutanto, L. A. Snider, and K. L. Mok, "EMTP Simulation of A STATCOM
Using Hysteresis Current Control", in Conf. Rec. IEEE International
Conference on Power Electronics andDrive Systems., pp. 531-535,1999.
[58]
P. Giroux, G. Sybille, and H. Le-Huy, "Modeling and Simulation of A
Distribution STATCOM Using Simulink's Power System Blockset", in Conf.
Rec. 27th Annual Conference of the IEEE Industrial Electronics Society, pp.
990-994,2001.
[59]
C. K. Sao, P. W. Lehn, M. R. Iravani, and J. A. Martinez, "A Benchmark
System for Digital Time-Domain Simulation of a Pulse-Width-Modulated DSTATCOM", IEEE Transactions on Power Delivery, Vol. 17, No. 4, pp.
1113-1120, Oct 2002.
[60]
J. Sun, D. Czarkowski, and Z. Zabar, "Voltage Flicker Mitigation Using
PWM-Based Distribution STATCOM", in Conf. Rec. IEEE Power
Engineering Society Summer Meeting, pp. 616-621, 2002.
[61]
B. N. Singh, A. Chandra, and K. Al-Haddad, "DSP-Based Indirect-CurrentControlled STATCOM Part II: Multifunctional Capabilities", IEE
Proceedings. Electric Power Applications, Vol. 147, No. 2, pp. 113-118, Mar
2000.
[62]
B. N. Singh, A. Chandra, and K. Al-Haddad, "DSP-Based Indirect-CurrentControlled STATCOM Part I: Evaluation of Current Control Techniques",
IEE Proceedings. Electric Power Applications, Vol. 147, No. 2, pp. 107-112,
Mar 2000.
268
Bibliography
[63]
P. Garica-Gonzalez and A. Garcia-Orrada. "Control System for a PWMBajed STATCOM", IEEE Transaction an Power Delivery, Vol. 15, No. 4,
pp. 1252-1257, Oct 2000.
[64]
W.-N. Chang and K.-D. Yeh, "Design of D-STATCOM for Fast Load
Compensation of Unbalanced Dist^Dution Systems", in Conf. Rec. 4th IEEE
International Conference on Power xHpr+ronics and Drive Systems, pp. 801806,2001.
[65]
S .-Y. Park and J.-K. Park, "The Modeling ,; nd Analysis of Shunt Type Custom
Power Device", in Conf. Rec. iK&E 'Power Engineering Society Winter
Meeting, pp. 186-191, 2001.
[66]
T. J. E. Miller, "Reactive Power Control in Elechic Systems", Canada, John
Wiley & Sons, Inc., 1982.
[67]
K. N. Choma and M. Etezadi-Amoli, "The Application of a DSTATCOxM to
an Industrial Facility", in Conf. Rec. IEEE Power Engineering Society Winter
Meeting, pp. 725-728, 2002.
[68]
C. Schauder and H. Mehta, "Vector Analysis and Control of Advanced Static
VAR Compensators", IEE Proceedings-C Generation Transmission &
Distribution, Vol. 140, No. 4, pp. 299-306, Jul 1993.
[69]
K. R. Padiyar and A. M. Kulkami, "Design of Reactive Current and Voltage
Controller of Static Condenser", International Journal of Electrical Power &
Energy Systems, Vol. 19, No. 6, pp. 397-410, Aug 1997.
[70]
L. A. Moran, J. W. Dixon, and R. R. Wallace, "A Three-Pbase Active Power
Filter Operating with Fixed Switching Frequency for Reactive Power and
Current Harmonic Compensation", IEEE Transactions on Industrial
Electronics, Vol. 42, No. 4, pp. 402-408, Aug 1995.
[71]
H. Akagi, "Trends in Active Power Line Conditioners", IEEE Transactions on
Power Electronics, Vol. 9, No. 3, pp. 263-268, May 1994.
[72]
S. Fukuda and S.-I. Sugawa, "Adaptive Signal Processing Based Control of
Active Power Filters", in Conf. Rec. IEEE Industry Applications Conference,
pp. 886-890,1996.
[73]
F. Z. Peng, "Application Issues of Active Power Filters", IEEE Industry
Applications Magazine, pp. 21-30, Sep/Oct 1998.
[74]
F. Z. Peng, G.-J. Su, and G. Farquharson, "A Series LC Filter for Harmonic
Compensation of AC Drives", in Conf. Rec. IEEE Power Electronics
Specialists Conference, pp. 213-218, 1999.
[75]
F. Z. Peng and D. J. Adams, "Harmon;c Sources and Filtering Approaches Series/Parallel, Active/Passive, and Tb'.u Combined Power Filters-", in Conf
Rec. IEEE Industry Applications Society Annual Meeting, pp. 448-455, 1999.
•. i
269
|
Bibliography
[76]
S. T. Senini and. P. J. Wolfs, "Systematic Identification and Review of Hybrid
Active Filter Topologies", in Conf. Rec. IEEE Power Electronics Specialists
Conference, pp. 394-399, 2002.
[77]
H. Akagi, "Ne*v Trends in Active Filters for Power Conditioning", IEEE
Transactions in Industry Applications, Vol. 32, No. 6, pp. 1312-1322,
Nov/Dec 1996.
[78]
S. Fukuda and T. En(>'>i , "Control Method and Characteristics of Active
Power Filters", in Co;;;! Rec. Fifth European Conference on Power
Electronics and Applications, pp. 139-144,1993.
[79]
H. L. Jou, J. C. Wu, and K. D. Wu, "Parallel Operation of Passive Power Filter
and Hybrid Power Filter for Harmonic Suppression", IEE Proceedings.
Generation, Transmission & Distribution, Vol. 148, No. 1, pp. 8-14, Jan 2001.
[80]
Z. Ye, B. Dong, and Z. Qian, "A Novel Active Power Filter for High Voltage
Application", in Conf. Rec. IEEE Power Electronics Specialists Conference,
pp. 1429-1435,1998.
[81]
H. Fujita and H. Akagi, "A Practical Approach to Hamionic Compensation in
Power Systems - Series Connection of Passive and Active Filters", IEEE
Transactions on Industry Applications, Vol. 27, No. 6, pp. 1020-1025,
Nov/Dec 1991.
[82]
H. Fujita, T. Yamasaki, and H. Akagi, "A Hybrid Active Filter for Damping of
Harmonic Resonance in Industrial Power Systems", IEEE Transactions on
Power Electronics, Vol. 15, No. 2, pp. 215-222, Mar 2000.
[83]
D. Rivas, L. Moran, J. Dixon, and J. Espinoza, "A Simple Control Scheme for
Hybrid Active Power Filter", in Conf. Rec. IEEE Power Electronics
Specialists Conference, pp. 991-996, 2000.
[84]
D. Rivas, L. Moran, J. Dixon, and J. Espinoza, "Improving Passive Filter
Compensation Performance with Active Techniques", in Conf. Rec. IEEE
Ninth International Conference on Harmonics and Quality of Power, pp. 232238,2000.
[85]
S. Bhattacharya, P.-T. Cheng, and D. M. Divan, "Hybrid Solutions for
Improving Passive Filter Performance in High Power Applications", IEEE
Transactions on Industry Applications, Vol. 33, No. 3, pp. 112-1Al, May/Jun
1997.
[86]
F. B. Libano, D. S. L. Simonetti, and J. Uceda, "Frequency Characteristics of
Hybrid Filter Systems", in Conf. Rec. IEEE Power Electronics Specialists
Conference, pp. 1142-1148,1996.
[87]
F. B. Libano, J. A. Cobos, and J. Uceda, "Simplified Control Strategy for
Hybrid Active Filters", in Conf. Rec. IEEE Power Electronics Specialists
Conference, pp. 1102-1108,1997.
270
Bibliography
[88]
F. Z. Peng, H. Akagi, and A. Nabae, "Compensation Characteristics of the
Combined System of Shunt Passive and Series Active Filters", in Conf. Rec.
IEEE Industry Applications Society Annual Meeting, pp. 959-966, 1989.
[89]
S. Bhattacharya and D. Divan, "Synchronous Frame Based Controller
Implementation for a Hybrid Series Active Filter System", in Conf. Rec. IEEE
Industry Applications Conference, pp. 2531-2540, 1995.
[90]
F. Z. Peng, H. Akagi, and A. Nabae, "A New Approach to Harmonic
Compensation in Power Systems", in Conf. Rec. IEEE Industry Applications
Society Annual Meeting, pp. 874-880,1988.
[91]
F. Z. Peng, H. Akagi, and A. Nabae, "A Novel Harmonic Pov/er Filter", in
Conf. Rec. IEEE Power Electronics Specialists Conference, pp. 1151-1159,
1988.
[92]
S. Park, J.-H. Sung, and K. Nam, "A New Parallel Hybrid Filter Configuration
Minimizing Active Filter Size", in Conf. Rec. IEEE Power Electronics
Specialists Conference, pp. 400-405, 1999.
[93]
H. Fujita and H. Akagi, "The Unified Power Quality Conditioner: The
Integration of Series- and Shunt-Active Filters", IEEE Transactions on Power
Electronics, Vol. 13, No. 2, pp. 315-322, Mar 1998.
[94]
H. Akagi, Y. Kanazawa, and A. Nabae, "Instantaneous Reactive Power
Compensators Comprising Switching Devices Without Energy Sstorage
Components", IEEE Transactions on Industry Applications, Vol. IA-20, No.
3, pp. 625-630, May/Jun 1984.
[95]
K. Sozanski, R. Strzelecki, and A. Kempski, "Digital Control Circuit for
Active Power Filter with Modified Instantaneous Reactive Power Control
Algorithm", in Conf. Rec. IEEE Power Electronics Specialists Conference, pp.
1031-1036,2002.
[96]
S. Bhattacharya, T. M. Frank, D. M. Divan, and B. Banerjee, "Active Filter
System Implementation", IEEE Industry Applications Magazine, pp. 47-63,
Sep/Oct 1998.
[97]
J. S. Tepper, J. W. Dixon, G. Venegas, and L. Moran, "A Simple FrequencyIndependent Method for Calculating the Reactive and Harmonic Current in a
Nonlinear Load", IEEE Transactions on Industrial Electronics, Vol. 43, No. 6,
pp. 647-654, Dec 1996.
[98]
L. Zhou and Z. Li, "A Novel Active Power Filter Based on the Least
Compensation Current Control Method", IEEE Transactions on Power
Electronics, Vol. 15, No. 4, pp. 655-659, Jul 2000.
[99]
P. S. Sensarma, K. R. Padiyar, and V. Ramanarayanan, "A Comparative Study
of Harmonic Filtering Strategies for a Shunt Active Filter", in Conf. Rec. IEEE
Industry Applications Conference, pp. 2509-2516, 2000.
271
Bibliography
[100] P. Mattavelli, "A Closed-Loop Selective Harmonic Compensation for Active
Filters", IEEE Transactions on Industry Apvlications, Vol. 37, No. 1, pp. 8189,Jan/Feb2001.
[101] H. Akagi, "Control Strategy and Site Selection of a Shunt Active Filter for
Damping of Harmonic Propagation in Power Distribution Systems", IEEE
Transactions on Power Delivery, Vol. 12, No. 1, pp. 354-363, Jan 1996.
[102] H. Akagi, "A Shunt Active Filter Based on Voltage Detection for Harmonic
Termination of a Radial Power Distribution Line", in Conf. Rec. IEEE
Industry Applications Conference, pp. 1393-1399, 1998.
[103] K. Wada, H. Fujita, and H. Akagi, "Considerations of a Shunt Active Filter
Based on Voltage Detection for Installation on a Long Distribution Feeder",
IEEE Transactions on Industry Applications, Vol. 38, No. 4, pp. 1123-1130,
Jul/Aug 2002.
[104] K. Wada, H. Fujita, H. Akagi, and N. Shibamaru, "Experimental Verification
of the Effect of a Voltage-Detection-Based Shunt Active Filter for Harmonic
Damping Throughout a Power Distribution Line", Electrical Engineering in
Japan (English Translation ofDenki Gakkai Ronbunshi), Vol. 133, No. 2, pp.
1-10, Nov 2000.
[105] Jintakosonwit P; Akagi H; Fujita H; Ogasawara S, "Implementation and
Performance of Automatic Gain Adjustment in a Shunt-Active Filter for
Harmonic Damping Throughout a Power Distribution System", IEEE
Transactions on Power Electronics, Vol. 17, No. 3, pp. 438-447, May 2002.
j
I]
\\
Ij
\!
[106] P. Jintakosonwit, H. Fujita, H. Akagi, and S. Ogasawara, "Implementation and
Performance of Cooperative Control of Shunt Active Filters for Harmonic
Damping Throughout a Power Distribution System", in Conf. Rec. IEEE
Industry Applications Conference, pp. 51-58, 2002.
I
I
-;f
|
[107] P. Jintakosonwit, H. Fujita, and H. Akagi, "Control and Performance of ?
Fully-Digital-Controlled Shunt Active Filter for Installation on a Power
Distribution System", IEEE Transactions on Power Electronics, Vol. 17, No.
1, pp. 132-140, Jan 2002.
f
I
f
[108] Y. Sato, S. Nagayama, H. Chigira, and T. Kataoka, "An Adaptive Control
Strategy for Active Power Filters with Voltage Detection", in Conf. Rec. IEEE
Industry Applications Society Annual Meeting, pp. 1356-1363, 1998.
j|
%
|
Ij
[109] Y. Sato, T. Kawase, M. Akiyama, and T. Kataoka, "A Control Strategy
for
General-Purpose Active Filters Based on Voltage Detection", in Conf. Rec.
IEEE Industry Applications Society Annual Meeting, pp. 471-478, 1999.
[110] P. Brogan and R. Yacamini, "Stability of Selective Harmonic Active Filters",
in Conf. Rec. Power Electronics and Variable Speed Drives, pp. 416-421,
2000.
272
j
|
j
!
f
|
!
i
Bibliography
[ I l l ] P. Brogan and R. Yacamini, "Measurements and Simulation of an Active
Filter Based on Voltage Feedback", in Conf. Rec. IEEE 8th International
Conference on Harmonics and Quality ofPower, pp. 1113-1118,1998.
'
[112] D. Casadei, G. Grandi, U. Reggiani, and C. Rossi, "Control Methods
Active Power Filters with Minimum Measurement Requirements", in Conf
Rec. Fourteenth Annual Applied Power Electronics Conference and
Exposition, pp. 1153-1158, 1999.
[113] J. C. Wu and H. L. Jou, "Simplified Control Method for the Single-Phase
Active Power Filter", IEE Proc.-Electr. Power Appl, Vol. 143, No. 3, pp.
219-223, May 1996.
j
\
i
for
\
\
\
\
!
j
\
j
.
I
[114] F. Pottker and I. Barbi, "Power Factor Correction of Non-Linear Loads
Employing a Single-Phase Active Power Filter: Control Strategy, Design
Methology and Experimentation", in Conf. Rec. IEEE Power Electronics
Specialists Conference, pp. 412-417,1997.
\
5
[115] B. Singh, K. Al-Haddad, and A. Chandra, "A Universal Active Power Filter
for Single-Phase Reactive Power and Harmonic Compensation" in Conf Rec.
IEEE Power Quality, pp. 81-87, 1998.
|
|
j
[116] K. Chatterjee, B. G. Fernandes, and G. K. Dubey, "An Instantaneous Reactive
Volt-Ampere Compensator and Hamionic Suppressor System", IEEE
Transactions on Power Electronics, Vol. 14, No. 2, pp. 381 -392, Mar 1999.
|
|
f
[117] W. 1. Roux and J. D. v. Wyk, "Effectivity Reduction of PWM-Converter
Based Dynamic Filter by Signal Processing Delay" in Conf. Rec. IEEE Power
Electronics Specialists Conference, pp. 1222-1227, 1999.
I
[118] S. Valiviita and S. J. Ovaska, "Delayless Method to Generate Current
Reference for Active Filters", IEEE Transactions on Industrial Electronics,
Vol. 45, No. 4, pp. 559-567, Aug 1998.
$
f
|
[119] H.-L. Jou, "Performance Comparison of the Three-Phase Active-Power-Filter
Algorithms" IEE Proceedings. Generation, Transmission & Distribution,
Vol. 142, No. 6, pp. 646-652, Nov 1995.
J
U
J
[120] N. Bruyant and M. Machmoum, "Simplified Digital-Analogical Control for
Shunt Active Power Filters Under Unbalanced Conditions", in Conf. Rec.
Seventh International Conference on Power Electronics and Variable Speed
Drives, pp. 11-16,1998.
I
[121] D. Nedeljkovic, D. Voncina, V. Ambrozic, R. Cajhen, and J. Nastran, "Control
of Three-Phase Power Filter with Direct Calculation of Load Current's Active
Fundamental Harmonic", in Conf Rec. 8th Mediterranean Electrotechnical
Conference, pp. 357-360, 1996.
[122] W. M. Grady, M. J. Samotyj, and A. H. Noyola, "Survey of Active Power
Line Conditioning Methodologies", IEEE Transactions on Power Delivery,
Vol. 5, No. 3, pp. 1536-1542, Jul 1990.
273
;|
f
|
f
|
§
|
I
|
Bibliography
[123] S. Rechka, T. Ngandui, J. Xu, and P. Sicard, "A Comparative Study of
Harmonic Detection Algorithms for Active Filters and Hybrid Active Filters",
in Conf. Rec. IEEE Power Electronics Specialists Conference, pp. 357-363,
2002.
[124] F. Z. Peng, H. Akagi, and A. Nabae, "A Study of Active Power Filters using
Quad-Series Voltage-Source PWM Converters for Harmonic Compensation",
IEEE Transactions on Power Electronics, Vol. 5, No. 1, pp. 9-15, Jan 1990.
[125] H. Akagi, A. Nabae, and S. Atoh, "Control Strategy of Active Power Filters
using Multiple Voltage-Source PWM Converters", IEEE Transactions on
Industry Applications, Vol. IA-22, No. 3, pp. 460-465, May/Jun 1986.
[126] Y. Komatsu and T. Kawabata, "Characteristics of Active Power Filter
Controlled by the Use of Extension PQ Theory", in Conf. Rec. Third
International Power Electronics and Motion Control Conference, pp. 359364, 2000.
[127] Y. Komatsu and T. Kawabata, "A Control Method of Active Power Filter
Where System Voltage Contains Negative-Phase-Sequence Component or
Zero-Phase-Sequence Component", in Conf. Rec. International Conference on
Power Electronics and Drive Systems, pp. 583-586, 1995.
[128] S. Bhattacharya, D. M. Divan, and B. Banerjee, "Synchronous Frame
Harmonic Isolator using Active Series Filter", in Conf. Rec. 4th European
Conference on Power Electronics and Applications, pp. 30-35, 1991.
[129] G. D. Marques, "A Comparison of Active Power Filter Control Methods in
Unbalanced and Non-Sinusoidal Conditions", in Conf. Rec. 24th Annual
Conference of the IEEE Industrial Electronics Society, pp. 444-449,1998.
[130] P.-T. Cheng, S. Bhattacharya, and D. D. Divan, "Line Harmonics Reduction in
High-Power Systems using Square-Wave Inverters-based Dominant Harmonic
Active Filter", IEEE Transactions on Power Electronics, Vol. 14, No. 2, pp.
265-272, Mar 1999.
[131] D. N. Zmood, D. G. Holmes, and G. H. Bode, "Frequency-Domain Analysis
of Three-Phase Linear Current Regulators", IEEE Transactions on Industry
Applications, Vol. 37, No. 2, pp. 601-610, Mar/Apr 2001.
[132] D. N. Zmood and D. G. Holmes, "Stationary Frame Current Regulation of
PWM Inverters with Zero Steady State Error", in Conf. Rec. IEEE Power
Electronics Specialists Conference, pp. 1185-1190,1999.
[133] X. Yuan, W. Merk, H. Stemmler, and J. Allmeling, "Stationary-Frame
Generalized Integrators for Current Control of Active Power Filters with Zero
Steady-State Error for Current Harmonics of Concern Under Unbalanced and
Distorted Operating Conditions", IEEE Transactions on Industry Applications,
Vol. 38, No. 2, pp. 523-532, Mar/Apr 2002.
274
Bibliography
[134] M. J. Newman, D. N. Zmood, and D. G. Holmes, "Stationary Frame Harmonic
Reference Generation for Active Filter Systems", IEEE Transactions on
Industry Applications, Vol. 38, No. 6, pp. 1591-1599, Nov/Dec 2002.
[135] H.-L. Jou, H.-Y. Chu, and J.-C. Wu, "A Novel Active Power Filter for
Reactive Power Compensation and Harmonic Suppression", International
Journal of Electronics, Vol. 75, No. 3, pp. 577-587, Sep 1993.
[136] L. W. Dixon, C. J. Garcia, and L. T. Moran, "A Control System for a Three
Phase Active Power Filter which Simultaneously Compensates Power Factor
and Unbalanced Loads", in Conf. Rec. International Conference on Industrial
Electronics, Control, and Instrumentation, pp. 1083-1087,1993.
[137] H. L. Jou, J. C. Vu, and H. Y. Chu, "New Single-Phase Active Power Filter",
IEEProc-Elecir. Power Appl, Vol. 141, No. 3, pp. 129-134, May 1994.
[138] J. Doval, A. Nogueiras, C. M. Penalver, and A. Lago, "Shunt Active Power
Filter with Harmonic Current Control Strategy", in Conf. Rec. IEEE Power
Electronics Specialists Conference,^. 1631-1635, 1998.
[139] M. P. Kazmierkowski and M. A. Dzieniakowski, "Review of Current
Regulation Techniques for Three-Phase PWM Inverters", in Conf Rec. 20th
International Conference on Industrial Electronics, Control and
Instrumentation, pp. 567-575, 1994.
[140] D. G. Holmes and D. A. Martin, "Implementation of a Direct Digital
Predictive Current Controller for Single and Three Phase Voltage Source
Inverters", in Conf Rec. IEEE Industry Applications Conference, pp. 906-913,
1996.
[141] D. M. Brod and D. W. Novotny, "Current Control of VSI-PWM Inverters",
IEEE Transactions on Industry Applications, Vol. IA-21, No. 3, pp. 562-570,
May/Jun 1985.
[142] J. Dixon, S. Tepper, and L. Moran, "Practical Evaluation of Different
Modulation Techniques for Current-Controlled Voltage Source Inverters", IEE
Proc-Electr. Power Appl, Vol. 143, No. 4, pp. 301-306, Jul 1996.
[143] S. Buso, L. Malesani, and P. Mattavelli, "Comparison of Current Control
Techniques for Active Filter Applications", IEEE Transactions on Industrial
Electronics, Vol. 45, No. 5, pp. 722-729, Oct 1998.
[144] Q. Yao and D. G. Holmes, "A Simple, Novel Method for Variable-HysteresisBand Current Control of a Three Phase Inverter with Constant Switching
Frequency", in Conf. Rec. IEEE Industry Applications Conference, pp. 11221129, 1993.
[145] J.-O. Krah and J. Holtz, "Total Compensation of Line-Side Switching
Harmonics in Converter-Fed AC Locomotives", IEEE Transactions on
Industry Applications, Vol. 31, No. 6, pp. 1264-1273, Nov/Dec 1995.
275
Bibliography
[146] M. Meyer., "Active Power Filters for Inverter Locomotives-A Concept for
Improved Efficiency and Low Distortion Currents", in Conf. Rec. IEEE Power
Electronics Specialists Conference, pp. 389-396,1992.
[147] T. Maeda, T. Watanabe, A. Mechi, T. Shiota, and K. Iida, "A Hybrid SinglePhase Power Active Filter for High Order Harmonics Compensation in
Converter-Fed High Speed Trains", in Conf. Rec. Proceedings of the Power
Conversion Conference, pp. 711-717,1997.
|
|
[148] S. Tnani, M. Mazaudier, A. Berthon, and S. Diop, "Comparison Between
Differential Real-Time Harmonic Analysis Methods for Control of Electrical
Machines", ui Conf. Rec. Power Electronics and Variable Speed Drives, pp.
342-345, 1994.
[149] D. K. Cheng, "Field and Wave Electromagnetics", 2nd ed, Addison-Wesley
Publishing Company, 1989.
I
$
[150] O. Hamoud, "Harmonic Problems in Queensland Railways Electric Traction
System" in Conf. Rec. International Conference on Main Line Railway
Electrification, pp. 227-231,1989.
|
'
j
[151] O. R. Kumar, K. Karunakara, E. M. Kumar, P. V. V. Nambudiri, and K. N.
Srinivasan. "Harmonic Levels in a Traction System - An Overview", in Conf.
Rec. IEEE Power Quality '98, pp. 139-143,1998.
4
j
|
i
f
|
f
I
[152] D. G. Holmes and B. P. McGrath, "Opportunities for Flarmonic Cancellation
with Carrier-Based PWM for a Two-Levd and Multilevel Cascaded
Inverters", IEEE Transactions on Industry Applications, Vol. 37, No. 2, pp.
574-582, Mar/Apr 2001.
i
[153] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, "A New
Multilevel PWM Method: A Theoretical Analysis", IEEE Transactions on
Power Electronics, Vol. 7, No. 3, pp. 497-505, Jul 1992.
[154] T. A. Meynard and H. Foch, "Mu)fi-l,c^el Conversion: High Voltage
Choppers and Voltage-Source Inver.crs'" in Conf. Rec. IEEE Power
Electronics Specialists Conference, pp. 397-403, 1992.
[155] P. C. Loh, D. G. Holmes, Y. Fukuta, and T. A. Lipo, "Reduced Common
Mode Carrier-Based Modulation Strategies for Cascaded Multilevel
Inverters" in Conf. Rec. IEEE Industry Applications Conference, pp. 20022009, 2002.
[156] B.-R. Lin and D.-J. Chen, "Single-Phase Neutral Point Clamped AC/DC
Converter with the Function of Power Factor Corrector and Active Filter", IEE
Proceedings. Electric Power Applications, Vol. 149, No. 1, pp. 19-30, Jan
| j
I
li
V
f;
I
§
I!
2002.
•
[157] M. Sedighy, S. B. Dewan, and F. P. Dawson, "A Robust Digital Current
Control Method for Active Power Filters" IEEE Transactions on Industry
Applications, Vol. 36, No. 4, pp. 1158-1164, Jul/Aug 2000.
|
|
I
f
Bibliography
[158] C. A. Claro, J. Kaffka, and A. Campos, "A Fully Digital Control Employing a
Dead Beat Technique for Active Power Filters", in Conf Rec. IEEE Power
Electronics Specialists Conference, pp. 143-148, 1999.
[159] S. Bhattacharya, A. Veltman, D. M. Divan, and R. D. Lorenz, "Flux-Based
Active Filter Controller", IEEE Transactions on Industry Applications, Vol.
32, No. 3, pp. 491-502, May/Jun 1996.
[160] M. Marchesoni, "High-Performance Current Control Techniques for
Application io Multilevel High-Power Voltage Source Inverters", IEEE
Transactions on Power Electronics, Vol. 7, No. 1, pp. 189-204, Jan 1992.
[161] F. Zare and G. Ledwich, "A Hysteresis Current Control for Single-Phase
Multilevel Voltage Source Inverters: PLD Implementation", IEEE
Transactions on Power Electronics, Vol. 17, No. 5, pp. 731-738, Sept 2002.
i
iI
[162] G. H. Bode and D. G. Holmes, "Implementation of Three Level Hysteresis
Current Control for a Single Phase Voltage Source Inverter", in Conf. Rec.
IEEE Power Electronics Specialists Conference, pp. 33-38,2000.
[163] P. C. Loh, G. H. Bode, D. G. Holmes, and T. A. Lipo, "A Time-Based Double
Band Hysteresis Current Regulation Strategy for Single-Phase Multilevel
Inverters", in Conf. Rec. IEEE Industry Applications Conference, pp. 19942001,2002.
I
i
[164] M. D. Manjrekar, P. K. Steimer. and T. A. Lipo, "Hybrid Multilevel Power
Conversion System: A Competitive Solution for High-Power Applications",
IEEE Transactions on Industry Applications, Vol. 36, No. 3, pp. 834-841,
May/Jun 2000.
[165] A. M. Gole and et al., "Guidelines for Modeling Power Electronics in Electric
Power Engineering Applications", IEEE Transactions on Power Delivery,
Vol. 12, No. 1, pp. 505-514, Jan 1996.
[166] P. Firpo, M. Fracchia, and S. Savio, "Locomotive Drive Harmonic Pollution in
AC Traction Systems", in Conf Rec. IEEE International Symposium on
Industrial Electronics, pp. 622-628, 1993.
[167] J. R. Marti, L. Marti, and H. W. Dommel, "Transmission Line Models for
Steady-State and Transients Analysis", in Conf Rec. IEEE/NTUA Athens
Power Tech Conference, pp. 744-750, 1993.
\
[168] R. Yacamini, O. A. R. Hamoud, and O. Afacan, "Modelling of Traction Load
Distortion in Electricity Supply Systems", IEE Proceedings-B, Vol. 128, No.
3, pp. 149-156, May 1981.
f. !
[169] "CS-IIB Integrated Inverter, Technical Manual", 1.0 ed, Creative Power
Technologies, 2001.
[170] "CS-AI016/4 Mini Micro Analog I/O Card, Technical Manual", 1.00 ed,
ByteWyde Systems, 1995.
277
I
Bibliography
[171] "TMS320-F240 CS-MiniDSP Controller Card, Technical Manual", 1.1 ed,
Power Electronics Group, Monash University, 2000.
'i
A
[172] "TMS320C24x DSP Controllers - Peripheral Library and Specific Devices",
Texas Instruments, 1997.
[173] G. F. Franklin, J. D. Powell, and M. Workman, "Digital Control of Dynamic
Systems", Third ed, Addison Wesley Longman, Inc., 1998.
[174] E. C. Ifeachor and B. W. Jervis, "Digital Signal Processing, A Practical
Approach", Addison-Wesley Publishing Company Inc., 1993.
[175] R. H. Middleton and G. C. Goodwin, "Improved Finite Word Length
Characteristics in Digital Control Using Delta Operators", IEEE Transactions
on Automatic Control, Vol. AC-31, No. 11, pp. 1015-1021, Nov 1986.
?
J
ti
[176] J. Kauraniemi, T. I. Laakso, I. Hartimo, and S. J. Ovaska, "Delta Operator
Realizations of Direct-Form IIR Filters", IEEE Transactions on Circuits &
Systems II-Analog & Digital Signal Processing, Vol. 45, No. 1, pp. 41-52, Jan
1993.
[177] M. J. Newman and D. G. Holmes, "Delta Operator Digital Filters for High
Performance Inverter Applications", IEEE Transactions on Power Electronics,
Vol. 18, No. 1, pp. 447-454, Jan 2003.
[178] R. C. Dorf and R. H. Bishop, "Modern Control Systems", Ninth ed, PrenticeHall, Inc., 2001.
[179] R. K. Y. Poon, K. K. Li, and M. Coupe, "Power Factor Correction in a 25kV
Electrified Railway", in Conf. Rec. International Conference on Main Line
Railway Electrification, pp. 149-153, 1989.
I
x{
i
278