Download this PDF file

S. P. Singh, M. Mishra and G. Srivastava / IJECCT 2013, Vol. 3 (3)
20
Leakage Reduction in Nanometer SRAM cell using
Power Gating VDD control technique
Suryabhan Pratap Singh¹, Manish Mishra¹, Geetika Srivastava²
1
2
Department of Electronics, DDUGU, Gorakhpur (273009), U.P, INDIA
Amity school of Engineering& Technology, Amity University Lucknow (226010), U.P, INDIA
[email protected]¹,[email protected]²
Abstract: Increased demand of storage capacity in
commercially available products has led to increased
attention of researchers in the field of memory design. As
today, memory block dominates more than 90% of entire
chip area; improvement in their performance will lead to
overall system performance improvement. This paper
focuses on optimization of power dissipation with
decreasing data retention voltage and size of virtual
supply node transistors. An 8T-SRAM cell simulation
results shows leakage power improvements compared
with previous 6T SRAM cell. The analysis proves
suitability of 8T-SRAM cell in low-power applications.
This paper presents access and virtual supply transistor
sizing analysis with respect to overall cell leakage power
performance. The data retention gates reduces the leakage
current of the SRAM cell in hold mode of operation and
propose the leakage improvement as high as 22 % at
90nm at 0.7V with (W/L)cell/(W/L)access=1,5% AT
65nm at 0.4V,17% at 45nm and 6.5% at 32nm at 0.2 V
compared with respective 6T SRAM cell and the leakage
power can be reduce 20.8% at 90nm with sizing of sleep
transistor is 2 at voltage 0.9V, 6.15% at 65nm with sizing
of sleep transistor is 2 at voltage 0.6V, 20.16% at 45nm
with sizing of sleep transistor is 2 at voltage 0.3V and
8.45% at 32nm with sizing of sleep transistor is 2 at
voltage 0.2V with respective G-gated SRAM cell .
Keywords – SRAM, Low power Design P-gated G-gated,
Leakage reduction
I.
INTRODUCTION
CMOS digital integrated circuits are the enabling
technology for modern information age [1]. The size of
MOS devices is approaching physical limit and their submicrons leakage currents are increasing dramatically. Most
of the time of its operation the memory cell remains in
standby mode and hence standby leakage currents of
SRAM cells typically contributes a major portion of chip
leakage. Since several millions of memory cells are
integrated in one SRAM chip, standby leakage currents of
each cell is accumulated to consume larger amount of total
chip power. As SRAM is most popular devices for digital
storage so, reduction of the leakage power and
improvement performance capabilities of SRAM is the
main focus of chip designer today.
SRAM is a type of semiconductor memory that uses bi-
stable latching circuitry to store a bit as voltage. Each
memory cell required six transistors. In this paper, 8T
SRAM p-gated and g-gated cell with VDD control power
reduction technique is analyzed and compared with 6TSRAM cell in nanometer technology. The performance of
cell is evaluated in different technologies with varying
virtual nodes voltages and size of sleep transistors. The
power consumption by cell is reduced by cutting off
supply terminals in standby mode of cell operation.
A.
6T-SRAM Cell Circuit Design
Figure 1: 6T SRAM cell [2]
Figure 1 shows basic SRAM cell configuration with 6
transistors, which stores bit in two cross-coupled inverters
made of four transistors (Q1, Q2, Q3 and Q4). This storage
cell has two stable states which represent stored 0 and
stored 1. Two additional access transistors serve to control
the access to a storage cell during read and write
operations. Access to the cell is enabled by the word line
(WL) which controls the two access transistors Q5 and Q6
connected to the bit lines BL and BL BAR. They are used
to transfer data for both read and write operation.
B. Sizing of Conventional 6t Sram Cell
The SRAM cell should be sized as small as possible to
achieve high density in memory design. However, issues
related to robustness impose a sizing constraint to the
6TSRAM cell. Fig. 1 shows the conventional 6TSRAM
cell configuration. The transistor ratio between Q1 and Q5
must be greater than 1.2 to keep a proper SNM during the
read operation.[3,4,5]
C. Leakage Current Component
Leakage current is the main source of standby power
dissipation in SRAM cell. In nano-scale MOS devices, the
major components of leakage current are the sub-threshold
leakage, the gate-tunneling leakage, and junction leakage
S. P. Singh, M. Mishra and G. Srivastava / IJECCT 2013, Vol. 3 (3)
21
(Figure 2). The sub-threshold leakage, which is defined as
a weak inversion conduction current with Vgs < Vth, is
significant component of off-state transistor leakage [6, 7].
Figure 3: 8T g-gated SRAM data retention circuit
Figure2: leakages component in the transistor.
The sub threshold current (I sub) is given by
I sub=Asub w exp (
)
(1-exp ( Vds))
Figure 4: 8Tp-gated SRAM cell data retention circuit
The Gate-tunneling current (I gate) is dominated by gate to
channel current of ON NMOS transistors.
I gate=A ox W N (
)²
(iii) Junction leakage (Ijn) is small contributed to total
leakage current.
D. SRAM Operation
An SRAM cell has three different states: standby or hold
mode, reading and writing. For proper operation of SRAM
read mode and write mode, it should have good "read
stability" and "write ability" respectively. The cell
operation in three different states can be defined as-(i)
Standby mode: The word line is not asserted, access
transistors Q 5 and Q 6 disconnect cell from the bit lines
and data inside cell remains Unaffected. (ii) Read mode:
The stored bit in the cell is transferred from Q and Q bar to
bit lines with a positive going pulse applied on word line.
(iii)Write mode: For writing a 0, it is applied on BL and 1
is applied on BL bar, WL is asserted and the value stored
in cell is latched to bit lines. Input drivers are designed
much stronger than the weak transistors in the cell for
proper operation of SRAM
II. 8T SRAM CELL
8T SRAM cell is designed for reducing power dissipation
by addition of two NMOS transistor in pull down of 6T
SRAM cell in G-gated mode and similarly two PMOS
transistor in pull up for P-gated mode (Figure 3 and figure
4). An 8T SRAM cell structure is analyzed for improved
power dissipation in standby.
In G-gated SRAM cell (Figure 3), the extra pair of NMOS
replaces mode from ground node with evaluated potential
by virtual ground node [8,9,10]. Q7 has main function of
cutting off the cell from ground in standby mode which
reduces leakage current in this mode, and Q8 is used to
provide a fix voltage Vy at this node. In P-gated SRAM
cell (Figure 4), the extra pair of PMOS replaces VDD node
by virtual VDD node.Q7 has main function of cutting of
the cell in standby mode from VDD which reduces leakage
current in this mode , Q8 is used to provide a fix voltage
VX at this node. Drawback: virtual ground (supply) node
may charge (discharge) to VDD (0) is stored bit may be
destroyed. Solution: In the standby mode, strap the virtual
ground or virtual supply to a fixed voltage node is Data
retention capability.
III. SIMULATION AND ANALYSIS
Circuits have been simulated using BSIM 4 at 90nm,
65nm, 45nm and 32nm technology. To make the impartial
testing environment all circuits has been simulated on the
same input patterns. In this paper, two different low power
techniques is presented and compared in detail for
nanometer technologies on SRAM cell. The relative power
dissipation at varying node voltage and sizing of different
transistors has been evaluated and compared with
conventional one.
IV. RESULT
Figure 5 and 6 shows that power dissipation of 6T-SRAM
cell decreases with increase of size of access transistor (Q5
and Q6) i.e. (W/L) access↑ Power dissipation↓ for all
technology (figure 1). Figure 7 show that power
dissipation of G-gated SRAM cell decreases with increase
data retention voltage (Vy) then after it (power dissipation)
increases at 90nm technology. figure 8,9 and figure 10
S. P. Singh, M. Mishra and G. Srivastava / IJECCT 2013, Vol. 3 (3)
22
shows that power dissipation of G-gated SRAM cell
increases with increase data retention voltage (Vy) with
respect to different size of sleep transistor (Q7 and Q8) at
65nm,45nm and 32nm technology (figure 3). figure11, 12,
13 and figure14 shows that power dissipation of P-gated
SRAM cell decreases with increase data retention voltage
(Vx) then after it (power dissipation) increase with respect
to different size of sleep transistor (Q7 and Q8) for all
technology. And figure15, 16, 17 and figure18 show that
percentage power dissipation of P gated and G gated
SRAM cell increases with increase data retention voltage
(V) at different size of sleep transistor for all technology.
Figure8: Power dissipation vs. voltage (Vy) with different sizing
of transistor at 65nm technology in G-gated SRAM cell.
Figure5: Power dissipation Vs. W/L of access transistor at 90nm
technology in 6T SRAM cell.
Figure 9: Power dissipation vs. voltage (Vy) with different sizing
of transistor at 45nm technology in G-gated SRAM cell.
Figure 6:Power dissipation Vs. W/L of access transistor at 65nm,
45nm, and 32nm technology 6T SRAM cell.
Figure10: Power dissipation vs. voltage (Vy) with different sizing
of transistor at 32nm technology in G-gated SRAM cell.
Figure7: Power dissipation vs. voltage (Vy) with different sizing
of transistor at 90nm technology in G-gated SRAM cell.
Figure11: Power dissipation vs. voltage (Vx) with different sizing
of transistor at 90nm technology in P-gated SRAM cell.
S. P. Singh, M. Mishra and G. Srivastava / IJECCT 2013, Vol. 3 (3)
Figure12: Power dissipation vs. voltage (Vx) with different sizing
of transistor at 65nm technology in P-gated SRAM cell.
Figure13: Power dissipation vs. voltage (Vx) with different sizing
of transistor at 45nm technology in P-gated SRAM cell.
Figure14: Power dissipation vs. voltage (Vx) with different sizing
of transistor at 32nm technology in P-gated SRAM cell.
23
Figure 16: Power dissipation in % vs. voltage of P and G-gated
SRAM cell at 65nm technology.
Figure 17: Power dissipation in % vs. voltage of P and G-gated
SRAM cell at 45nm technology.
Figure: 18: Power dissipation in % vs. voltage of P and G-gated
SRAM cell at 32nm technology.
V. CONCLUSION
Figure15: Power dissipation in % vs. voltage of P and G-gated
SRAM cell at 90nm technology.
The most efficient technique to reduce the power
dissipation is the reduction of supply voltage (data
retention voltage Vx and Vy), the power dissipation
reduction in SRAM cell is not only due to power supply
voltage reduction, but also to the operating sizing of sleep
transistor In this paper, proposed circuit is presented for
reducing power consumption through scaling the supply
voltage as compared to conventional circuit at different
technologies. We have shown that the leakage power can
be reduce 20.8% at 90nm with sizing of sleep transistor is
2 at voltage 0.9V, 6.15% at 65nm with sizing of sleep
transistor is 2 at voltage 0.6V, 20.16% at 45nm with sizing
of sleep transistor is 2 at voltage 0.3V and 8.45% at 32nm
with sizing of sleep transistor is 2 at voltage 0.2V in 8T Pgated SRAM cell than 8T G-gated SRAM cell. 8T P-
S. P. Singh, M. Mishra and G. Srivastava / IJECCT 2013, Vol. 3 (3)
GATED SRAM is better than conventional 6T SRAM cell
and 8T G-gated SRAM cell at different technology.
REFFERENCES
[1]
[2]
[3]
[4]
Sung-Mo Kang,Yusuf Leblebici, “CMOS digital integrated circuits
analysis and design”, ISBN -13:978-0-07-053077-5/0-07-0530777, third edition, Tata McGraw Hill education,2003,30th reprint
2012,pp preface pp (xi).
Adel S. Sendra and Kenneth C. Smith “microelectronic circuits”,
ISBN 0 19 511690 9, fourth edition, oxford, pp 1117-1118.
Kevin Zhang, Uddalak Bhattacharya, Zhan ping Chen, Fatih
Hamzaoglu,Daniel Murray, Narendra Vallepalli, Yih Wang, B.
Zheng, and Mark Bohr,‫״‬SRAM Design on 65-nm CMOS
Technology With Dynamic Sleep Transistor for Leakage
Reduction” IEEE JOURNAL OF SOLID-STATE CIRCUITS,
VOL. 40, NO. 4, APRIL 2005, pp. 895-896
Bhavya Daya, Shu Jiang, Piotr Nowak, Jaffer Sharief
„„Synchronous 16x8 SRAM Design” pp.1-2
24
A.Chandrakasan, W.J. Bowhill, F. Fox, “Design of HighPerformance Microprocessor Circuits”, IEEE Press, 2000.
[6] Behnam Amelifard, Farzan Fallah, and Massoud Pedram
“Low‐ Leakage SRAM Design in Deep Submicron Technologies”
Jan 25, 2008 Presentation at SNU, pp.29
[7] Sung-Mo Kang,Yusuf Leblebici,
“CMOS digital integrated
circuits analysis and design, ISBN -13:978-0-07-053077-5/0-07053077-7, third edition, Tata McGraw Hill education,2003,30th
reprint 2012,pp 449.
[8] Geetika Srivastava &R.K.Chauhan “Deasign of a new 10T SRAM
cell for leakage reduction & stability enhancement”
IEEE,VOLUME 3,Number 39 (2010) pp.225-230.
[9] Geetika Srivastava &R.K.Chauhan “Effect of technology scale
down on power reduction stretegies” ISBN-978-1-4577-0694-3
PN-717, IEEE Explorer conference proceding May 2012.
[10] Geetika Srivastava &R.K.Chauhan “Effect of process parameter on
6T SRAM cell design for low power reduction ”International
Journal of Microcircuits & Electronics, ISBN 09742204,VOLUME 1, Number1 (2010) pp.35-42.
[5]