Download CMOS Transistors, Gates, and Wires

CMOS Transistors,
Gates, and Wires
Should the hardware abstraction layers
make today’s lecture irrelevant?
Application
Algorithm
RP
Guarded Atomic Actions
RW
Cd
CW/2
CW/2
Cg
Previous Two Lectures
Register-Transfer Level
Gates
Today’s Lecture
Circuits
6.375 Complex Digital Systems
Christopher Batten
February 15, 2006
Devices
Physics
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 2
Should the hardware abstraction layers
make today’s lecture irrelevant?
Application
Algorithm
Guarded Atomic Actions
Register-Transfer Level
Gates
Circuits
Devices
Physical design issues
are increasingly pushing
their way up the
abstraction layers
It is essential for modern
digital designers to have
some intuition about the
lower level physical
design issues
CMOS Transistors, Gates, and Wires
Gates
Transistors
Wires
output
input0
input1
Physics
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 3
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 4
Metal Oxide-Semiconductor
Field-Effect (MOSFET) Transistor
Overview of operation of a
NMOS transistor
Gate
Source
diffusion
ID
Vin
Ev
bulk
Vout
ID
INVERSION:
A sufficiently strong vertical
field will attract enough
electrons to the surface to
create a conducting n-type
channel between the source
and drain.
VDS
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 5
Key qualitative characteristics of
MOSFET transistors
Width
VDS
VGS
Drain
diffusion
S
lg(ID)
Vt
VGS
V
Vt
VGS
time
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 6
CMOS Transistors, Gates, and Wires
Gates
Vout
Vin
G
bulk
ID
CONDUCTION:
If a channel exists, a
horizontal field will cause a
drift current from the drain
to the source.
VDS
D
Source
diffusion
Drain
diffusion
Eh
Gate
VGS
Inversion
happens here
Transistors
Cg
Reff
Cd
Wires
Length
output
•
•
•
•
•
•
Threshold voltage sets when transistor turns on – also impacts leakage
IDS is proportional to mobility x (W/L)
NMOS mobility > PMOS mobility => ReffN < ReffP (assume mobility ratio is 2)
Increase W = Increase I = Decrease Reff
Increase L = Decrease I = Increase Reff
input0
input1
Cg proportional to ( W x L ) and Cd proportional to W
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 7
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 8
The most basic CMOS gate
is an inverter
The most basic CMOS gate
is an inverter
VDD
Let’s make the following assumptions
WP/LP
Vin
1. All transistors are minimum length
2α
Vout
WN/LN
WP/LP
2. All gates should have equal rise/fall
times. Since PMOS are twice as slow
as NMOS they must be twice as wide
to have the same effective resistance
1α
Vin
2α
PMOS
Vout
WN/LN
3. Normalize all transistor widths to
minimum width NMOS
1α
A
Y
NMOS
GND
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 9
A simple RC model for the
inverter can provide significant insight
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 10
A simple RC model for the
inverter can provide significant insight
Reff
Vin
Vout
Reff
Vin
Vout
Cg
Reff
Cd
Vout
Vin
Cg
Reff
Cd
CL
Reff = Reff,N = Reff,P
Cg = Cg,N + Cg,P
Cd = Cd,N + Cd,P
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 11
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 12
A simple RC model for the
inverter can provide significant insight
The most basic CMOS gate
is an inverter
Reff
Reff
Vout
Vin = “0”
Cg
Reff
Cd
Vout
Vin = “1”
CL
Charge RC Time Constant = Reff x ( Cd + CL )
Cg
Cd
Reff
CL
Discharge RC Time Constant = Reff x ( Cd + CL )
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 13
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 14
Larger gates are faster since they
decrease Reff (but they also increase Cd!)
Simple RC model can also yield intuition
on energy consumption of inverter
Process gen
= 0.25µm
Supply voltage = 5V
Min width NMOS = 0.5µm
Param
Value
Units
Cd,N/µm
1.42
fF/µm
Cd,P/µm
2.40
fF/µm
Cg,N/µm
1.55
fF/µm
Cg,P/µm
1.48
fF/µm
Reff,N x µm
4.93
kΩ/µm
Reff,P x µm 10.83
kΩ/µm
2
1
2
1
Cd = (0.5x1.42) + (1x2.40) = 3.11 fF
CL = (0.5x1.55) + (1x1.48) = 2.26 fF
Cd+CL = 5.37 fF
TPLH = 2.2 x (10.83/1) x 5.37 = 128ps
TPHL = 2.2 x (4.93/0.5) x 5.37 = 116ps
Vin
= “0”
Vout
2
2
1
Cd = (1x1.42) + (2x2.40) = 3.66 fF
CL = (0.5x1.55) + (1x1.48) = 2.26 fF
Cd+CL = 5.92 fF
TPLH = 2.2 x (10.83/2) x 5.92 = 70.5ps
TPHL = 2.2 x (4.93/1) x 5.92 = 64.2ps
→ 1
T
T
0
0
Reff
Cd
T
CL
T
dQ
dt
dt
0
= ∫ P(t) dt = VDD∫ I(t) dt = VDD∫
= VDD∫ C
Cg
4
E0
Reff
0
VDD
dV
dt = VDD ∫ (Cd + CL)dVout
dt
0
= (Cd + CL)VDD2 = CVDD2
• During 0l1 transition, energy CVDD2 removed from power supply
• After transition, 1/2 CVDD2 stored in capacitor, the other 1/2 CVDD2
was dissipated as heat in pullup resistance
• The 1/2 CVDD2 energy stored in capacitor is dissipated in the
Ignores the fact that previous
gate now must drive a bigger
gate capacitance!
pulldown resistance on next 1l0 transition
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 15
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 16
Larger gates use slightly more energy,
real concern is affect on previous gate
Process gen
= 0.25µm
Supply voltage = 5V
Min width NMOS = 0.5µm
Param
Value
Units
Cd,N/µm
1.42
fF/µm
Cd,P/µm
2.40
fF/µm
Cg,N/µm
1.55
fF/µm
Cg,P/µm
1.48
fF/µm
Reff,N x µm
4.93
kΩ/µm
Reff,P x µm 10.83
kΩ/µm
2
2
1
1
Cd
CL
Cd+CL
E0>1
Many other types of power consumption
in addition to dynamic power
= (0.5x1.42) + (1x2.40) = 3.11 fF
= (0.5x1.55) + (1x1.48) = 2.26 fF
= 5.37 fF
= 5.37 x 52 = 134fJ
Reff
Cg
4
2
2
1
Ignores the fact that previous
gate now must drive a bigger
gate capacitance!
Cd
CL
Cd+CL
E0>1
= (1x1.42) + (2x2.40) = 3.66 fF
= (0.5x1.55) + (1x1.48) = 2.26 fF
= 5.92 fF
= 5.92 x 52 = 148fJ
Short Circuit Current
Reff
Cd
Reff
Reff
Cd
Fast edges keep to <10% of cap charging current
Subthreshold Leakage Approaching 10-40% of active power
Diode Leakage
Usually negligible
Gate Leakage
Was negligible, increasing due to thin gate oxides
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 17
More complicated gates use more
transistors in pullup/pulldown networks
Cg
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 18
Series and parallel MOSFET networks
provide natural duals of each other
VDD
Pullup network, connects output
to VDD, contains only PMOS
Input 0
Input 1
Input N
A
A
A
B
B
VOUT
Pulldown network, connects output
to GND, contains only NMOS
For every set of input logic values, either pullup or pulldown
network makes connection to VDD or GND
– If both connected, power rails would be shorted together
– If neither connected, output would float (tristate logic)
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 19
Conducts if A=0
A
Conducts if A=0 OR B=0
A
Conducts if A=0 AND B=0
A
B
B
Conducts if A=1
Conducts if A=1 AND B=1
Conducts if A=1 OR B=1
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 20
NAND and NOR gates illustrate the dual
nature of the pullup/pulldown networks
NAND Gate
Designers can use a methodical
approach to build more complex gates
• Goal is to create an logic function f ( x 1, x 2 , K)
NOR Gate
– We can only implement inverting logic with one CMOS stage
A
B
A
B
(A.B)
• Implement pulldown network
(A+B)
– Write PD = f ( x 1, x 2 , K)
– Use parallel NMOS for OR of inputs
– Use series NMOS for AND of inputs
A
(A.B)
B
• Implement pullup network
B
(A+B)
A
– Write pullup network PU = f ( x 1, x 2 , K) = g( x 1, x 2 , K)
– Use parallel PMOS for OR of complemented inputs)
– Use series PMOS for AND of complemented inputs)
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 21
Designers can use a methodical
approach to build more complex gates
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 22
CMOS Transistors, Gates, and Wires
Gates
A
f = ( A + B) ⋅ C
B
Transistors
Wires
PD = ( A + B) ⋅ C
(A+B).C
C
PU = ( A + B) ⋅ C
= ( A + B) + C
= ( A ⋅ B) + C
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 23
output
input0
input1
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 24
Wires are an old problem
Modern interconnect stacks
have six to nine or more metal layers
Metal 6
Cray-1
1976
© IBM
Via 5-6
Metal 5
Metal 4
Metal 3
Metal 2
Cray-3
wiring
Via 1-2
Metal 1
Cray-3
1993
Cray-1 Wiring
IBM CMOS7 process
© IBM
6 layers of copper wiring
1 layer of tungsten local interconnect
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 25
Wire resistance is a function
of height, width, and length
resistance =
Height
Length
Width
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 26
Wire capacitance is relative to the
substrate and to neighboring wires
( length × resistivity )
( height × width )
bulk aluminum
2.8x10-8 Ω-m
bulk copper
1.7x10-8 Ω-m
bulk silver
1.6x10-8 Ω-m
• Height (Thickness) fixed in given manufacturing process
• Resistances quoted as Ω/square
• TSMC 0.18mm 6 Aluminum metal layers
– M1-5 0.08 Ω/square (0.5 mm x 1mm wire = 160 Ω)
– M6 0.03 Ω/square (0.5 mm x 1mm wire = 60 Ω)
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 27
H2
W2
D12
H1
ε
W1 S1
DD1
• Capacitance depends on geometry of surrounding wires and
relative permittivity (εr) of insulating dielectric
– silicon dioxide (SiO2)
– silicon flouride (SiF4)
– SiLKTM polymer
εr = 3.9
εr = 3.1
εr = 2.6
Capacitive coupling to
neighbors is becoming a
serious problem!
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 28
Wire capacitance is relative to the
substrate and to neighboring wires
ε
2
ε
12
ε
ε
This IBM experimental 130nm process
includes two metals and two dielectrics
H2
W2
D12
Al
H1
1
W1 S1
D1
DD1
• Capacitance depends on geometry of surrounding wires and
relative permittivity (εr) of insulating dielectric
– silicon dioxide (SiO2)
– silicon flouride (SiF4)
– SiLKTM polymer
εr = 3.9
εr = 3.1
εr = 2.6
• Can have different materials between wires and between layers,
E. Barth, IBM Microelectronics
and also different materials on higher layers
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 29
Distributed RC wire model gives accurate
results but is computationally expensive
Rdriver
R1
R2
RN
Cload
C1
C2
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 30
Lumped Π model can provide a
quick reasonable approximation
Rdriver
Rw
Cload
CN
Cw/2
Cw/2
Use Penfield-Rubenstein equation to find delay
N
⎛ j=i ⎞
Delay ∝ ∑ ⎜ ∑ R j ⎟ Ci
⎠
i ⎝ j =1
How does the delay scale with longer wires?
– Wire delay increases quadratically
– Edge rate also degrades quadratically
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 31
Delay ∝ R driver ×
Cw
⎛C
⎞
+ (R driver + R w ) × ⎜ w + C load ⎟
2
⎠
⎝ 2
Rw is lumped resistance of the wire
Cw is lumped capacitance
Partition half of Cw at each end
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 32
Estimate the rise time of node A
using an RC delay model
Estimate the rise time of node A
using an RC delay model
Process gen
= 0.25µm
Supply voltage = 5V
Min width NMOS = 0.5µm
Process gen
= 0.25µm
Supply voltage = 5V
Min width NMOS = 0.5µm
Param
Value
1.42
fF/µm
Cd,P / µm
2.40
fF/µm
Cg,N / µm
1.55
fF/µm
Cg,P / µm
1.48
fF/µm
µm2
0.016
fF/µm2
CL,M2 / µm
0.084
fF/µm
CA,M2 /
Reff,N x µm
4.93
kΩ/µm
Reff,P x µm 10.83
kΩ/µm
RM2 / sq
0.07
16
Units
Cd,N / µm
Ω/sq
Metal 2 wire
(250u x 0.250u)
8
1
A
RP
RW
Cd
Cg
Cd
Rp
Rw
Cw
TPLH
2
CW/2
CW/2
Cg
= ( 0.5 x 1.55 ) + ( 1 x 1.48 ) = 2.26 fF
= (4 x 1.42 ) + ( 8 x 2.40 ) = 24.88 fF
= 10.83/8 = 1.35 kΩ
= ( 250 / 0.25 ) x 0.07 = 70 Ω
= (( 250 x 0.25 ) x 0.0016 ) + ( 250 x 0.084 ) = 21.14 fF
= 2.2 x ( 1350 x (21.14/2 + 24.88)
+ (1350 + 70) x (21.14/2 + 2.26) ) = 66ps
Param
Value
Units
Cd,N / µm
1.42
fF/µm
Cd,P / µm
2.40
fF/µm
Cg,N / µm
1.55
fF/µm
Cg,P / µm
1.48
fF/µm
µm2
0.016
fF/µm2
CL,M2 / µm
0.084
fF/µm
Reff,N x µm
4.93
kΩ/µm
Reff,P x µm 10.83
kΩ/µm
CA,M2 /
RM2 / sq
0.07
8
2
1
A
How should we buffer up this signal?
Should we have a few big stages or
many small stages?
2
8
16
2
6
10
14
16
1
2
8
1
3
5
7
8
Ω/sq
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 33
In deep submicron technologies many
predicted an interconnect doomsday
Metal 2 wire
(250u x 0.250u)
16
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 34
Is there really an
interconnect doomsday looming?
Local wire delay
tracks improvement
in gate delay
Scaling
Impact
National Technology Roadmap for Semiconductors, SIA, 1997
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 35
Affect on
Affect on
Resistance Capacitance
Length
Decreases
Decreases
Decrease
Width
Decreases
Increases
Decrease
Height
~ Constant
--
--
R. Ho, K. Mai, M. Horowitz, Proc. of the IEEE, Apr 2001
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 36
Is there really an
interconnect doomsday looming?
Scaling
Impact
Affect on
Affect on
Resistance Capacitance
Length
~ Constant
--
--
Width
Decreases
Increases
Decrease
Height
~ Constant
--
--
R. Ho, K. Mai, M. Horowitz, Proc. of the IEEE, Apr 2001
No doomsday, just one more physical
design issue to carefully manage
Global wire delay
increases relative to
wire delay!
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 37
Take away points
• Simple RC models of CMOS transistors, gates, and
wires can provide reasonable insight into the power and
delay of circuits
• A methodological approach enables creating static
CMOS gates relatively straightforward
• Although global wire delay is getting worse relative to
gate delay, local wire delay is scaling with gate delay
which forces designers to better manage global wires
early in the design process
Next Lecture: Srini Devadas will be
discussing algorithms and issues in
synthesis and place+route
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 39
National Technology Roadmap for Semiconductors, SIA, 2005
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 38