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Semiconductor Memory ECE 3710 Fall 2006 1 Memory: basic concepts • Stores large number of bits … m x n: m words of n bits each k = Log2(m) address input signals or m = 2k words e.g., 4,096 x 8 memory: m words – – – – m × n memory … n bits per word • 32,768 bits • 12 address input signals • 8 input/output data signals memory external view r/w • Memory access 2k × n read and write memory enable – r/w: selects read or write – enable: read or write only when asserted – multiport: multiple accesses to different locations simultaneously A0 … Ak-1 … Qn-1 Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 Q0 2 • Traditional ROM/RAM distinctions – ROM • – Advanced ROMs can be written to • – Life of product Battery life (10 years) e.g., EEPROM Ideal memory OTP ROM EPROM EEPROM FLASH NVRAM Nonvolatile In-system programmable SRAM/DRAM Near zero Write ability e.g., NVRAM Write ability – Mask-programmed ROM Tens of years Advanced RAMs can hold bits without power • • read and write, lose stored bits without power Traditional distinctions blurred – • read only, bits stored without power RAM • • Storage permanence Write ability and storage permanence Manner and speed a memory can be written During External External External fabrication programmer, programmer, programmer 1,000s OR in-system, only one time only 1,000s of cycles of cycles External In-system, fast programmer writes, OR in-system, unlimited block-oriented cycles writes, 1,000s of cycles Storage permanence – Ability of memory to hold stored bits after they are written Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis Write ability and storage permanence of memories, showing relative degrees along each axis (not to scale). ECE 3710 Fall 2008 3 Writability • Ranges of writability – High end • processor writes to memory simply and quickly • e.g., RAM – Middle range • processor writes to memory, but slower • e.g., FLASH, EEPROM – Lower range • special equipment, “programmer”, must be used to write to memory • e.g., EPROM, OTP ROM – Low end • bits stored only during fabrication • e.g., Mask-programmed ROM • In-system programmable memory – Can be written to by a processor in the microcomputer system using the memory – Memories in high end and middle range of write ability Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 4 Storage permanence • Range of storage permanence – High end • essentially never loses bits • e.g., mask-programmed ROM – Middle range • holds bits days, months, or years after memory’s power source turned off • e.g., NVRAM – Lower range • holds bits as long as power supplied to memory • e.g., SRAM – Low end • begins to lose bits almost immediately after written – refreshing needed • e.g., DRAM • Nonvolatile memory – Holds bits after power is no longer supplied – High end and middle range of storage permanence Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 5 ROM: “Read-Only” Memory External view A0 Ak-1 – Store software program for general-purpose processor – Store constant data (parameters) needed by system – Implement combinational circuits (e.g., decoders) Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis 2k × n ROM enable … • Nonvolatile • Can be read from but not written to, by a processor in an microcomputer system • Traditionally written to, “programmed”, before inserting to microcomputer system • Uses ECE 3710 Fall 2008 … Qn-1 Q0 6 Example: 8 x 4 ROM • • • • Horizontal lines = words Vertical lines = data Lines connected only at circles Decoder sets word 2’s line to 1 if address input is 010 • Data lines Q3 and Q1 are set to 1 because there is a “programmed” connection with word 2’s line • Word 2 is not connected with data lines Q2 and Q0 • Output is 1010 Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis Internal view 8 × 4 ROM word 0 enable 3×8 decoder word 1 word 2 A0 A1 A2 word line data line programmable connection Q3 Q2 Q1 Q0 ECE 3710 Fall 2008 7 Mask-programmed ROM • Connections “programmed” at fabrication – set of masks • Lowest write ability – only once • Highest storage permanence – bits never change unless damaged • Typically used for final design of high-volume systems – spread out NRE (non-recurrent engineering) cost for a low unit cost Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 8 OTP ROM: One-time programmable ROM • Connections “programmed” after manufacture by user – – – – user provides file of desired contents of ROM file input to machine called ROM programmer each programmable connection is a fuse ROM programmer blows fuses where connections should not exist • Very low write ability – typically written only once and requires ROM programmer device • Very high storage permanence – bits don’t change unless reconnected to programmer and more fuses blown • Commonly used in final products – cheaper, harder to inadvertently modify Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 9 EPROM: Erasable programmable ROM • Programmable component is a MOS transistor – – – – – • Transistor has “floating” gate surrounded by an insulator (a) Negative charges form a channel between source and drain storing a logic 1 (b) Large positive voltage at gate causes negative charges to move out of channel and get trapped in floating gate storing a logic 0 (c) (Erase) Shining UV rays on surface of floating-gate causes negative charges to return to channel from floating gate restoring the logic 1 (d) An EPROM package showing quartz window through which UV light can pass 0V floating gate drain source (a) +15V (b) source drain Better write ability 5-30 min – can be erased and reprogrammed thousands of times • Reduced storage permanence – program lasts about 10 years but is susceptible to radiation and electric noise • Typically used during design development source (d) . Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis drain (c) ECE 3710 Fall 2008 10 Sample EPROM components Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 11 Sample EPROM programmers Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 12 EEPROM: Electrically erasable programmable ROM • Programmed and erased electronically – typically by using higher than normal voltage – can program and erase individual words • Better write ability – can be in-system programmable with built-in circuit to provide higher than normal voltage • built-in memory controller commonly used to hide details from memory user – writes very slow due to erasing and programming • “busy” pin indicates to processor EEPROM still writing – can be erased and programmed tens of thousands of times • Similar storage permanence to EPROM (about 10 years) • Far more convenient than EPROMs, but more expensive Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 13 FLASH • Extension of EEPROM – Same floating gate principle – Same write ability and storage permanence • Fast erase – Large blocks of memory erased at once, rather than one word at a time – Blocks typically several thousand bytes large • Writes to single words may be slower – Entire block must be read, word updated, then entire block written back • Used with embedded microcomputer systems storing large data items in nonvolatile memory – e.g., digital cameras, MP3, cell phones Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 14 Class Project Program Memory Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 15 Example Show how to use a 128K x 8 FLASH to implement an 8K x 8 FLASH. A13 – A16 13 A0 – A12 Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 16 RAM: “Random-access” memory external view • Typically volatile memory r/w – bits are not held without power supply • 2k × n read and write memory enable Read and written to easily by microprocessor during execution • Internal structure more complex than ROM A0 … Ak-1 … Qn-1 – a word consists of several memory cells, each storing 1 bit Q0 internal view I3 I2 I1 I0 – each input and output data line connects to each cell in its column 4×4 RAM enable – rd/wr connected to every cell – when row is enabled by decoder, each cell has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read 2×4 decoder A0 A1 Memory cell rd/wr To every cell Q3 Q2 Q1 Q0 Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 17 Basic types of RAM • SRAM: Static RAM memory cell internals – Memory cell uses flip-flop to store bit – Requires 6 transistors – Holds data as long as power supplied SRAM Data' • DRAM: Dynamic RAM – Memory cell uses MOS transistor and capacitor to store bit – More compact than SRAM – Retains data for only 2 – 4 ms – “Refresh” required due to capacitor leak Data W DRAM Data W • word’s cells refreshed when read – Slower to access than SRAM Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 18 RAM variations • PSRAM: Pseudo-static RAM – DRAM with built-in memory refresh controller – Popular low-cost high-density alternative to SRAM • NVRAM: Nonvolatile RAM – Holds data after external power removed – Battery-backed RAM • SRAM with own permanently connected battery • writes as fast as reads • no limit on number of writes unlike nonvolatile ROM-based memory – SRAM with EEPROM or FLASH • stores complete RAM contents on EEPROM or FLASH before power turned off Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 19 Class Project data/stack memory HM6264ALP Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 20 Example: HM6264 & 27C256 RAM/ROM devices • Low-cost low-capacity memory devices • Commonly used in 8-bit microcontroller-based embedded systems • First two numeric digits indicate device type – RAM: 62 – ROM: 27 • Subsequent digits indicate capacity in kilobits – 64 Kbits = 8 Kbytes – 256 Kbits = 32 Kbytes Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis 11-13, 15-19 2,23,21,24, 25, 3-10 22 data<7…0> addr<12...0> 11-13, 15-19 data<7…0> 27,26,2,23,21, addr<14...0> 24,25, 3-10 22 /OE 27 /WE 20 /CS1 26 CS2 HM6264 20 /OE /CS 27C256 block diagrams Device Access Time (ns) HM6264 85-100 27C256 90 Standby Pwr. (mW) .01 .5 Active Pwr. (mW) 15 100 Vcc Voltage (V) 5 5 device characteristics Read operation Write operation data data addr addr OE WE /CS1 /CS1 CS2 CS2 HM6264 timing diagrams ECE 3710 Fall 2008 21 DRAM Structure Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 22 The TMS4464 (64Kx4) DRAM But a 64K memory needs 16 address lines? Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 23 The TMS4464 DRAM Timing Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 24 DRAM Address Multiplexer 74LS157, quad 2-line to 1-line data selector/multiplexer Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 25 The 41256 (256Kx1) DRAM Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 26 Example: Address decoding • 16-bit address bus (A0 – A15) • Desired memory space: – EPROM 16 Kbytes (0000, ..., 3FFF) – RAM 8 Kbytes (4000, ..., 5FFF) Address A15 A14 A13 Enable inputs (active low) /CS_EPROM /CS_RAM 0000 – 1FFF 0 0 0 0 1 2000 – 3FFF 0 0 1 0 1 4000 – 5FFF 0 1 0 1 0 Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 27 Implementing combinational function • Any combinational circuit of n functions of same k variables can be done with 2k x n ROM • How could we implement the previous EPROM/RAM decoder with a tiny (and fast) 16-bit ROM circuit? – a = A15, b = A14, c = A13, y = /CS_EPROM, z = /CS_RAM Truth table Inputs (address) a b c 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Outputs y z 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis 8×2 ROM 0 0 1 1 1 1 1 1 enable c b a y 1 1 0 1 1 1 1 1 word 0 word 1 word 7 z ECE 3710 Fall 2008 28 Composing memory • • • Memory size needed often differs from size of readily available memories When available memory is larger, simply ignore unneeded high-order address bits and higher data lines When available memory is smaller, compose several smaller memories into one larger memory – – – Connect side-by-side to increase width of words Connect top to bottom to increase number of words • added high-order address line selects smaller memory containing desired word using a decoder Combine techniques to increase number and width of words Increase number of words 2m+1 × n ROM 2m × n ROM A0 Am-1 Am … … 1×2 decoder … 2m × n ROM enable … … … Qn-1 2m × 3n ROM 2m × n ROM enable Increase width of words A0 Am … 2m × n ROM … … Q3n-1 2m × n ROM Q2n-1 Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis A Increase number and width of words … … Q0 … enable Q0 ECE 3710 Fall 2008 outputs 29 Memory hierarchy • Want inexpensive, fast memory • Main memory – Large, inexpensive, slow memory stores entire program and data • Cache – Small, expensive, fast memory stores copy of likely accessed parts of larger memory – Can be multiple levels of cache Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis Processor Registers Cache Main memory Hard disk CD or DVD ECE 3710 Fall 2008 30 Cache • Usually designed with SRAM – faster but more expensive than DRAM • Usually on same chip as processor – space limited, so much smaller than off-chip main memory – faster access (1 cycle vs. several cycles for main memory) • Cache operation: – Request for main memory access (read or write) – First, check cache for copy • cache hit – copy is in cache, quick access • cache miss – copy not in cache, read address and possibly its neighbors into cache • Several cache design choices – cache mapping, replacement policies, and write techniques Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 31 Dual-port RAM (DPRAM) • Usually a static RAM circuit with two address and data bus connections – Shared RAM for two independent users • Flexible communication link between two processors – Master/slave Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 32 Serial memory interface • Typically EEPROM or FLASH memory – – – – Compact package Low cost Slow access A convenient program storage Serial vs. parallel interface (32 Kbytes) Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 33 Summary • Two memory categories: – Write ability – Storage permanence • Various RAM and ROM alternatives for different needs • Typically byte-wide memory components in embedded microcomputer systems • Compose smaller memory components into larger memory systems • Hierarchical memory even in many embedded systems Embedded Systems Design: A Unified Hardware/Software Introduction © 2000 Vahid & Givargis ECE 3710 Fall 2008 34