Download Bond Pad Parasitics

Microwave Interference Effects on Device,
Integrated Circuits and PC-Board System
A Presentation on Recent Progress
N. Goldsman, Y. Bai, A. Akturk, T. Chitnis, B. Jacob, J. Baker, A. Iliadis, J. Melngailis
10/10/01
Effects on PC-Board and System Level
Effects on Integrated Circuit Level
Effects on Device Level
Standard Planar Technology Implementation:
IC Chips on PC Board
Chip-to-Chip Connection on PC Board:
PC Board
Bond Pad
Die (Integrated Circuits)
Input
Output
Pins
Bond Wire
Transmission Line
Chip-to-Chip Connection
Bond Wire
Bond Pad
Pins
Input
Output
ICs
ICs
Transmission Line
IC Chip with Bond Pads
Bond Pad
Die
(Integrated Circuits)
Electro-Static Discharge
(ESD)
Close Shot of Bond Pad
Bonding Wire
Bond Pad
Metal
Insulator
Oxide
Si Substrate
Bond Wire
Classification of Bond Pads
 Analog Reference Pad
 Bi-Directional Pad with Buffer
 Ground Pad
 Input Pad with Buffer
 I/O Pad
 Padless Corner Pad
 Padless Spacer Pad
 Pad No Connect Pad
 Output Pad with Buffer
 Power Pad
ESD Pad
--- Eliminate Harmful Static Charge
Example I/O ESD Pad:
Bond Pad
ESD Transistor
PMOS
Pad Logic
ESD Transistor
NMOS
Layout
Schematic
Bond Pad Parasitics - Capacitance
Metal
Insulator
Oxide
Pad Parasitic Capacitance vs. Process
Plate Capacitor
Metal Layer
Substrate
C pad
Pad Capacitance (pF)
Si Substrate
(Ref: MOSIS)
160
140
120
100
80
60
40
20
0
1.5u
0.5u
0.35u
Process
0.25u
Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
IC Package
Bond
Pad
Bond
Wire
Pin
Package Parasitics
Die
Bond Wire & Pin
(Several nanoHenry)
Bond Pad
Bond Wire
Pin
Bond Pad
(Several Hundred
femto-Farad)
Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
Chip-to-Chip Connection on PC Board
Bond Pad
Bond Wire
Transmission Line
Pins
Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
Input
IC 1
Output
IC 2
IC 1
IC 2
Input
Output
Transmission Line
Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
Why to Match?
• Maximize Power Transformation
• Eliminate Reflection
Match impedance on board with bond pads, bond wire and pins:
IC 1
IC 2
Input
Output
Transmission Line
Tune to Z0
Tune to Z0
If Impedances are not matched, signals will get reflected.
Tune to Z0
Z0
CMOS Low Noise Amplifier
IC1 Input Circuit
• Inductor L1 and capacitors
C1 and C2 are on – chip
components for input
matching.
• Inductor L2 is the
downbond inductor and is
also used in input matching.
• In addition to the shown
components the pad
capacitance and package
model were taken into
consideration.
Matching
• Looking into the MOSFET M1, input impedance
Z in  sL 2 
g
1
 m L2
sC gs Cgs
Real part
• The real part is made to be 50 Ohms.
• Inductors L1 and C1 give additional degrees of freedom to have the
input resonate at 2.4 GHz
• Values are tuned to include effects of pad and package parasitics
• Models provided by the foundry were used for on-chip inductors and
capacitors.
Transistor sizing
• Sizing is an important factor in the Power consumed vs. Noise Figure
trade off. The expression below is derived by constraining the power
consumed and then optimizing the Noise Figure.
Wopt
1

3LCox Rs
 = Operating frequency
L = Device Length
Rs = Source Resistance
• Substituting appropriate values gives a transistor size of W = 200
microns.
CMOS LNA Layout
Input_C1
Input_L1 MOSFETs
Output_C2
Simulation Results
•Simulation results
–Operating at 2.4 GHz
–Power gain = 21 dB
–Noise Figure = 2.7 dB
–Supply voltage = 2.5V
–Idc = 7.5 mA
This is a test chip.
Results are obtained for an output termination of 50 Ohms
Effects of Bond Pad Parasitics on Circuit Performance
--- Matching
Example Circuit: RF Power Amplifier
Bond Pad, Bond
Wire, and Pin
PA without bond pads
or package parasitics
Bond Pad, Bond
Wire, and Pin
PA with bond pads and package parasitics
Bond pad, bond wire, and pin add together which shift the resonant frequency, decrease the
power gain, and narrow the bandwidth of the amplifier.
Device Switching Details
Performance Improves by
 the reduction of the capacitive load
 the utilization of the halo implants
General Device Hierarchy
=>
=>
=>
Governing Equations
<=
Device Equations are
solved for each mesh point
/
<=
Supplementary device
equations
\
=>
=> Supplementary
Lumped circuit
equation
Example Solutions of the Previous Equations
Potential Distribution:
The applied voltage at the gate is shared between the oxide and the
surface after the built-in voltages are deducted.
More electrons are attracted to the channel as VGS gets higher. This
also drags the surface potential to a higher level
As the gate voltage increases, the surface potential does not increase
linearly, causing the vertical electrical field to take higher values. This
might eventually lead to a breakdown, around 3MV/cm
Carrier Distribution:
To turn the device on, the minority carriers are attracted to the oxide
interface, ultimately they invert the surface and form a conductive channel,
by the application of a positive VGS for electrons and negative for holes
When the device is turned on, the accumulation of the carriers at the interface
forms the conductive path
Potential Distribution for VGS=1V and VGS=5V
VDS=1.5V and VSB=0V
VGS=1V EOX_MAX=3MV/cm
VGS=5V EOX_MAX=15MV/cm
Electron Concentration of NMOS throughout the substrate,
specifically around the interface, when the channel is on and
off
Off
On
The bump shows the
attracted carriers
Hole Concentration of PMOS throughout the substrate,
specifically around the interface, when the channel is on and
off
On
The bump shows the
attracted carriers
Off