Download Design and Use of Memory-Specific Test Structures to Ensure

Design and Use of Memory-Specific Test Structures to
Ensure SRAM Yield and Manufacturability
F. Duan, R. Castagnetti, R. Venkatraman,
O. Kobozeva and S. Ramesh
LSI Logic Corporation
Outline
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Products need very high-density and high-performance
memories without sacrificing yield and manufacturability
LSI Logic’s Industry-leading 1.87um2 embedded SRAM
bitcell in 130 nm CMOS SoC technology
Need for SRAM-specific test structures to ensure
robustness and manufacturability
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Accurately shows process-design interaction
Correlate to SRAM yield
Direct feedback for rapid process-improvement
Accurate SRAM device and cell characterization
RAMPCM for design rule robustness validation
Summary
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LSI Logic SRAM Technology for SoC
6T SRAM CELL SIZE (m m2)
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Smallest production
high-density SRAM in
180nm and 130nm
technology
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Fabricated by
standard CMOS SoC
process
LSI Logic
TSMC
INTEL
IBM
NEC
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4
3
2
1
80
130
180
Technology Node (nm)
“High-Density and High-Performance 6T-SRAM for System-on-Chip in
130 nm CMOS Technology,” 2001 VLSI Technology Symposium, pp. 105-106,
W. Kong, R. Venkatraman, R. Castagnetti, F. Duan and S. Ramesh.
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Why Do We Need for SRAM-specific Test
Structure? An Example
(a)
(b)
(c)
Structures to test metal bridging
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Electrical Test Data
Only structure (a) detects the early metal /contact bridging
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Features of Our Structures
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Compared to the conventional structures, our structures:
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More product-driven than process-development-driven
Accurately show process-design interaction
Correlate to functionality and yield directly
Identify the yield limiting factors quickly for fast process or
design improvements.
– Sensitive enough for ongoing monitoring and process
transfers.
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Test Structure Design and Results
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Yield correlation and improvement
SRAM manufacturability
SRAM device and cell characterization
RAMPCM chip
– Functional SRAM test chip
– Used for SRAM design rule validation
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Test Structures of Front-end Critical Layer Monitor
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Critical layers: island, poly
and contact
Monitor bridging current
from intra- and interlayers
Monitor shared-contact
connection
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Test Structures of Back-end Monitor
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Monitor bridging current
from:
– Contact and metal 1
(blue arrows)
– Metal 2 (red arrows)
– Metal 3 (black arrow)
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Example of a Test Structure For Poly Bridging
Test cell
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Test array
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Poly Bridging Data
100,000 cells
No poly bridging found in SRAM
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Metal Bridging and Correlation to SRAM Yield
100,000 cells
Detected early metal /contact bridging
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Yield
Metal Bridging and Correlation to SRAM Yield
(cont.)
1.0E-14
1.0E-12
1.0E-10
1.0E-08
Metal 1 Bridging Leakage Current (A)
Metal bridging identified as yield limiting factor
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Metal 1 Bridging Data after Process Improvement
100,000 cells
No metal bridging seen after improvement
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Test Structures for Manufacturability
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An illustration of test structure
List of test structures
Electrical data
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An Illustration of the Test Structure
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Sizing poly by 5% per
side
Build test cell to test its
effects on:
– Poly to poly bridging
– Poly to contact bridging
– Pull down transistor
leakage
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List of Test Structures for SRAM Manufacturability
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Sizing island
– Island to island bridging
– Transistor leakage
Sizing poly
– Poly to poly bridging
– Poly to contact bridging
– Transistor leakage
Sizing contact
– Contact to poly bridging
– Contact / metal 1 bridging
– Contact resistance
Sizing metal 1
– Metal 1 / contact bridging
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Effect of Poly Sizing – SRAM Poly to Poly Bridging
100,000 cells
Poly to poly spacing in SRAM is robust
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Effect of Poly Sizing – SRAM Poly to Contact
Bridging
100,000 cells
Poly to contact spacing in SRAM is robust
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Effect of Poly Sizing – SRAM Pull Down
Transistor Leakage
100,000 cells
All leakage currents are within device model spec
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Test Structures for Characterization
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Transistors in SRAM
– Due to the environmental difference (OPC, etc), transistors
in SRAM may behave differently compared to isolated
devices
– Need to measure transistor in the real SRAM array for
accurate characterization
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An illustration of test structures
Electrical data for transistor measurement
Cell characterization
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Illustration of Measuring SRAM Transistor
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Transistors in SRAM Cell
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Measure all the 6
transistors in 6T SRAM
– To compare cell
symmetry between left
and right
– To compare with isolated
devices
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Measure 4 orientations
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Saturation Current of Pass Gate Transistors
(Left, Right, Isolated Counterpart)
Good symmetry and little difference between iso. / dense
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Saturation Current of Pull Down Transistors
(Left, Right, Isolated Counterpart)
Good symmetry and little difference between iso. / dense
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Threshold Voltage of Pull Down Transistor in
4 Directions (0, 90, 180, 270)
Little difference of 4 different orientations
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SNM and Cell Current of 1.87 um2 Bitcell
(130nm Generation)
1.2
1.0
Vout
0.8
0.6
0.4
0.2
0.0
0.0
0.2
0.4
0.6
0.8
Vin
Butterfly curve
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1.0
1.2
0.001
0.003
0.005
0.007
0.009
Cell Current (A)
Cell current (L&R)
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RAMPCM Test Chip
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RAMPCM is a functional
SRAM test chip that is
used to prove robustness
of the most critical SRAM
design rules.
Size of the chip is 1M with
1024 row by 1024
columns
Every 64 columns
evaluate one critical
SRAM design rule
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RAMPCM Test Chip (continued)
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8 most critical design
rules are evaluated
Each design rule has 4
variations, distributed
across array
Data logs from failing dies
are used to extract
numbers of failing bits per
design rule variation
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RAMPCM Test Data -- Normalized Failure Rate
Within
process
window
Rule
DR
Tightness 1
x
x-D
x - 2D
x - 3D
1.0
0.9
1.1
1.1
DR
2
DR
3
DR
4
DR
5
DR
6
DR
7
DR
8
1.0
1.0
1.0
1.3
1.0
1.0
1.4
1.3
1.0
1.0
1.3
1.4
1.0
1.0
1.2
1.4
1.0
1.0
0.9
1.1
1.0
0.9
1.0
1.0
1.0
1.0
1.0
1.1
Note: More than 50Mb data for
each variation.
Design rules used
in 1.87 um2 cell
This data proves the robustness and
manufacturability of the 1.87 um2 bitcell
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Use of Test Structures in 90nm and Beyond
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Increased design-process interaction in 90nm and
beyond (Ex. OPC variation)
The test structure methodology we have presented today
becomes even more necessary for 90 nm and beyond
Gate leakage impact for SRAM must be accurately
evaluated
We have designed such necessary test structures for the
90nm node
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Summary
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We have designed and used SRAM-specific test
structures as effective tool for SRAM technology
development.
The data from these SRAM test structures provides us
direct feedback on process-design interactions and helps
to identify yield-limiting factors early and quickly.
The data (including from RAMPCM) is analyzed to prove
the robustness and manufacturability of our industryleading 1.87 um2 SRAM cell.
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