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Evaluation of the Operation for the Shift Register Circuit Implemented by Low Temperature Poly-Si Thin-Film Transistors Hung-Guang Liou1, Ya-Hsiang Tai2 1 Department of Photonics & Institute of Electro-Optical Engineering, NCTU, Hsinchu, Taiwan, 30010, R.O.C Department of Photonics & Display Institute, NCTU, Hsinchu, Taiwan, 30010, R.O.C Abstract In this paper, the LTPS TFT shift register circuit is simulated with Monte Carlo method to evaluate the effects due to the non-uniformity in the LTPS TFT characteristics. A computationally efficient method has been presented for the estimation of the power distribution and the yield in the presence of device variations. 1. characteristics. To evaluate the product performance and yield before the real fabrication, a proper simulation technique is strongly required. Similar studies are popular for MOSFETs [5] but not well noticed for LTPS TFTs. 20 stages Vdd Vdd Vdd Vdd Introduction CLK Low temperature poly-Si (LTPS) TFT technology appears to be one of the most promising technologies for ultimate goal of building fully-integrated AMLCD system on glass. [1] Development of the “System-on glass” display with low temperature poly-Si (LTPS) thin film transistors (TFTs) has rapidly advanced recently. The LTPS TFT LCDs achieve high resolution, high luminance displays as well as “System on glass” displays, which allow us to integrate various functional circuit s on to the display panels. The LTPS TFT contributes to making compact, highly reliable LCDs for mobile terminal devices. The LTPS TFT has also the possibility for realizing far more value-added circuit monolithically with the pixels on the array glass. [2] Therefore, the research efforts also have been focused on realization of system integration for LTPS TFT LCDs and have been developed various types of circuit-integrated LCDs so far. A shift register (SR) shown in Fig.1 is not only a basic circuit block in application of LCD scan/data driver, but also an important unit composing a sequential logic circuit such as timing controllers.[3,4] Considering the effects of non-uniformity characteristic in LTPD TFTs. This nonuniformity is due to the random variations of the silicon grains formed after laser annealing. The electrical parameters mainly affected by these variations are the threshold voltage VT and the mobility μ.Thus, operating in high speed and low voltage, the SR function can be diversely performed depending on the variant TFT V1 CLK V2 CLK V3 CLK V20 Vin CLK CLK CLK CLK Fig.1. an example of a 20 stages shift register circuit composed of clocked inverters and inverters. 2. Conventional Simulation Worst-Case analysis is the most commonly used technique in industry for considering manufacturing process tolerances in the design of digital integrated circuits. These approaches are relatively inexpensive compared to the yield maximization approaches in terms of computational cost and designer effort, and they also provide high parametric yields. Computer simulations were conducted using HSPICE program. LTPS TFT devices described by a level 62 RPI models are used to simulate how fast and slow the SR can operate. Fig. 2 is the conventional simulation results for the 20-stage Shift Register with VDD=3.3V. The threshold voltage parameters VTO and mobility parameters MU0 of N-type and P-type TFTs are +1 and -1V with the variation range of ±1V, as well as 77.1 and 85 cm2/Vs with the variation range of ±20cm2/Vs, respectively. In the Fig. 1 20th stage of output waveform (V) 5 Typical Model at 12.5MHz Fast Model at 22.2MHz Slow Model at 3.2MHz 4 3 20 15 10 5 0 2 18.0u 18.4u 18.8u 19.2u Power(uW) 1 0 0 25 50 75 100 125 Fig.3. 100 times MC simulation results for 20 stages of SR (a) output waveform (b) power distribution. Time / Clock Period (%) 3. 5 Typical Model at 13MHz Fast Model at 23MHz Slow Model at 4MHz 4 3 2 1 0 0 25 50 75 100 125 Time / Clock Period (%) Fig.2. Conventional simulation results of the SR circuit in (a) functional cases (b) failed cases 20th stage of output waveform (V) 20 stages 25 Distribution of Power 20th stage of output waveform (V) 2 , the typical, fast and slow operation frequencies of the Shift Register can exceed 12.5MHz, 22.2MHz, and 3.2MHz, correspondingly. [6] Fig. 2 also shows the failed result for the 20-stage Shift Register in order to compare with the normal operating 20-stage Shift Register. V1 4 3 2 1 V0 0 -1 2.1u 2.2u Time (us) Monte Carlo Simulation Because coping with macroscopic variations impact process control, while coping with microscopic variations impact circuit or device design tolerance [7], only considering the extreme cases, the conventional simulation methods might overstretch the operating range prediction for the circuit performance. Assuming the behaviors of the TFTs device parameters are randomly distributed in a Gaussian way, Monte Carlo (MC) method [8,9] is used to estimate the circuit performance of LTPS TFT circuit instead. The 3σ variation of the normal distributions for VTO and MU0 are set to ± 20cm2/Vs and ± 1V, respectively. The circuit operating at 10, 11, and 12MHz is simulated for 100 times. The simulated output waveforms and the power distribution at 10MHz are shown in Fig. 3. The output failure can be identified by the V0 and V1 indicated in Fig. 3(a). The high voltage of V0 and the low V1 correspond to two types of failure, which are indicated by LV1 and HV0, respectively. The output waveforms at the 20th stage for the 10MHz case are plotted in Fig. 3(a) and the statistics of the power dissipation for the good cases is shown in Fig. 3(b), which exhibits normal distribution. This MC approach is believed to give better approximation to the actual circuit performance for LTPS TFTs because that it makes no restrictive assumptions on the nature of the relationship between the circuit parameters and the circuit performance. However, Monte Carlo sampling is still expensive in terms of computational cost due to the large number of sample and the high cost circuit simulations. Therefore, a fast novel simulation method is proposed to reduce long time consumption. 2.3u 4. Reduction of MC Simulation Methods to reduce simulation time were explored. [10,11] A new method only involving 3 stages of SR is proposed to 2 approximate the simulated results for 20 stages. The simulated output waveforms and the power distribution at 10MHz are shown in Fig. 4. (PMC3) Average (PEn) = Average (PMC3) × n / 3 3th stage of output waveform (V) Deviation (PEn) = Deviation (PMC3) × 3 2 V0 HV0MC3 0 LV1MC3 1.3u 1.4u Time(us) HV0E20 1.5u LV1E20 HV0MC20 LV1MC20 ERROR HV0 30 Distribution of power eq. (4) Table I. Failure Rate Estimation for 20-stage SR circuit 1 -1 n /3 respectively. The comparison between PE20 and PMC20 at 10, 11, and 12MHz is listed in Table II. For the frequencies with enough good cases, the errors for the average and deviation are as low as 3% and 8%, respectively. V1 4 eq. (3) and ERROR LV1 3 stages 10M 1% 3% 9% 24% 3% 17% 6% 7% Failure Rate 11M 12M 2% 5% 10% 19% 17% 37% 61% 85% 6% 7% 61% 90% 11% 30% 0% -5% Remark 3-stage Monte Carlo 1- [ 1- (HV0MC3 )9 ] 1- [ 1- (LV1MC3 )9 ] 20-stage Monte Carlo HV0MC3 - HV0MC20 LV1MC3 - LV1MC20 25 Table II. Power Estimation for 20-stage SR Circuit 20 15 10 5 0 2.5u 2.6u 2.7u 2.8u 2.9u 3.0u Power(uW) Fig.4. 100 times MC simulation results for 3 stages of SR (a) output waveform (b) power distribution. The estimated failure rates of LV1 and HV0 for an n-stage SR circuit (LV1En and HV0En) can be calculated based on the failure rate for 3-stage SR from MC simulation (LV1MC3 and HV0MC3) by LV1En = 1 - [1- (LV1MC3)(n/2 -1)] eq. (1) and HV0En = 1 - [1- (HV0MC3)(n/2 -1)] eq. (2) correspondingly. Table I lists the failure rate estimations of 20 stages Shift Register circuit with the proposed method and the MC method. The errors for LV1 and HV0 at different frequencies are lower than 7% and 30%, respectively. As for the power consumption, after excluding the failed cases, the linearly product method can be applied. That is, the power distribution of an n-stage SR circuit (PEn) can be estimated by the results of MC simulation for 3-stage SR Power Distribution for the Good Cases 10MHz 11MHz 12MHz Remark PMC3 2.73 3.00 3.14 uW 3-stage Monte Carl ±0.09 ±0.10 ±0.345 uW Good case # 96 88 76 PE20 18.17 20.03 20.90 uW PMC3 x 20 / 3 ±0.23 ±0.26 ±0.89 uW PMC3 x √20 / 3 PMC20 18.58 20.59 22.52 uW 20-stage Monte Ca ±0.25 ±0.28 ±0.276 uW 33 3 Good case # 80 ERRORavg -2.2% -2.7% -7.2% (PE20-PMC20)/PM ERRORdev -8.3% -8.2% 223.8% 5. Conclusions Monte Carlo simulation method is applied to the estimation of power and yield for LTPS TFT Shift Register circuits to compare with the conventional simulation one. It provides better prediction of the circuit performance for the variation range. Furthermore, a new method is proposed to save the time consumption. The proposed method can quickly estimate not only the yield rate but also the power distribution for the multi-stage SR circuits. 3 6. Acknowledgements We would like to thank the Toppoly Optoelectronics Corporation for their technical support. This work has been sponsored by NSC 93-2215-E-009-075. References 1. K. Werner, “The flowering of flat displays”, IEEE Spectrum, Vol. 34, p.45, (1997) 2. Y. Nakajima, Y. Kida, M. Murase, Y. Toyoshima, and Y. Maki “Latest Development of ’System-on-Glass’ Display with Low Temperature Poly-Si TFT”, SID 2004 Digest, p. 864, (2004). 3. J. M. Rabaey, A. Chandrakasan, Anantha, and B. Nikolic’, “Digital Integrated Circuit”, Prentice Hall, New Jersey (1996) 4. S. M. Kang, and Y. Leblebici, “CMOS digital integrated Circuits”, Boston, MA: WCB/McGraw-Hill (1999) 5. K. Okada, K. Yamaoka, and H. Onodera, “Statistical modeling of gate-delay variation with consideration of intra-gate variability”, IEEE ISCAS, Vol. 5, p. 513 (2003) 6. S. Gavrilov, A. Glebov, S. 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