Download THAT Corporation Design Note 100

THAT Corporation Design Note 100
A Fully Adjustable
Noise Gate
The circuits within this application note feature THAT4301 Analog Engine® to provide
the essential elements of voltage-controlled amplifier (VCA) and rms-level detector (RMS).
Since writing this note, THAT has introduced several new models of Analog Engines, as well
as new VCAs. With minor modifications, these newer ICs are generally applicable to the
designs shown herein, and may offer advantages in performance, cost, power consumption,
etc., depending on the design requirements. As well, a standalone RMS is available to
complement our standalone VCAs. We encourage readers to consider the following alternatives in addition to the 4301:
•
Low supply voltage and power consumption: 4320
•
Low cost, supply voltage, and power consumption: 4315
•
Low cost and power consumption: 4305
•
High-performance (VCA only): 2180-series, 2181-series
•
Dual (VCA only): 2162
•
RMS (standalone): 2252
For more information about making these substitutions, please contact
THAT Corporation's technical support group at [email protected].
45 Sumner St, Milford, MA 01757-1656 USA; www.thatcorp.com; [email protected]
Copyright © 2001 - 2013 by THAT Corporation; All rights reserved.
Document 600144 Revision 02
THAT Corporation Design Note 100
A Fully Adjustable Noise Gate
Gates are useful for suppressing background noise in the absence of masking source
material, but for a gate to sound “natural”, it can be desirable to control one or more of the
following parameters:
• the threshold below which the gate acts;
• the hold time which prevents gating action during brief pauses in the source material;
• the release rate during which the gain is smoothly “faded” down.
The circuit shown in Figure 1 is a feedforward design with independent, variable control of
each gating parameter. Gates need to react quickly to be effective, so the level detector
timing must be very fast. A fast detector, however, results in ripple on its output
waveform. Ripple, in turn, can cause "false" triggering of the gate when the detector output
is very near the trip point of the threshold comparator.
A solution is to use a timing circuit we refer to as the "non-linear capacitor" or "NLC",
shown in Figure 1 around OA2. This circuit utilizes the Miller Effect to amplify the effect of
C6 while the change in the voltage at pin 5 is small enough to avoid turning on D1 or D2.
When these devices do turn on, the gain of OA2 is reduced and the contribution of C6 is
only 100nF. The exact tuning of the NLC is best done by ear, but there is an in-depth explanation of this circuit, which includes some rough guidelines for tuning, at the end of THAT
Corporation's Design Note 03 (formerly Application Note 103). We suggest reviewing that
document before beginning to tweak the circuit's performance.
Q1 and Q2 form logarithmically adjustable current sources, and Q3 sets their full-scale
currents. The rest of the design is relatively straightforward. The current through Q3 is the
program current, and it sets up a voltage across Q3’s base-emitter junction. When VR4 and
VR5 are adjusted to put this same voltage on their VBE‘s, they will have the same program
current running through them. The potentiometers allow the individual transistors currents
to be adjusted, and as a results of the logarithmic nature of transistors, the current will
vary by a factor of 10 for each 60mV change in VBE. The divider networks on each adjustment
limit the dynamic range of the controls, since a VBE = 0.6V divided by 60mV/decade yields a
range of 10 decades, much too large in practical terms.
U2A and U2B are connected as comparators, with VR3 providing a means for adjusting
the threshold. While the signal is above threshold, the LM393 steals all the current from Q1,
and the output of U2B is forced low. In the steady state condition, the output of U3A (we
used a FET input op-amp) will be high. VR1 is used to trim the output of U1D to yield a VCA
gain of one.
When the signal level drops below threshold, the output of U2A become a high impedance,
and the current in Q1 causes the voltage on C4 to ramp upwards. After a time, which is
directly proportional to the current in Q1, the comparator, U2B, trips and its output
becomes a high impedance, allowing the integrator, U3A, to ramp down at a rate that is
directly proportional to the current in Q2. This is how the release rate is set.
Copyright © 2001-2013
by THAT Corporation
All rights reserved.
45 Sumner St, Milford, MA 01757 USA; www.thatcorp.com
Design Note 100
Page 2 of 3
Doc. 600144 Rev. 02
Vin
Copyright © 2001-2013
by THAT Corporation
All rights reserved.
R16 +C12
28k8 47u
V-
CT
IT
4
C3
50n
4301P
RMS 5
OUT
IN
U1B
R6
2M0
2
1
Threshold at -10dBu
Threshold
VR3
50k
R18
2k
R19
150k
45 Sumner St, Milford, MA 01757 USA; www.thatcorp.com
7
1
V-
100n
100n
100n
100n
V+
D4
1N4148
100n
V-
V+ Bypass for LF353
C10
C11
R5
10k
Release
Rate
R20
30k
100n
D6
1
C1
220n
R14
100k
VR1 R13
50k 2M
-3dB
R7
110k
VUnity Gain Trim
+3dB
LF353
V+
3 U3A
2
1N4148
R11
1k
C16 provides thereturn path for the
transient current thru R4, D6, and C1,
and should be connected directly between
the V+ of U3 and theV- of U2
C16
VBypass for LM393
7
R15
100k
Q3
2SA1015
VR5
20k
V+
V-
12
4301P
OA3
47p
R2
20k
U1A
C14
Q2
2SA1015
C15
10u
15
EC+ 14
11
R1 17 SYM V+ 13
IN VCA OUT
V20k
GND 10
EC- 9
C9
4301P 16
R10
300k
V+
R9
51R
R4
6 U2B
10k
LM393
D5
1N4148
5
V-
V+
C8
C4
100n
D3
1N4148
5k1
R21
V+
Hold Time VR4
20k
R3
20k
C7
V+
LM393
3 U2A
2
Q1
2SA1015
4301P
8 OA2
D1
LED
D2
LED
6 U1C
2n2
R8
C5 1M
100n
C6
V-
V+
V+
47u
C13
Symmetry
VR2
50k
V+
18
U1D
4301P
20 OA1
19
R12
2k49
Vout
THAT Corporation Design Note 100
A Fully Adjustable Noise Gate
Design Note 100
Page 3 of 3
Doc. 600144 Rev. 02