Download CMOS CIRCUIT TECHNOLOGY

CMOS CIRCUIT TECHNOLOGY
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NMOS & PMOS TRANSISTOR SWITCH
NMOS & PMOS AS LOGIC CIRCUITS
NMOS & PMOS LOGIC GATES
CMOS LOGIC GATES
POSITIVE & NEGATIVE LOGIC
PHYSICAL CHARACTERISTICS
PASS-TRANSISTORS
PASSING 1’S AND 0’S
TRANSMISSION GATES
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
1
NMOS & PMOS TRANSISTOR SWITCH
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NMOS TRANSISTOR SWITCH
GATE
VG
HIGH
X=1
VD
VS
DRAIN
SOURCE
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LOW
X=0
PMOS TRANSISTOR SWITCH
GATE
VG
VS
SOURCE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
HIGH
X=1
LOW
X=0
VD
DRAIN
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NMOS & PMOS AS LOGIC CIRCUITS
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NMOS AS LOGIC CIRCUITS:
VDD IS THE HIGH VOLTAGE FROM THE POWER SUPPLY
0 VOLTS IS THE LOW VOLTAGE,GROUND POLARITY
VD
VD
VD
VG
VD= 0
VD= 0
CLOSED
SWITCH
WHEN
VG = VDD
VD= 0
OPEN
SWITCH
WHEN
VG = 0
IN NMOS, WHEN TURNED ON, VD IS PULLED DOWN TO GROUND
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
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NMOS & PMOS AS LOGIC CIRCUITS
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PMOS AS LOGIC CIRCUITS:
VDD IS THE HIGH VOLTAGE FROM THE POWER SUPPLY
0 VOLTS IS THE LOW VOLTAGE,GROUND POLARITY
VS
V DD
V DD
VG
VD
VD= 0
OPEN
SWITCH
WHEN
VG = VDD
V D = V DD
CLOSED
SWITCH
WHEN
VG = 0
IN PMOS, WHEN TURNED ON, VD IS PULLED UP TO VDD
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
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NMOS & PMOS LOGIC GATES
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NMOS LOGIC GATES: THE NOT GATE
THERE IS POWER DISSIPATION IN STEADY STATE
V DD
V DD
H
Vf
GROUND
L
VX
Vf
VX
VX
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
V
H
L
X
V
f
L
H
Vf
LOGIC SYMBOL
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NMOS & PMOS LOGIC GATES
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NMOS LOGIC GATES: THE NAND GATE
THERE IS POWER DISSIPATION IN STEADY STATE
V DD
V
Vf
VX
VY
LOGIC SYMBOL
L
L
H
H
X
V
L
H
L
H
Y
V
f
H
H
H
L
IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NAND GATE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
6
NMOS & PMOS LOGIC GATES
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NMOS LOGIC GATES: THE NOR GATE
THERE IS POWER DISSIPATION IN STEADY STATE
V
DD
V
V
V
X
V
X
L
L
H
H
f
Y
V
L
H
L
H
Y
V
f
H
L
L
L
LOGIC SYMBOL
IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NOR GATE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
7
NMOS & PMOS LOGIC GATES
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NMOS LOGIC GATES: THE AND GATE
THERE IS POWER DISSIPATION IN STEADY STATE
V
DD
V
DD
V
V
V
V
f
V
X
V
Y
V
f
f
X
Y
LOGIC SYMBOL
L
L
H
H
L
H
L
H
L
L
L
H
IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE AND GATE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
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NMOS & PMOS LOGIC GATES
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NMOS LOGIC GATES: SUMMARY
THERE IS POWER DISSIPATION IN STEADY STATE
V
PULL-UP DEVICE
DD
V
V
V
X
.
.
.
Z
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
PULL-DOWN NETWORK
(PDN)
f
S
NMO ORS
S
I
S T
TRAN
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NMOS & PMOS LOGIC GATES
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PMOS LOGIC GATES: THE NOT GATE
THERE IS POWER DISSIPATION IN STEADY STATE
V DD
VX
V DD
H
VX
Vf
Vf
GROUND
L
VX
Vf
V
H
L
X
V
f
L
H
LOGIC SYMBOL
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
10
NMOS & PMOS LOGIC GATES
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PMOS LOGIC GATES: THE NAND GATE
THERE IS POWER DISSIPATION IN STEADY STATE
V
V DD
VX
X
V
Y
V
f
VY
Vf
LOGIC SYMBOL
L
L
H
H
L
H
L
H
H
H
H
L
IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NAND GATE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
11
NMOS & PMOS LOGIC GATES
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PMOS LOGIC GATES: THE NOR GATE
THERE IS POWER DISSIPATION IN STEADY STATE
V
V
V
DD
V
V
L
L
H
H
X
Y
f
LOGIC SYMBOL
X
V
L
H
L
H
Y
V
f
H
L
L
L
IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE NOR GATE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
12
NMOS & PMOS LOGIC GATES
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PMOS LOGIC GATES: THE AND GATE
THERE IS POWER DISSIPATION IN STEADY STATE
V DD
V DD
V
VX
VY
Vf
LOGIC SYMBOL
L
L
H
H
X
V
L
H
L
H
Y
V
f
L
L
L
H
IF {H = 1, L = 0} THEN THE CIRCUIT PRODUCES THE AND GATE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
13
NMOS & PMOS LOGIC GATES
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PMOS LOGIC GATES: SUMMARY
THERE IS POWER DISSIPATION IN STEADY STATE
V
V
V
X
.
.
.
Z
DD
PULL-UP NETWORK
(PUN)
S
PMO ORS
T
S
I
S
TRAN
V
f
PULL-DOWN DEVICE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
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CMOS LOGIC GATES
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TO EVOID STEADY STATE POWER DISSIPATION
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THE PULL-UP DEVICE, USED IN NMOS LOGIC GATES, IS REPLACED BY A PULL-UP NETWORK
BUILT WITH PMOS TRANSISTORS.
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THE PULL-DOWN DEVICE, USED IN PMOS LOGIC GATES, IS REPLACED BY A PULL-DOWN
NETWORK BUILT WITH NMOS TRANSISTORS.
V DD
PULL-UP NETWORK
(PUN)
VX
Vf
VZ
PULL-DOWN NETWORK
(PDN)
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
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CMOS LOGIC GATES
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CMOS CIRCUIT : NOT GATE
V DD
VX
T1
Vf
T2
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
VX
T1
T2
V
L
ON OFF
H
H
OFF ON
L
f
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CMOS LOGIC GATES
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CMOS CUIRCUIT
V DD
T1
VX
VY
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
VX VY
T1
L
L
H
H
ON ON OFF OFF
ON OFF OFF ON
OFF ON ON OFF
OFF OFF ON ON
L
H
L
H
T2
T3 T4
V
f
H
H
H
L
T2
Vf
T3
T4
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CMOS LOGIC GATES
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PROCEDURE TO CONSTRUCT CMOS COMPLEX LOGIC GATES F.
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THE PULL-UP NETWORK IS CONSTRUCTED WITH F USING ONLY
PMOS TRANSISTORS. THE POLARITIES OF THE VARIABLES ARE
COMPLEMENTED
THE PULL-DOWN NETWORK IS CONSTRUCTED WITH !F USING
ONLY NMOS TRANSISTORS.
PUN AND PDN ARE MUTUALLY EXCLUSIVE. THEY CANNOT BE
CONDUCTING AT THE SAME TIME. THE OUTPUT Vf CANNOT BE
HIGH AND LOW SIMULTANEOUSLY. IF BOTH NETWORKS ARE NOT
CONDUCTING, THEN THE OUTPUT IS SAID TO BE FLOWTING OR
PESENTING HIGH IMPIDANCE.
THE POLARITY OF THE INPUT VARIABLES IS THE SAME FOR
BOTH NETWORKS.
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
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CMOS LOGIC GATES
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GENERAL STRUCTURE OF A CMOS COMPLEX LOGIC GATE
CIRCUIT F.
V DD
INPUT VARIABLES
PULL-UP NETWORK :
SYNTHESIZE F
COMPLEMENTING THE
POLARITY OF THE
VARIABLES. THESE ARE
INPUTS TO PMOS
TRANSISTORS
OUTPUT F
PULL-DOWN NETWORK :
SYNTHESIZE !F WITH THE
POLARITY OF THE
VARIABLES UNCHANGED.
THESE ARE INPUTS TO
NMOS TRANSISTORS
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
19
CMOS LOGIC GATES
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EXAMPLE OF A CMOS COMPLEX LOGIC GATE
CIRCUIT F.
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DESIGN A CMOS CIRCUIT PRODUCING THE
FUNCTION F(A,B,C,D) = !A + (!B +!C) !D.
!F(A,B,C,D) = A(BC + D)
D
PULL-UP NETWORK
A
B
C
F
A
PULL-DOWN NETWORK
B
D
C
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
20
POSITIVE & NEGATIVE LOGIC
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THE BEHAVIOR OF A SWITCHING DEVICE, LIKE A CMOS GATE, IS
GIVEN IN TERMS OF HIGH AND LOW VOLTAGES. FOR A GIVEN
DEVICE, THIS BEHAVIOR IS UNIQUE.
HOWEVER, ITS LOGIC BEHAVIOR CAN BE DEFINED EITHER WITH
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POSITIVE LOGIC CONVENCTION: HIGH FOR 1 ; LOW FOR 0
OR WITH
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NEGATIVE LOGIC CONVENCTION: HIGH FOR 0; LOW FOR 1.
IN GENERAL THE LOGIC BEHAVIOR OF A SWITCHING DEVICE MAY BE
DIFFERENT IN POSITIVE AND NEGATIVE LOGICS. FOR EXAMPLE, THE
CMOS DEVICE ON NEXT SLIDE REPRESENTS THE NAND GATE IN
POSITIVE LOGIC AND THE NOR GATE IN NEGATIVE LOGIC
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
21
POSITIVE & NEGATIVE LOGIC
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EXAMPLE OF POSITIVE AND NEGATIVE LOGICS
V
T
V
V
DD
1
T
2
Vf
X
T
Y
T
3
4
PHYSICAL
BEHAVIOR
V X VY V f
L L
H
L H H
H L H
H H L
SWITCHING DEVICE NOR LOGIC GATE NAND LOGIC GATE
1
2
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
POSITIVE NEGATIVE
LOGIC
LOGIC
X Y F
X Y
F
0 0 1
1 1
0
0 1 1
1 0
0
1 0 1
0 1
0
1 1 0
0 0
1
a1
b1
5
a2
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PHYSICAL CHARACTERISTICS
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TRANSISTOR AS A SWITCH
STATIC CURRENT
NOISE MARGIN
DYNAMIC OPERATION
PROPAGATION DELAY
POWER DISSIPATION
FAN-IN/FAN-OUT
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
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PHYSICAL CHARACTERISTICS
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TRANSISTOR AS A SWITCH: STATIC CURRENT; THE NOT GATE
V DD
R
PULL-UP DEVICE
I SAT
V f = V OL
Vf  V
RDS
DD RDS  R
Vf
VX
R DS
I SAT
V X = HIGH VOLTAGE
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Vf
0.2V


 0.2mA
RDS 1K
WHEN THE TRASISTOR IS CUT-OFF, IT CAN CONDUCT A VERY
LOW CURRENT, CALLED LEAKAGE CURRENT
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
24
PHYSICAL CHARACTERISTICS
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VOLTAGE TRANSFER CHARACTERISTIC
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VT is the threshold voltage ~ 0.2 VDD
VOH is the output high voltage = VDD
VOL is the output low voltage = 0.2 volts
The plot of Vf versus Vx shows the voltage transfer characteristic
Vf
OFF
Slop = -1
VOH = VDD
VOL = 0 v.
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
VT
VT1
VD
VX
D
VIH(VDD – VT)
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PHYSICAL CHARACTERISTICS
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NOISE MARGIN
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TWO MARGINS: NML , NMH
BY DEFINITION: NML = VIL - VOL ; NMH = VOH – VIL
EXAMPLE: FOR CMOS SWITCHING CIRCUITS
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LET VOH = VDD AND VOL= 0 v.
Finding the two points where SLOPE = -1
VIL~ 1/8 (3 VDD + 2 VT), VIH~ 1/8 (5 VDD - 2 VT)
IF VT = 0.2 VDD THEN NML = NMH = 0.425 VDD
For VDD = 5 v. NML = NMH = 2.1 v.
For VDD = 3.3 v. NML = NMH = 1.4 v.
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
26
PHYSICAL CHARACTERISTICS
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DYNAMIC OPERATION
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LET US CONSIDER TWO INVERTERS CONNECTED IN CASCADE
V
V
T
DD
T
1
X
1
V
A
T
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V
DD
2
T
F
2
CAPACITIVE LOAD AT NODE A IS DUE TO SILICON
CONSTRUCTION OF TRANSISTOR. IT IS CALLED PARASITIC OR
STRAY CAPACITANCE
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
27
PHYSICAL CHARACTERISTICS
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DYNAMIC OPERATION (Continues)
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Each transistor contributes a GATE CAPACITANCE
Cg = W . L . Cox
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where Cox is called OXIDE CAPACITANCE and depends on
technology and is given in f F/µm2 units
Other capacitance is due to wiring.
ALL THESE CAPACITANCE ARE REPRESENTED BY C.
C AFFECTS THE SPEED OF OPERATION OF THE CIRCUIT
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
28
PHYSICAL CHARACTERISTICS
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PROPAGATION DELAY is defined as the time required to discharge C
through the NMOS transistor voltage VDD/2 and it is given by the
formula
V

C   DD 
2
C  V

tp 

ID
ID
or
1.7C
tp 
kn W VDD
L
 
where kn’ is the process transconductance parameter, W the width
and L the length of the substrate.
For PMOS, the propagation delay is computed by choosing the
corresponding kn’ .
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
29
PHYSICAL CHARACTERISTICS
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POWER DISSIPATION
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Is the amount of power used by a transistor. It must be
small
Consider the inverter:
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For Vx = 0, no current flows, and therefore, no power is
consumed.
For Vx = 5 v., the current flowing is ISAT, the power dissipated is
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PS = ISAT VDD. If ISAT = 0.2 mA, then
PS = 0.2 x 5 = 1.0 mW
10 000 inverters will dissipate 10 watts
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
30
PHYSICAL CHARACTERISTICS
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POWER DISSIPATION (Continues)
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Steady state power dissipation: is the power dissipated in
steady state current flow.
Dynamic power dissipation: is the power dissipated due to
the switching action.
NMOS circuits present STATIC and DYNAMIC power
dissipation
PMOS circuits present STATIC and DYNAMIC power
dissipation
CMOS circuits present ONLY DYNAMIC power dissipation
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
31
PHYSICAL CHARACTERISTICS
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POWER DISSIPATION (Continues)
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CMOS CIRCUITS POWER DISSIPATION:
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THE ENERGY STORED IN THE CAPACITOR IS
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E =(C VDD2)/2
FOR CHARGING AND DISCHARGING THE CAPACITOR, THE
TOTAL ENERGY IS 2 E = C VDD2.
POWER = ENERGY PER UNIT TIME
IF THE CYCLE TIME (CHARGE – DISCHARGE PER SECOND) IS
EQUAL TO f, THEN THE
DYNAMIC POWER CONSUMED IS PD = f C VDD2
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
32
PHYSICAL CHARACTERISTICS
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FAN-IN/FAN-OUT
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FAN-IN of a circuit is the number of its inputs.
It is given by the formula:
tp 
1.7C
k
W
kn
V
L DD
 
where k is the number of inputs and C is the equivalent capacitance at the output
of the gate
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FAN-OUT of a circuit is the maximum number of circuits, n, that can be connected
to its output. Then, the capacitor in the above equation is Cn = n x C. The
propagation delay is computed by the same formula.
NAND’S with small FAN-IN are constructed with NMOS transistors
NOR’S with large FAN-IN are constructed with NMOS transistors: k transistors in parallel
~ k x W; C, however, increases the load.
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
33
PASS-TRANSISTORS
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PASSING 1’S AND 0’
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Let us consider the following two configurations
V DD
V DD
A
B
VA = VDD – VT
VB is not quite equal to 0 v
NOT FULLY PASSING VDD
NOT FULLY PASSING 0 v.
THIS IS DUE TO WHAT IS CALLED BODY EFFECT. BOTH SUBSTRATES
ARE BIASED TO VDD WHICH INCREASES THE THRESHOLD VOLTAGE, VT,
BY A FACTOR OF 1.5 V..
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
34
TRANSMISSION GATES
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A TRANSMISSION GATE (T-GATE) IS A CMOS CIRCUIT THAT PASSES, EQUALLY WELL,
THE HIGH AND THE LOW VOLTAGES.
BOTH PATHS ARE EITHER SIMULTANEOUSLY CONNECTING OR SIMULTANEOUSLY
DISCONECTING X TO F.
A T-GATE DRIVES ITS OUTPUT EITHER TO LOW OR TO HIGH EQUALLY WELL.
EXAMPLE:
!S
F
X
S
F
0
1
HIGH IMPEDANCE: Z
X
TG
S=0
X
S
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
X
F=Z
S=1
F=X
35
TRANSMISSION GATES
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ANOTHER EXAMPLE: EX-OR GATE F = A  B
THE SHANNON EXPANSION GIVES
F = A [!B] + !A [B]
A
B
F
Copyright © 2004 by
Miguel A. Marin
Revised 2005-1-17
36