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EMC problems of DSOI device and circuits Binhong LI@IMECAS IHEP mini workshop 20160714 Topics All about DSOI: Compensation of TID; Dynamically adjustable circuit by VSOI2; EMC problems of the circuits; [email protected] 2 TID Compensation NMOS transistor TID experiment Semiconductor parameter analyzer SMU1 SMU2 Shield Vgate Vsource STI SMU3 SMU4 NMOS was biased under OFF state: VS=VG=0V, VD=1.8V, Vsub=0V Radiated with Co60 gamma rays with 50 Rad (Si) /s Vdrain STI BOX1 Middle-Si Vsoi2 BOX2 Vsub D-SOI [email protected] 3 TID Compensation NMOS transistor TID experiment DSOI-NMOS Vsoi2=0 V 1.00E+00 4.5E-04 4.0E-04 3.5E-04 3.0E-04 2.5E-04 2.0E-04 1.5E-04 1.0E-04 5.0E-05 0.0E+00 1.00E-02 0K 1.00E-04 0K 100K 1.00E-06 100K 1.00E-08 300K 1.00E-10 500K 300K 500K 1M 2M -2 -1 0 VG/V 1 ID/ A ID/ A DSOI-NMOS Vsoi2=0 V 1M 1.00E-12 2M 1.00E-14 2 -2 -1 1 2 DSOI-NMOS Vsoi2=-5 V DSOI-NMOS Vsoi2=-5 V 3.50E-04 1.00E-01 3.00E-04 1.00E-03 2.50E-04 0K 2.00E-04 100K 1.50E-04 300K 500K 1.00E-04 1M 5.00E-05 2M ID/ A ID/ A 0 VG/V 1.00E-05 0K 1.00E-07 100K 300K 1.00E-09 500K 1.00E-11 1M 1.00E-13 2M 1.00E-15 0.00E+00 -2 -1 0 VG/V 1 2 [email protected] -2 -1 0 VG/V 1 2 4 TID Compensation NMOS transistor TID experiment IV curve shifts negatively due to radiation induced holes accumulated in oxide. Since buried oxide are thicker than gate oxide, the main source of holes accumulation is in buried oxide. By applying a negative voltage, the leakage current and threshold voltage can be recovered to pre-irradiation level. For our case of study after 2M rad (Si), -7V on middle silicon layer is enough to compensate. [email protected] 5 Dynamically adjustable circuit Ring oscillator frequency adjustment We use a 101 stages ring oscillator to test VSOI2 impact on circuit performance. 101 stages Out Since Vth can be controlled by the back gate, with middle silicon layer, we can adjust Vthn and Vthp separately [email protected] 6 Dynamically adjustable circuit Ring oscillator frequency adjustment We use a 101 stages ring oscillator to test VSOI2 impact on circuit performance. f osc 1 2 N d τd is related to V , V th dd, and also Vsoi2 With Vsoi2 increasing, Vthn and Vthp will decrease. So by changing Vsoi2, we can adjust RO’s frequency and power consumption [email protected] 7 Dynamically adjustable circuit Ring oscillator frequency adjustment Best performance and highest power consumption: Vthn =+5V, Vthp =-5V [email protected] 8 Summary By introducing middle silicon layer: Compensation of TID with negative bias; Adjustment of circuit performance and power consumption; [email protected] 9 EMC of Circuit Electromagnetic compatibility of integrated circuit The increases of complexity and integration make EMC concern moving from system level to IC level. Aircraft Electronic equipment Coupling of external wave to cables Source of emission Noise propagation in supply lines Noise injection to the IC Printed circuit Failure Radiated mode Radar Integrated circuit [email protected] 10 EMC of DSOI circuit Conducted immunity (150kHz – 1GHz): Power Supply Susceptibility Criterion Monitoring Current meter RF Source Power Meter Pforw Signal Generator Prefl Output Coupler Amplifier DPI Capacitance Oscilloscope Decoupling network According to [IEC62132-4], we inject a sinusoidal wave with different frequency and amplitude. The RF disturbance is superimposed on the useful signal to simulate the noise injection in the real world . [email protected] 11 EMC of DSOI circuit DSOI Ring oscillator • We limit the maximum noise power at 30dBm. • The frequency of noise varied from 1MHz to 1GHz. • The failure criteria contains a static margin (±10% of power supply) and a dynamic margin( ± 10% of output 12 signal period), EMC of DSOI circuit DSOI Ring oscillator Vsoi2p VDD=1.8V Ring Oscillator Oscilloscope Vsoi2n [email protected] 13 EMC of DSOI circuit DSOI Ring oscillator Electromagnetic Immunity (EMI): VSOI2 and Substrate are vulnerable [email protected] 14 EMC of DSOI circuit DSOI Ring oscillator DPI on VDD(FD-SOI vs. DSOI) Injected Power[dBmW] 35 30 25 20 15 10 5 0 -5 1.00E+06 Power limit FDSOI(PIN28=0V) DSOI(SOI2N=SOI2P=0V) 1.00E+07 1.00E+08 1.00E+09 Freq[Hz] Compare FDSOI and DSOI, VDD’s EMI are same [email protected] 15 EMC of DSOI circuit DSOI Ring oscillator DPI on SUB (FDSOI & DSOI) Injected Power[dBmW] 35 30 25 20 15 10 5 0 -5 1.00E+06 Power limit FDSOI_SUB DSOI_SUB_SOI2=0V DSOI_SUB_SOI2=-5V 1.00E+07 1.00E+08 1.00E+09 Freq[Hz] Compare FDSOI and DSOI, substrate’s EMI: When Vsoi2=0V DSOI circuits has better EMI than FDSOI, due to SOI2 shielding. But when Vsoi2=-5V, the EMI level is worse than FDSOI [email protected] 16 EMC of DSOI circuit Problems: From previous study, that coupling capacitance between SOI1 and substrate are decrease: CFD>CDSOI(VSOI2=0V)>CDSOI(VSOI2=-1V); ?We test the impedance Network with VNA of device that we cant find different of capacitance for different VSOI2; More detail research in capacitance characterization are in progress; We propose that the EMI changing are due to circuit performance changing with back gate voltage. [email protected] 17 Summary Middle silicon layer works as an input, need to be characterized EMI performance, and useful EMC design rule need to be evaluated. Negative bias on Vsoi2 has impact on capacitance between SOI1 and substrate, which need to be checked; Back gate effect to circuit performance and EMI level need to be studied in detail. [email protected] 18 [email protected] 19