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Transcript
Reconfigurable Computing Assignment Feedback
John Morris
Chung-Ang University
The University of Auckland
‘Iolanthe’ at 13 knots on Cockburn Sound, Western Australia
Assignment Feedback
 A final grade for this assignment will be set when Stage B is
completed
result!
 There is no correlation between the amount of written
 When a report was already good,
how to make it ‘perfect’ !
Assignment Feedback
 Should have TWO architectures!
 One for a ‘standard’ implementation using full adder
components
 One using Altera’s (or Xilinx’ or …) fast carry logic
 ENTITY
 Formally describes the interface for this model
 Common
 Used by both implementations of the adder
GENERIC( n_bits : positive := 8 );
PORT( a, b : IN std_logic_vector;
c : IN std_logic;
sum: OUT std_logic_vector;
c_out : OUT std_logic );
 First ARCHITECTURE
GENERIC( n_bits : positive := 8 );
PORT( a, b : IN std_logic_vector;
c : IN std_logic;
sum: OUT std_logic_vector;
c_out : OUT std_logic );
SIGNAL c_int: std_logic_vector( n_bits DOWNTO 1 );
BEGIN
FOR J IN n_bits DOWNTO 1 GENERATE
fa: full_adder PORT MAP( … );
END GENERATE;
END ARCHITECTURE simple;
 Second ARCHITECTURE
GENERIC( n_bits : positive := 8 );
PORT( a, b : IN std_logic_vector;
c : IN std_logic;
sum: OUT std_logic_vector;
c_out : OUT std_logic );
BEGIN
rc: lpm_add_sub PORT MAP( … );
END ARCHITECTURE fast_carry ;
Configurations
 VHDL’93 allows you to write a configuration
CONFIGURATION std OF test_bench IS
FOR test_bench_architecture
END FOR;
END FOR;
Specifies the
END std;
architecture to be
used
 This capability is very important!
 It allows you to
 Check that the substitution of an improved architecture does
not alter the function (correctness) of a system
 Substitute different versions of basic modules in different
 fast adder when speed is important
 small adder when space is important
Configurations
 VHDL’93 allows you to write a configuration
CONFIGURATION std OF test_bench IS
FOR test_bench_architecture
END FOR;
END FOR;
Specifies the
END std;
architecture to be
used
 The full capabilities of a configuration allow
 Specification of an architecture for all instances of a model
 Specification of architectures for individual (labelled) instances
 An instantiation has a label
• Used to identify a component in simulation
 Substitution of equivalent entities
 ‘Equivalent’ = having compatible interfaces
Configurations (and Altera Limitations)
 VHDL’93 allows you to write a configuration
CONFIGURATION std OF test_bench IS
FOR test_bench_architecture
END FOR;
END FOR;
END std;
 Unfortunately, Altera’s software is, in some respects, primitive!!
 It does not support configuration
ie it does not allow you to specify which architecture to use
when instantiating a component
 It also insists that the ENTITY and ARCHITECTURE parts are in
the same file
 Preventing you from separating them!
 Good design separates interfaces and implementations!
• Separating the abstract from the concrete
 It probably has some good points though!
eg the synthesizer and simulator appear to be integrated well
Altera - Getting around the problem
1. Copy (link) everything into a different directory
2. Alter one of the architectures
3. Fine until you change something else!
 This is the reason that we want to have configuration
capabilities
•
So that we could work with two (or more) architectures
 Do NOT try renaming one of the entities!
 Unless you need to use BOTH architectures in the same
system!
 Altera only!
Abstract designs
 Copying and renaming defeats the idea that you can have
 the abstract part - a common interface

represented by an ENTITY
and
 concrete parts or different implementations

represented by different ARCHITECTURES
 Abstraction allows you to design at a high level
 Concentrate on the major functions of a system
… and leave low level details until later
 Example



A washing machine clearly needs a timer
Specify a generic timer
• By writing out its entity
Decide how to implement the timer later
Abstract designs
 Concept: designs have two parts
 the abstract part - a common interface and
 (several) concrete parts or implementations
 Designing at a high level: Example B
 At this point in the system, we need an adder
but we know several types of adder that we could use


Defer the decision as to what type of adder
until more is known about the full system
We may need
• a fast one,
• a compact one,
• a really small one (bit serial?)
 At an early stage in design, the only critical thing is that it adds
correctly!
 You might even use the multiple architectures capability to
test various implementations to find the best one
Assignment Summary
 The assignment specification called for a short report
‘summarizing what you have done so far’
 Some of you interpreted ‘short’ in an extreme way!!
 Ideally, your summary should have consisted of
1. a table with resource usage (# of logic blocks) and times for
2. some text commenting on this table
• Which configuration is best for each adder width?
•
•
Configuration with minimum delay should have been
highlighted, marked or mentioned
How much does the resource usage differ?
•
If the time advantage is small, you might prefer the smaller
structure!
 If there were anomalies or unexpected results
 They should have been explained
or at least (if you were unable to explain them)
 mentioned as unexpected
Assignment Summary
 Most of you omitted the ‘base’ configuration for an n-bit adder –
a simple n-bit ripple carry adder
 The 1  n configuration

Requires you to synthesize the ripple carry adder only!
 Actually important because


Fast carry logic  almost as fast as the CS adder
Only ~ half the resources (or space) required!
 One important design question

Use a simple ripple carry adder?
• Not too slow if the fast carry logic is used and
• Uses considerably less space
• Simple to implement (1 line of VHDL)
• Regular
or
 Try to implement a faster adder?
• Is it really needed?
Assignment - Details
 The following details are important and were commonly omitted
 Which software package was used?
 Altera’s MaxPlus, Quartus, Xilinx’s Webpack, etc
 Precise explanation of measurement unit for resources
 What does a slice mean?
 Even the term ‘logic block’ has a different sense for different
FPGAs
• Xilinx CLB has 2 FF’s, 9 inputs, 2 outputs
• Altera Logic Element has 1 FF, 4 inputs, 1 output
• Quicklogic has …
 So resource columns should be headed
• Altera Flex10K logic cells
or
ie be precise!
• Xilinx 4000 series CLBs
or
• ….
Delay Estimates and Accuracy
 Do not take the figures for delays reported by the tools as
perfectly accurate!!
 Delays are computed by summing the propagation delays
through every element on a signal’s path
These elements include
 Transmission gates (probably several types)
 Multiplexers
 Look up tables (LUTs)
 Flip flops
and sometimes
 Buffers
 Other logic gates
 Thus each reported path delay might be a sum of a 100 or more
elementary delays
Delay Estimates and Accuracy
 Delays
 For a given technology, the manufacturers estimate (by
measurement or calculation) the propagation delays of each
of these types of elements
tpd for a real circuit is a function of
 Temperature
 Supply Voltage
 Circuit dimensions
• Width of gates
• Length of channels, etc
 Even if the voltage and circuit dimensions are precisely
known, tpd values are only accurate for one temperature
 Circuits are usually rated for
 Commercial - 0oC – 70oC
 Industrial - 0oC - ~100oC
 Military, space – even wider range
Delay Estimates and Accuracy
 Delays
 Combined with manufacturing tolerances for circuit dimensions
 Track and gate widths
 Size of etched, implanted, … regions
 It is unlikely that a propagation delay for an individual circuit
element is accurate to < 100ps or 0.1ns over even a small T range
 If several hundred figures with errors of 0.1ns are added,
the error in the sum can be very large!
 A predicted delay is probably only good to 1ns
 … and could be much less accurate!
 Values in your report should reflect this!!
 Thus you should NOT copy the 55.828ns figure from the
synthesis report
 A realistic estimate is probably 56ns
 This is the value which should appear in your report
 55.8ns is tolerable, but probably completely unrealistic!
Delay Estimates and Accuracy
 Delays
 Selecting the best configuration
 If the synthesizer reports tpd = 23ns for configuration A and
tpd = 25ns for configuration B
 Is it safe to assume that A at 23ns is really faster?
 Almost certainly not!
 It may be …
but on a chip with slightly different track widths or running at a
slightly different T or Vdd
 Then the relative speeds may be different and B may be faster
 Again your report should reflect this
 It should not claim that a configuration differing from another by a
small margin is faster
 It should note the similarity
and
 look at other factors – such as size, regularity, …
Finally, English -
The hardest bit?
1. Technical Reports should be mainly written in the simple past tense
 Use the simple past tense in the active voice



Errors in measurement caused …
I/we implemented …
This result confirmed …
and in the passive voice



this effect was caused by …
the designs were implemented in …
our hypotheses were supported by these observations
2. Acronyms
 Explain them before you use them!



Several used ‘RCA’ for ripple-carry adder
Not generally accepted (even in this context) so must be spelt out
in full before use
VHDL and FPGA are OK (in this context) though!
Finally, English …
 The hardest bit?
1. Articles
 Even native speakers have difficulty explaining the rules!


I’ve tried to correct most errors
See if you can follow the patterns in my use
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