Download Compensation Made Easy: Advances in Designing with Digital

Utilizing a Digital PWM Controller to Monitor
the Health of a Power Supply
Mark Hagen
Systems Engineer
Digital Power Group
Texas Instruments
13 Oct 2008 CEME
1
A Digitally Controlled Power Supply
Power Stage
iL
Vin
L
RCS CCS
+
V
RLoad out
-
C2
+
-
Gate
drivers
C1
isense
divider network
Digital PWM Controller
+
u[n]
d[n]
digital
Compensator
ramp
counter
Vref
current
ADC
e[n]
error
ADC
verr
+
supervising
CPU
R1
Vref
DAC
vsense
EAmp
R2
serial
I/O
Reasons to go digital

Cp
to host
Programmable start/stop sequencing.
(Programmable start/stop delay and voltage ramp rates.)


Monitoring of system power and health metrics of the circuit.
Ease of adjusting the loop compensation.
 PC design tool does the math
 Can be tailored to the system late in the process since it is defined by serial bus
commands instead of by RC components.
13 Oct 2008 CEME
2
Start/Stop Sequence

PMBus Standard supports
sequencing commands




Digital controller operation




TON_DELAY
TON_RISE
TRACKING_MODE
Delay timed digitally.
Track desired ramp under
closed loop control by
slewing Vref setpoint DAC
ramp rate defined by
TON_RISE &
VOUT_COMMAND
rail#2 tracks
rail#3
Vout follows
digitally
defined ramp
May want separate loop
compensation for
start/stop ramps
Operating modes:  Start/stop ramp
13 Oct 2008 CEME
 Regulate
 Light load
3
Digitally Monitored Parameters


VIN (scaled input voltage)
IIN (requires dedicated current sense circuit)
 Shunt resistor: 4-terminal, low TCR type.
 Current sense amplifier:
INA13x, INA19x, INA21x, etc.
 "READ_IN" PMBus command

VOUT
 PMBus provides for a separate measure of Vout from the control loop voltage sense.

IOUT
 Either shunt sense circuit like Iin or Inductor DCR sense.
 Amplifier typically internal to controller or driver IC.

Temperature
 Ambient temperature measured at controller.
 Component temperature at each controlled power stage.

duty cycle
 "READ_DUTY_CYCLE" PMBus command
 Combined with Vin and Iout measure, forms a efficiency/circuit-health metric.
13 Oct 2008 CEME
4
Power Supply as a Feedback Controlled System
Power Stage
iL
Vin
L
RCS CCS
C2
+
-
Gate
drivers
C1
+
V
RLoad out
-
isense
divider network
Digital PWM Controller







d[n]
digital
Compensator
-
System consists of
+

u[n]
ramp
counter
Vref
current
ADC
e[n]
error
ADC
supervising
CPU
verr
+
R1
Vref
DAC
vsense
EAmp
Cp
R2
serial
I/O
Plant (Power stage)
to host
Sensor network (voltage divider)
Setpoint reference (Vref. Typically a DAC in digital PWM controllers.)
Error amplifier (fast ADC)
Compensator (digital filter)
Pulse width modulator (fast digital counter)
Delay elements (account for phase loss due to the time it takes to
calculate and apply the control effort)
13 Oct 2008 CEME
5
G ( s)
u[n]
G Delay 2
G Plant
Modeling the Loop
Vout
Vsense
G Div
Example with analog
summing junction
H(s)
KPWM
d[n]
G Delay 1

Open-loop gain

Closed-loop gain
where









13 Oct 2008 CEME
KAFE
KEADC
KNLR
GCLA
GDelay1
KPWM
GDelay2
GPlant
GDiv
=
=
=
=
=
=
=
=
=
G CLA
KNLR
e[n]
K EADC
K AFE
Ve
+
Vr K
DAC
ref
v Sense
 H s   G s 
v error
v Sense
H s   G s 

ref
1  H s   G s 
analog front end gain in V/V
error ADC gain in LSB/volt
Nonlinear boost gain
Control-law accelerator (digital compensator) gain
Total sampling and CLA computational delay
PWM gain in duty/LSB
On-time and any delay to multiple power stages driving Vout
Transfer function from d to Vout of the power stage
Divider network transfer function in V/V
6
Loop Stability Criteria
G(s)
u[n]
G Delay 2
G Plant
Vout
Vsense
G Div
H(s)
KPWM



d[n]
G Delay 1
G CLA
KNLR
e[n]
K EADC
K AFE
Ve
+
Vr K
DAC
ref
The frequency response is
derived from the average model of
the power stage
Open-loop gain = H(f)•G(f)
Stability criteria
(same as analog control)
 Phase margin: Phase distance
from 180º at the frequency where
gain = 0 dB  want 45º to 65º
 Gain margin: Gain at frequency
where phase = 180º  want > 6 dB
13 Oct 2008 CEME
GM
PM
7
G(s)
Power-Stage Model
u[n]
G Delay 2
G Plant
Vout
Vsense
G Div
H(s)
KPWM

G Delay 1
G CLA
KNLR
e[n]
K EADC
Ve
K AFE
+
Vr K
DAC
ref
A (discrete) time model is needed
to get accurate estimates of transient
performance and stability


Define continuous-time
state equations
(states are iL and vC)
L
+
vout  Cq x  Dq Vg
–
Convert to discrete-time
difference equations
RL
Vg
x  A q x  Bq Vg and
ˆ  1] and
ˆ  x[n
ˆ  1]  d[n
x[n]
ˆ
vˆout [n]  Cx[n]

d[n]
iL
R esr
R
+
vc
–
c(t)
DPWM
G(z)
C
Hvo
H=1
eADC
vref
Design software such as Spice or the Fusion Digital Designer integrates
difference equations for each interval to simulate the power stage
13 Oct 2008 CEME
8
Define the Plant (power stage)
Resulting transfer function for the plant

Enter component parameter values



Gain elements Vin and duty (from Vout)
Series elements L, DCR, RDS(on)
Parallel elements C, ESR, ESL
 Lump like components together
13 Oct 2008 CEME
9
G(s)
u[n]
Divider-Network Model
G Delay 2
G Plant
Vout
Vsense
G Div
H(s)
KPWM


G CLA
K NLR
e[n]
K EADC
KAFE
Ve
+
Vr K
DAC
ref
GDiv(f )
Vout
Set RC lowpass corner frequency at 35% to 45%
of error-ADC sample frequency.
Continuous model
R2
R1Czs  1
K Div 
G Div  s   K Div
R1  R2
K Div R1 Cz  Cp s  1


G Delay 1
Divider scales Vout to error-ADC
input range.
With Cp, forms anti-alias low-pass
for error-ADC.


d[n]
R1
Cz
Vsense
R2
Cp

Digital power-design software creates a discrete model from
continuous circuit description.


Apply discrete transform to continuous model
evaluated at each error-ADC sample time
13 Oct 2008 CEME
10
Define the divider network

Set the divider gain (attenuation)

Set nominal Vout at ~75% of
error-ADC dynamic range
 headroom for margining,
 over-voltage detection.

Communicated to device by
PMBus commands
 VOUT_SCALE_LOOP
 VOUT_SCALE_MONITOR

Define capacitors to set pole
(or zero)

Good idea to roll off high frequency
at 70% to 90% of Nyquist
frequency. (35% tp 45% of
switching frequency.)
13 Oct 2008 CEME
11
G(s)
Model the Compensator
u[n]
G Delay 2
G Plant
Vout
Vsense
G Div
H(s)

POL applications require
2nd-order compensation




d[n]
G Delay 1
G CLA
K NLR
e[n]
Two zeros and a pole at zero Hz
This is a classical PID controller (Proportional, Integral, Derivative)
Discrete form:
duty(z) b z 2  b z  b
G CLA  z  
e(z)

01
11
z 1
21
K EADC
KAFE
Ve
+
Vr K
DAC
2 zeros
pole at origin
Additional poles improve effect of error-voltage quantization by smoothing the
2 zeros
CLA output:
duty(z) b01z 2  b11z  b21
G CLA  z  

KPWM
e(z)

z 2  a11z  a 21
2 poles
To model in discrete time, the design software evaluates the compensator
difference equation:
d(z) 
b01  b11z 1  b21z 2
1  a11z
1
 a 21z
2
e(z)
d  n  b01e n  b11e n  1  b21e n  2  a11d n 1  a 21d n  2
13 Oct 2008 CEME
12
ref
Types of Compensator Realizations
Numerator

2nd-order table look-up (UCD9112)
d[n]
d z
K 0 z2  K1z  K 2

e z
z 1
K0N
...
K1N
...
K2N
...
K01
K00
K11
K10
K21
K20
z –1
e[n]

z –1
d[n – 1]
z –1
e[n – 2]
Direct-form digital filter (UCD9240)
d z
e z

Numerator
b0 z 2  b1z  b2
d[n]
a1
PID-form digital filter (conceptual)
d z
e z
 KP  KI

Denominator
z 2  a1z  a 2
z –1
e[n]

Denominator
z
z 1
 KD
z 1
z
KP  KI  KD  z
2
b0
z –1
z –1
e[n – 1]
d[n – 1]
z –1
a2
d[n – 2]
e[n – 2] b2
b1
KP
dP[n]
e[n]
Kl
  K P 1     K I   2K D  z   K P   K D 
dl[n]
KD
z 2  1    z  
d[n]
Proportional
Integral
z –1
dD[n]
z –1
Derivative
e[n – 1]
13 Oct 2008 CEME

z –1
13
G(s)
u[n]
Choosing the
Compensation

G Delay 2
G Plant
Vout
Vsense
G Div
H(s)
KPWM
d[n]
G Delay 1
G CLA
K NLR
e[n]
K EADC
KAFE
Ve
+
Vr K
DAC
ref
Choose continuous time parameters to shape the Bode-plot loop gain
to achieve desired phase and gain margin



DC gain KDC
Zeros ωz1 ωz2
Poles: origin, ωp2
 s
 s

s2
s

1

1

1



2
d s


 or K r r Q
 K DC  z1  z2
DC
e s
 s

s2
s
s
 1
 p2

p2



Then transform the continuous-time polynomial in s to a discrete-time polynomial
in z. This is typically done by the design software
 TI Fusion Digital Power Designer performs the transformation by:
1.
Apply the bilinear transformation by
substituting s into the above polynomial:
2.
Then solve for discrete-time
polynomial coefficients:
13 Oct 2008 CEME
d z
e z

 z 1 
s  2Fs  

 z 1
b0 z 2  b1z  b2
z 2  a1z  a 2
14
Define the compensation

Center zeros on 2nd order plant pole
 Spreading the zeros either side of the plant pole
improves the output impedance of the system
 In above example I reduced the 2nd order zero
frequency a bit to buy some phase margin.

Define the compensator poles
 Integrator function defines 1st pole at the origin.
 Set 2nd pole above 0 dB cross-over to increase
gain margin.
13 Oct 2008 CEME
15
Effect of locating zeros
perfect
cancellation

Perfectly canceling plant 2nd order pole does not
result is lowest possible closed loop output
impedance
 Results in increased load transient settle time.
13 Oct 2008 CEME
16
Effect of locating zeros, cont.
zeros
spread

Spreading zeros minimizes output impedance
 Lower output impedance improves load transient
settle time.
13 Oct 2008 CEME
17
Adding Nonlinear gain to the compensation

Strictly linear compensation


flat gain
Transient response
13 Oct 2008 CEME
18
Adding Nonlinear gain to the compensation

Reduce gain for quiescent cond. where verror near 0.



gain high for transient,
gain low at around zero.
Improves steady state voltage, peak error reduced.
13 Oct 2008 CEME
19
Nonlinear Boost

Scope traces with and without nonlinear boost
1.3
1.2
Uniform gain of 1X
Gain boosted 3X for
|verr | > 5
Gain boosted 4X for
|verr | > 5
130.5 mV
108.1 mV
5.2 mV
5.0 mV
88.4 mV
5.0 mV
no boost
1.15
Vout (V)
Parameter
Peak-toPeak Output
Excursion
RMS Error
During
Quiescent
Operation
rms
pk-pk
1.25
1.1
3X boost
1.05
1
4X boost
0.95
0.9
load current
0.85
0.8
0
200
400
600
800
1000
Time (µs)
13 Oct 2008 CEME
20
System Identification (Transfer Function)

Digital PWM controllers offer the opportunity to identify the system
dynamics (System-ID) by measuring the transfer function of the
system in situ (in place).
 No external test equipment
 No auxiliary circuits or probes

To do this we need to:




From this response, calculate the open loop gain


Generate an excitation signal
Inject that signal at a summing junction
Capture the response of the system to the excitation
From the open loop gain determine key performance metrics of
bandwidth, gain margin and phase margin.
For a digitally controlled system the logical location to make the
measurement is just before or just after the digital compensator.
13 Oct 2008 CEME
21
Possible Measurement Locations
Given the following basic system equations:
u'
G(s)
power stage
y  Gu
u  d  x2
y'
d  Hc
c  e  x1
digital controller
PWM
ADC
u
y
x2
H(z)
d
c
digital
compensator



ery
x1
e
-
The closed loop response at each node is:
r
Inject a sinewave at r, x1 or x2
Measure response at node
y, e, c, d or u
Solve for GH
13 Oct 2008 CEME
GH
GH
G
r
x1 
x2
1  GH
1  GH
1  GH
H
H
1
u
r
x1 
x2
1  GH
1  GH
1  GH
H
H
GH
d
r
x1 
x2
1  GH
1  GH
1  GH
1
1
G
c
r
x1 
x2
1  GH
1  GH
1  GH
1
GH
G
e
r
x1 
x2
1  GH
1  GH
1  GH
y
22
Calculate the open-loop gain from the closedloop response
Solution of G(f)H(f) for various injection and measurement nodes:
Loop gain
G(f)H(f)
r
inject
at:
x1
x2


Measure response at:
y
y
ry
y
x1  y
Hy
x2  Hy
u
d
c
e
H
r
1
u
H
r
1
d
r
1
c
r
1
e
H
x1
1
u
H
x1
1
d
x1
1
c
 x1
1
e
x2
1
u
d
x2  d
 Hc
x 2  Hc
e
x2  e
Note that the formula for calculating open loop gain contains the
compensator gain H(f) if the system is excited before the
compensator and measured after, or vice-a-versa.
This is not a big problem since a digital compensator is completely
deterministic. Its frequency response can be calculated as:
(for a 2nd order compensator)

b0 z 2  b1 z  b2
 H  f meas   2
Ts is the compensator sample period

z  a1 z  a 2
 z  exp  j 2πf meas Ts   cos2πf meas Ts   j sin 2πf meas Ts 
13 Oct 2008 CEME
23
Type of Excitation to use for System-ID
# of frequencies per measurement
Needed dynamic range
Needed memory (RAM)
Max meas. interval
Measurement signal to noise
sinewave
white noise
1
narrow (few bits)
2 words
1 M samples*
high
N/2
wide (many bits)
1k words or more
limited by available memory
medium
Accurate
Fast
* 12 bit samples, 32 bit accumulator
13 Oct 2008 CEME
24
Sinewave Generation

Use table look-up technique


Digital controllers such as the UCD9240 or TMS320C2801, have a
build-in sinewave table in ROM.
For each sample, step through the table with a step size defined as
step  N tableLen
Fmeas
Fsamplerate
then generate the excitation signal as:
phase = phase + step;
index = phase >> PHASE2INDEX;
sine_signal = sine_table(index);


// use MSB bits for sine table index
// lookup excitation signal value in table
When the end of the table is reached, wrap to the beginning of the table
by subtracting the table length from the index.
By maintaining the fractional part of the table index and rounding to
determine the table entry, very high frequency resolution can be
obtained.
13 Oct 2008 CEME
25
Response Measurement

The definition of a Discrete Fourier Transform (DFT) is:
N 1
K k   v n e  j 2πnk / N
n0
 
k 
k 

  v n    cos 2 n   j sin  2 n  
N 
N 

n 0
 
This says that we can calculate the real and imaginary magnitudes of the kth
harmonic of a signal by multiplying that signal by a sine and cosine sequence
and summing.
Since we've already generated a sinewave to inject into the loop as the
excitation signal, the response measurement is simply:
N 1


cosSum += d*Xcos;
sinSum -= d*Xsin;
//
//
//
//
Accumulate cosine sum
for measurement node d
Accumulate sine sum
for measurement node d
(Note that since a sine is shifted by π/2 from a cosine, the cosine sequence is easily generated by
adding an offset to the sine table index of 1/4 the table length.)
13 Oct 2008 CEME
26
Example Calculation of G(f)H(f)
Inject at r measure at d
u'
G(s)
power stage
y'
digital controller
PWM
ADC
y
d
H(z)
e
digital
compensator
r
x
CPU
xcos
z-1
cosSum
xsin
z-1
sinSum
serial bus
to host
• Return cosSum and sinSum for each injected excitation frequency.
Calculate open loop gain as follows:
N
Gainopenloop  G  f H  f 
X cos
r
2
 H  f   1  hr  f   jhi  f 
1
d
cosSum  j  sinSum
• Where Xcos is the base to peak amplitude of the excitation and N is the # samples the
response is summed over.
• Then plot magnitude and phase of G(f)H(f) to determine phase margin, gain margin and
bandwidth.
13 Oct 2008 CEME
27
Practical Auto-ID measurements

Windowing

The definition for the DFT produces the response just at harmonic
frequencies. These frequencies produce an integer number of cycles
in the measurement interval. At other frequencies you need to do
something to reduce "leakage".
1.
2.

Window the measurement data. A raised cosine or triangle window are popular
options.
Modify the measurement interval so that an integer number of cycles are measured.
(What we implemented.)
Settling

13 Oct 2008 CEME
We want just the forced response, so the controller needs to wait
some number of samples for the natural response to decay.
28
Power Stage Transfer Function

The compensation in a digital
PWM controller is deterministic
 No gain or offset error
 Poles and zeros concisely defined.



So divide measured loop gain
by known compensator TF.
Then use this measured
response instead of modeled
plant to choose compensation.
Note that the measured TF is
more damped than the modeled TF.
 Measurement takes into account losses not included in plant model.
 Losses show up as effective increase in resistance, which adds
damping.
13 Oct 2008 CEME
29
Monitor power system health

DC/low frequency measurements
 Vin, Iin
 Iout, Vout
 Temperature of each power stage

AC measurements
 Automatic Identification of the system transfer function
 Use linear (average) model of the plant to estimate component values

Look for a change in monitored parameter
 Use statistical process control techniques to decide if it has changed.
13 Oct 2008 CEME
30
Statistical Process Control

Many techniques



Mean & Range charts
Mean & Sigma charts
Key concepts

Average a set (sample) of measurements.
 This guarantees normally distributed measurement error based on central limit theorem.

Compare sample average to a confidence interval to decide if the mean
has changed.
13 Oct 2008 CEME
31
Confidence Interval


Givenk  z  where σ is the expected population standard deviation,
2 n
n is the sample size and z is the probability that the sample mean is
2
within the confidence interval. Then the interval is   k,   k 
Example
During product development μ, σ of
open loop bandwidth were found to be to be
μ = 55.0 kHz
σ = 0.750 kHz.
 Last 4 measurements of BW using Auto-ID
are 56, 58, 53, 55 kHz.x = 55.5 kHz
 z
for 90% confidence is 1.96
 2So confidence interval is
[ 54.2650, 55.7350]
 Therefore we can say with 95% confidence
that the mean has not changed.

13 Oct 2008 CEME
double sided
sigma (zα/2) probability (%)
event ppm
1.00
68.26
317k
1.65
90.00
100k
1.96
95.00
50k
2.00
95.44
45.6k
2.58
99.00
10k
3.00
99.73
2.7k
3.09
99.98
2.0k
3.29
99.99
1.0k
3.48
500
3.89
100
4.00
63.6
5.00
0.6
6.00
2 ppb
32
"Health" metrics

Transfer function based measures

open loop bandwidth, phase margin, gain margin



Power stage Q



Compare to expected values
Don't have to measure full frequency range. One freq may be sufficient.
Lossy components cause Q to be reduced.
Input power vs. output power

efficiency =v IN i IN

Average duty cycle (see next slide).
vOUT  i L
Temperature

Power stage balance


UCD9240 allows closed loop control of temperature balance
Power stage vs ambient (measured at controller IC.)
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33
Average Duty Cycle

vOUT 
Then
D VIN
FET
switchs
D VIN  VOUT
iL
Monitor RS and compare to
SPC control limits
L1
CC
RS
V
 Rs i L
D  OUT
VIN
RS 

RLoad  RS
RLOAD
RC
40
39.5
duty in %

Capture duty cycle at output of digital compensator.
At DC
RLoad
RSW(LOSS) RDS(ON) RDCR
39
38.5
38
37.5
25
series resistance in mOhms

0
5
10
15
20
inductor current in Amps
20
15
10
5
25
13 Oct 2008 CEME
30
35
duty in %
40
45
34
Conclusion

Digital PWM Controllers now offer:


Programmable start/stop sequencing.
Ability to Monitor power and health metrics.
 Power stage voltages and currents
 Temperature
 Duty cycle


Complete control of compensation gain, zeros and poles.
In situ measurement of system dynamics.
 Enables measurement at other than the lab bench.
(For instance, on factory floor or installed in end equipment.)

Use monitored parameters to assist in predicting failure
 Apply statistical confidence limits to decide if the parameter has changed.
 If a mean shift is indicated, issue a warning to the host system.

Design tools for Digital Power:




Pull together sequencing, monitoring and control configuration in one place.
Allow sophisticated, accurate frequency and time simulation of the target system.
Automatic System Identification of the power supply dynamics.
Automatic tuning of the loop compensation.
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35