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REASON WP8 Appendix 1 Workpackage WP8. Technologies and contents for distance training DELIVERABLE D8.1.part1 Specification of Java-applets for teaching Test and Design for Test of digital systems Partners: CR3-TTU, CR8-TUI The rapid developments in the areas of deep-submicron electron technology and design automation tools are enabling engineers to design larger and more complex integrated circuits. This progress is driving engineers towards design methodologies called System-onChip (SoC). The more complex are getting electronics systems the more important are getting the problems of test and design for testability, as the expenses of verification and testing are becoming the major components of the design and manufacturing costs of new electronic products. The design and test cannot be seen any more as separate engineering issues. Entering into the SOC era means that test must become an integral part of the VLSI and system design courses. The next generation of engineers involved with VLSI technology should be made aware of the importance of test, and trained in test technology to enable them to produce high quality and defect-free products. Teaching the basics of Digital Test and Testable Design means teaching a lot of complex connections that have to be explained, at first, one by one and then in their dynamic interactions. Traditional teaching methods using desk, overhead or “PowerPoint™“ presentations can explain those connections only partially. After the lecture the dynamic part of the lecture, the connections created by the teacher between different subjects, gets lost. The static part of the whole scenario that students find in their notes, lecture handouts or books does not help well when they try to solve some given problems by using the learned methods. They can do it just as good as they can recall the lecture. An enhancement of this situation can be reached, if the whole material, containing all scenes of the dynamic process can be easily accessed via the Internet and be well illustrative. The core of the teaching concept presented here is Java-applets (interactive modules) running on any standard browser like Netscape and Internet Explorer connected to the Internet. We call this type of applets - “Living Pictures”. The applets simulate tricky, quite complicated situations of the learning subject in a graphical form on the computer. The graphic is selfexplanatory and provides interaction possibilities. By using these possibilities the students can generate examples that are interesting enough to encourage their own experiments but not too complicated for learning. The teacher can use these applets during lectures or during the exam giving some tasks to students. The students can use the same applet while training. 1. TTU-JALLTD – Java Applet on Logic Level Test Generation & Diagnosis Tool acronym: TTU-JALLTD Tool destination: The goal of the tool is to illustrate the basics of testing of digital systems, test generation, fault simulation and fault diagnosis on the gate level. Tool description: The applet allows the test vector insertion by hands as well as automatic pseudo-random test generation by LFSR. The first mode aims at illustration of different test generation approaches manually. In this mode, the needed signal values for fault activation or fault propagation can be inserted directly at the connections on the circuit schematics making the process of test generation very illustrative. The LFSR mode is used for emulating different BIST architectures like BILBO and CSTP. In the fault simulation mode, a fault table is generated for all the created test vectors. By selecting a single vector all the faults detected by this vector will be highlighted by colors on the circuit schematics. The applet allows insertion of stuck-at faults into the circuit. There are two different fault diagnosis modes possible. In the guided probing mode the fault diagnosis procedure can be simulated by clicking on the wires on the circuit schematics and “measuring” the “real” signal levels in the “defective” circuit. For learning the combinational diagnosis strategy, a single vector or a subset of vectors can be selected in the fault table (imitating test experiments). The applet simulates these vectors and shows the results of diagnosis displaying the subset of suspected faults. The main didactic point in learning diagnostic strategies is in trying to localize the faults by as few test vectors (in the combinational approach) or by as few measurements (in the case of sequential approach) as possible. In this task a competition between students can be carried out which makes the “play” with the applet even more exciting. Tool platform: OS platforms: virtually any platform that supports Java 1 and Java 2 runtime environment Programming language: Java 1 and Java 2 using Java Development Kit and Java Runtime Environment by Sun Microsystems and the Java Development Tools (www.eclipse.org) within the Eclipse Platform Expected number of lines of source code – 15000 lines Estimated efforts: 18,75 person-months 2. TTU-JARTDT – Java Applet on Register Transfer Level Design, Test, and Design for Test Tool acronym: TTU-JARTDT Tool destination: The goal of the applet is to illustrate quite a large number of different problems of RT-level design and test related to each other. The selection of illustrated topics is the following: RT level design, simulation, and validation of a digital device consisting of datapath and control part (microprogram), investigation of tradeoffs between speed of the system & HW cost, gate-level deterministic test generation and functional testing, fault simulation, design for testability, logic BIST, circular BIST, functional BIST, etc. Tool description: The applet consists of several modules. The main part of the applet is the schematic view panel that provides the schematic representation of the target system reflecting the internal structure of the datapath. The datapath is well reconfigurable. Different functions can be selected in each functional unit. The control part of the design should be specified in the microprogram table. This can be done in a relaxed way giving the possibility of designing many different devices using the same basic datapath. Even the same device can be designed in many different ways using less or more of hardware resources. This may result in a lower or higher speed of the system, which can also be measured. When the device is ready it can be simulated and validated. The results of simulation are stored in a special table as well as shown graphically in the schematic view panel. There is also a special table for RT-level fault simulation. This table provides fault coverage for each functional unit separately as well as for the datapath as a whole. There are several modes for test generation. The functional testing mode uses the “normal” operands and simulates the device during normal working mode. Another mode, the deterministic test mode, allows manual test generation on the gate level for each of the functional units used in the device separately. A gate-level schematic of those units is provided. This mode need a set of special test microprograms, which are generated on the fly and can be modified by the user. There are different BIST modes selected for this applet. Logic BIST and Circular BIST are aimed at illustration of BILBO and CSTP approaches on the RT level. Functional BIST is a special mode similar to Functional test where it is possible to use a number of signature analyzers to improve the design testability. The main advantage of the applet is the fact that it gives a unique possibility to teach all the mentioned problems in a consecutive iterative way using the same teaching system. Tool platform: OS platforms: virtually any platform that supports Java 1 and Java 2 runtime environment Programming language: Java 1 and Java 2 using Java Development Kit and Java Runtime Environment by Sun Microsystems and the Java Development Tools (www.eclipse.org) Expected number of lines of source code – 20000 lines Estimated efforts: 25 person-months within the Eclipse Platform 3. TTU-JABSBT – Java Applet on Boundary Scan Standard: Board Test Tool acronym: TTU-JABSBT Tool destination: The goal of the applet is to illustrate the IEEE 1149.1 standard, the Boundary Scan Test. Tool description: The applet allows several working modes: design/editing of the Boundary Scan (BS) structures inside the target chip using the BSDL language; design/description of the target board consisting of several chips; simulation of work of the TAP controller, scan register and other BS registers; insertion and diagnosis of interconnection faults. In the board description mode, each chip on the board can be defined and redefined. The applet reads the description of BS structures using BSDL format and the description of the chip’s internal logic in SSBDD format. Such BSDL descriptions are widely available for free via Internet. This makes the work with the applet easier and more exciting, since the student can visualize the work of many well known chips with BS available in the market. The latter may also be interesting for test engineers. The simulation of the chip’s work can be done in two modes. The first one, the TAP controller mode, provides a very detailed illustration of operation of BS registers and the TAP controller. This mode is intended for the beginners and for teachers, helping to understand all the needed basics. Another mode, the command mode, can be used for faster simulation with different predefined input data and for the fault diagnosis. There is a possibility of random or specific fault insertion. The operation of the faulty device can be then simulated and the fault can be diagnosed. Tool platform: OS platforms: virtually any platform that supports Java 1 and Java 2 runtime environment Programming language: Java 1 and Java 2 using Java Development Kit and Java Runtime Environment by Sun Microsystems and the Java Development Tools (www.eclipse.org) Expected number of lines of source code – 7000 lines Estimated efforts: 8,75 person-months within the Eclipse Platform