Download Answer all questions PART A – (10*2=20marks) 1. What are the

Answer all questions
PART A – (10*2=20marks)
1. What are the advantages of SOI CMOS process?
2. Distinguish electrically alterable and non-electrically alterable ROM.
3. Compare nMOS and pMOS.
4. Compare enhancement and depletion mode devices.
5. What is meant by continuous assignment statement in Verilog HDL?
6. What is a task in Verilog?
7. Give the application of PLA.
8. What is meant by a transmission gate?
9. What is the aim of adhoc test techniques?
10. Distinguish functionality test and manufacturing test.
PART B – (5*16=80 marks)
13. (a) (i) Give a verilog structural gate level description of a bit comparator.
(ii) Give a brief account of timing control and delay in verilog.
OR
(b) (i) Give a verilog structural gate level description of a ripple carry adder.
(ii) Write a brief note on the conditional statements available in verilog.
14. (a) (i) Compare the different types of ASICs.
(ii) Discuss the operation of a CMOS latch.
OR
(b) Explain the ASIC design flow with a neat diagram. Enumerate clearly the different
steps involved.
UNIT – I
MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY
PART A (2 Marks)
1. What is meant by “Epitaxy”?
2. What is isolation?
3. What is the special feature of Twin-Tub process?
4. What are the various processes used in SOI?
5. What is siliside?
6. What is LDD?
7. What is LOCOS?
8. Give the advantages of IC
9. What is Depletion mode Device?
10. Name the four generations of Integration Circuits?
11. Name the types of Integrated Circuits
12. Give the basic process for IC fabrication.
13. What are the various steps in Silicon wafer preparation?
14. What are the advantages of Silicon-on-Insulator process?
15. What are the advantages of CMOS process?
16. What are the different MOS layers?
17. Why NMOS technology is preferred more than PMOS technology?
18. What are the different operating regions an MOS transistor?
19. What are four generations of Integration Circuits?
20. Give the advantages of IC?
21. Give the variety of Integrated Circuits?
22. Give the basic process for IC fabrication
23. What are the various Silicon wafer Preparation?
24. Different types of oxidation?
25. What is the transistors CMOS technology provides?
26. What are the different layers in MOS transistors?
27. What is Enhancement mode transistor?.
28. What is Depletion mode Device?
29. When the channel is said to be pinched –off?
30. Give the different types of CMOS process?
31. What are the steps involved in twin-tub process?
32. What are the advantages of Silicon-on-Insulator process?
33. What is BiCMOS Technology?
34. What are the basic processing steps involved in BiCMOS process?
35. What are the advantages of CMOS process?
36. What are the advantages of CMOS process?
37. What is the fundamental goal in Device modeling?
PART-B (16 Marks)
1. 1.a) Explain the operation of NMOS Enhancement transistor (8)
2. b) Derive the Threshold voltage for NMOS Enhancement transistor (8)
3. a) Explain about the body effect of MOS transistors. (6)
4. b) Derive the design equations for MOS devices (4)
5. c) What do you mean by channel length modulation? Explain. (6)
6. 3. a) Explain the second order effects with their equations. (10)
7. b) Explain small signal AC characteristics with its design equations. (6)
8. 4. Explain the fabrication of PMOS transistor and its substrate fabrication
9. Process. (16)
10. 5. Explain different fabrication process of CMOS transistor (16)
11. Derive the CMOS inverter DC characteristics and obtain the relationship for
output
12. voltage at different region in the transfer characteristics.
13. Explain with neat diagrams the various CMOS fabrication technology
14. Explain the latch up prevention techniques.
15. Explain the operation of PMOS Enhancement transistor
16. Explain the threshold voltage equation
17. Explain the silicon semiconductor fabrication process.
18. (i) Draw and explain the n-well process.
(ii) Explain the twin tub process with a neat diagram.
19. (i) Discuss the origin of latch up problems in CMOS circuits with necessary
diagrams. Explain the remedial measures.
(ii) Draw and explain briefly the n-well CMOS design rules.
20.i) Derive expressions for the drain to source current in the nonsaturated and
saturated
regions of operation of an nMOS transistor.
(ii) Define and derive the transconductance of nMOS transistor.
21.Discuss the small signal model of an nMOS transistor.
& Explain the CMOS inverter DC characteristics
UNIT-II
INVERTERS AND LOGIC GATES
PART- A (2 Marks)
1. Define noise margin.
2. Define Rise Time.
3. What is body effect?
4. What is low noise margin?
5. What is stick diagram?
6. What are Lambda (O) - based design rules?
7. Define a super buffer.
8. Give the CMOS inverter DC transfer characteristics and operating regions
9. Give the various color coding used in stick diagram?
10. Define Delay time
11. Give the different symbols for transmission gate.
12. Compare between CMOS and bipolar technologies.
13. What are the static properties of complementary CMOS Gates?
14. Draw the circuit of a nMOS inverter
15. Draw the circuit of a CMOS inverter
16. Define Short Channel devices?
17. What is pull down device?
18. What is pull up device?
19. Why NMOS technology is preferred more than PMOS technology?
20. What are the different operating regions foe an MOS transistor?
21. What are the different MOS layers?
22. What is Stick Diagram?
23. What are the uses of Stick diagram?
24. Give the various color coding used in stick diagram?
25. Compare between CMOS and bipolar technologies.
26. Define Threshold voltage in CMOS?
27. What is Body effect?
28. What is Channel-length modulation?
29. What is Latch – up?
30. Give the basic inverter circuit.
31. Give the CMOS inverter DC transfer characteristics and operating regions
32. Define Rise time
33. Define Fall time
34. Define Delay time
PART-B (16 Marks)
1. List out the layout design rule. Draw the physical layout for one basic gate and
two universal gates. (16)
2. Explain the complimentary CMOS inverter DC characteristics. (16)
3. Write short notes on:
4. Briefly discuss about the following:
5. a. Explain the concept of static and dynamic CMOS design (8)
b. Explain the construction and operation of transmission gates (8)
UNIT III
CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION
PART-A (2 Marks)
1. What are the issues to be considered for circuit characterization and
performance estimation?
2. Give the formula for resistance of a uniform slab of conducting material.
3. What are the factors to be considered for calculating total load capacitance on
the output of a CMOS gate?
4. What are the components of Power dissipation?
5. What is meant by path electrical effort?
6. Define crosstalk.
7. Define scaling.
8. What are the factors to be considered for transistor scaling?
9. Define constant voltage scaling.
10. What are the sources to be considered for design margin?
PART-B (16 Marks)
1. Explain in detail about the following:
a) Resistance estimation (8)
b) Inductance estimation (8)
2. Explain about routing capacitance with neat diagram. (16)
3. With neat diagram explain about power dissipation. (16)
4. Briefly explain about the following:
a) CMOS transistor sizing (8)
b) Design margining (8)
5. Explain about scaling of MOS transistor dimensions and charge sharing. (16)
UNIT –IV
VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL
PHYSICAL DESIGN
PART-A (2 Marks)
1. Write the difference between encoder and priority encoder.
2. Draw the CMOS implementation of 4-to-1 MUX using transmission gates.
3. Give the verilog coding for 4-bit magnitude comparator.
4. Draw the wheel floor plan
5. What is meant by clock distribution?
6. Design a circuit for finding the 9's compliment of a BCD number using 4-bit
7. binary adder and some external logic gates
8. What is physical verification?
9. Mention the levels at which testing of a chip can be done
10. What are the approaches in design for testability?
11. What is known as boundary scan register?
12. Design a set of CMOS gates to implement the sum function.
13. Give some of the important CAD tools.
14. What is Verilog?
15. What are the various modeling used in Verilog?
16. What is the structural gate-level modeling?
17. What is Switch-level modeling?
18. What are identifiers?
19. What are the value sets in Verilog?
20. What are the types of gate arrays in ASIC?
21. Give the classifications of timing control?
22. Give the different arithmetic operators?
23. Give the different bitwise operators.
24. What are gate primitives?
25. Give the two blocks in behavioral modeling.
26. What are the types of conditional statements?
27. Name the types of ports in Verilog
28. What are the types of procedural assignments?
29. Give the different symbols for transmission gate
30. What are the categories of testing?
31. Write notes on functionality tests?
32. Write notes on manufacturing tests?
33. Mention the defects that occur in a chip?
34. Give some circuit maladies to overcome the defects?
35. What are the tests for I/O integrity?
36. What is meant by fault models?
37. Give some examples of fault models?
38. What is stuck – at fault?
39. What is meant by observability?
40. What is meant by controllability?
41. What is known as percentage-fault coverage?
42. What is fault grading?
43. Mention the ideas to increase the speed of fault simulation?
44. What is fault sampling?
45. What are the approaches in design for testability?
46. Mention the common techniques involved in ad hoc testing?
47. What are the scan-based test techniques?
48. The circuit is level-sensitive.
49. What are the self-test techniques?
50. What is known as BILBO?
51. What is known as IDDQ testing?
52. What are the applications of chip level test techniques?
53. What is boundary scan?
54. What is the test access port?
55. What are the contents of the test architecture?
56. What is the TAP controller?
57. What is known as test data register?
PART-B (16 Marks)
1. Give the design procedure for 8 bit carry look ahead adder. (16)
2. Design a multiplier for the given sequence: (16)
3. Draw the basic physical design for the inverter AND, OR and half-adder. (16)
4. Explain in detail about manufacturing of test principles. (16)
5. Explain the concept of clock distribution and power distribution. (16)
6. Explain the Transmission gate and the tristate inverter briefly.
7. Explain about the various non ideal conditions in MOS device model.
8. Explain the design hierarchies.
9. Explain the concept involved in Timing control in VERILOG.
10. Explain with neat diagrams the Multiplexer and latches using transmission
11. Explain the concept of gate delay in VERILOG with example
12. Explain the concept of MOSFET as switches and also bring the various logic
gates using the switching concept .
13. Explain the concept involved in structural gate level modeling and also give the
description for Half adder and Full adder.
UNIT – V
VERILOG HARDWARE DESCRIPTION LANGUAGE
PART – A (2 Marks)
1. What is Verilog?
2. What are identifiers?
3. What are gate primitives?
4. What are the different kinds of the test bench?
5. Give the two blocks in behavioral modeling.
6. Define FSM.
7. What do you mean by Data flow model?
8. What is Switch-level modeling?
9. Define vector in verilog.
10. What are the different types of modeling Verilog?
11. Give the different types of ASIC.
12. What is the full custom ASIC design?
13. What is the standard cell-based ASIC design?
14. Differentiate between channeled & channel less gate array.
15. Give the constituent of I/O cell in 22V10.
16. What is a FPGA?
17. What are the different methods of programming of PALs?
18. What is an antifuse?
19. What are the different levels of design abstraction at physical design.
20. What are macros?
21. What are Programmable Interconnects ?
22. Give the steps inASIC design flow.
23. Give the XILINX Configurable Logic Block .
24. Give the XILINX FPGA architecture
25. Mention the levels at which testing of a chip can be done?
PART-B (16 Marks)
1. Design a 4-bit carry look ahead adder and write the verilog HDL for it. (16)
2. Design 4X1 multiplexer and write the HDL for it in all four modeling: (16)
3. Briefly explain behavioral modeling(all functions) with an example: (16)
4. Design and develop a project in HDL to compare x5x4x3x2x1x0 with
5. y5y4y3y2y1y0.Check the output by means of test bench. (16)
6. Explain the following with an example:
a. Tasks and functions (4)
b. Test bench for multiplexer (4)
c. Difference between always and initial (4)
d. Blocking and non-blocking statements
7. Explain the ASIC design flow with a neat diagram
8. Explain fault model
9. Briefly explain
i. Fault grading & fault simulation
ii. Delay fault testing
iii. Statistical fault analysis
iv. Fault sampling (4)
10. Explain scan-based test techniques.
11. Explain Ad-Hoc testing and chip level test techniques.
12. Explain self-test techniques and IDDQ testing.
13. Explain system-level test techniques.
14. Explain the chip level test techniques.
15. Explain the system level test techniques
.