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EEL3404
Project 1
Ingrid Bobadilla
July 14th, 2003
5996-7920
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pledge to hold ourselves and our peers to the highest standards of honesty
and integrity.
I.
Hand Calculations
Assumptions
To obtain an overall gain of 50 V/V, three amplifiers were used. The first stage of
the design is composed of a Common – Emitter amplifier which was designed to have a
voltage gain of 20 V/V. The second stage is another Common-Emitter amplifier with an
overall gain of 2.5V/V. For the last stage, a Common-Collector, also known as an Emitter
follower amplifier, was used to provide a gain of 1 V/V. Together, multiplying the gains
of these three stages, an overall gain of 50V/V is obtained.
An input signal of approximately 140mV p-p can be applied to the amplifier.
This input will then be amplified by a factor of 50 to obtain an output voltage of 7V p-p
through the 1kΩ load resistor. To ensure this output, the third stage common collector
amplifier had to be adjusted to provide a minimum current of 3.5mA through the emitter.
This minimum requirement is necessary because the emitter current IE should be greater
than the maximum current through the load resistor by at least 10% to prevent the
transistor from shutting off.
Below is a detailed description of all the calculations made to arrive to a final
design.
3rd Stage Design: Common Collector
The maximum current through the load resistor was calculated using Ohm’s Law. With a
peak output of 3.5V through a 1kΩ load resistor, the current was calculated to be 3.5mA.
To obtain IE greater than this current by 10%, ILmax was multiplied by 1.1 to obtain a
minimum current of 3.85mA. Rounding this to 4mA, the value for re was obtained by
dividing VT/IE = 0.025/4mA = 6.49Ω
Using this value of re , the equation for the input resistance was used as follows:
Rin = (R1//R2)//(B+1)(re + (RL//RE))
Assuming B = 255, R1 = R2 = 100K, RE = 1kΩ and RL = 1kΩ we have that R1//R2 =
50kΩ and substituting the values in the equation we obtain:
Rin = 50k//(256(6.49 + 500)) = 36.1kΩ.
This value of Rin for the third stage acts as the load resistance of the 2nd stage amplifier.
2nd Stage Design: Common Emitter
Using RL = Rin ≈ 36kΩ as above and the sought gain of 2.5 V/V, the equation for a
general common emitter circuit yields:
Av = (Rc//RL)/ (re + Re) = (10k//36k)/(re + Re) = 2.5V/V
Assuming the current in the emitter is about 1mA, re = VT/1mA ≈ 25Ω. Plugging this
value in the equation above and solving for Re we obtain a value of 2.92kΩ, which can
be approximated to the nearest real valued resistor of 3.0kΩ.
The value of Rin for this stage was calculated using the following equation with R1 =
100kΩ and R2 = 51kΩ:
Rin = (R1//R2)//((B+1)(re+Re)) = 33.77k//(256(25+3k)) ≈ 33.8kΩ
This value of Rin is used as the load resistance of the first stage amplifier.
1st stage Design: Common Emitter
In this stage, a gain of 20 V/V is desired. Using the input resistance calculated above for
the second stage as the load for this stage we obtain:
Av = 20 = (Rc//RL)/(re + Re) = (10k//33.8k)/(25+Re)
Again, the value of IE is assumed to be about 1mA, allowing re to be about 25Ω.
Solving for Re in the equation above, we obtain Re ≈ 360Ω.
All the values for R1, R2, RE and RC were randomly chosen to obtain the right values.
After simulating and measuring the output and gain, the final result obtained was an
output of 6.91 Vp-p at an input of 139mVp-p making this a gain of 49.72V/V.
The small variations on the desired output of 7 Vp-p are due to the approximations made
in order to use real-valued resistors.