Download Senior Design 4006C Group G7 Design Report

Senior Design 4006C
Group G7
Design Presentation
1394b – Receiver
The new generation of FireWire.
Luke Starnes (gte874d)
Aparna Trimurty (gt9794a)
Jeff Schlipf (gte877e)
Main components to look at:
• 1394b Ethernet card
• MAX3264 chip and evaluation kit
• MAX3266 chip and evaluation kit
• Extra stuff (power supplies, cable,
connectors)
• Components are designed for 1.25Gbps
Gigabit Ethernet applications
1394b Ethernet Card (cont.)
• Don’t have actual card yet
• Similarly will have OE module like Intel and D-link
cards
Layout of Optical Receiver from
Opto-Electronics module
• We will focus on Transimpedance (TIA) and
Limiting Amplifiers
MAX3266 chip – includes TIA
MAX3266 Stage 1
• the TIA, is a high
gain amplifier that
converts an input
current from the
PhotoDiode to an
output voltage.
•The pair of diodes is used to clamp any input
currents above 1mA.
•Voltage amplifier converts the single-ended
signal into a differential one
MAX3266 Stage 2
• S2) a DC
cancellation circuit is
used to center the
signal around zero.
This is done through
low frequency
feedback.
MAX3266 Stage 3 + 4
• S3) Output Buffer designed as a 100W
differential load
between OUT+ and
OUT• The two 50W resistors between the output buffer
and filter are used to reduce the signal by a factor of
2 through voltage division
• S4) Output Filter - a single pole low pass filter that is
used to limit the circuit’s bandwidth and improve
noise performance
3266 Evaluation Kit
• Simply hook your Photodiode into J1 and your
Limiting Amplifier into J2 and J3 and your ready
to test
But wait…
• We need to determine current going into
system is adequate to support system
and still maintain an open eye throughout
• Sensitivity for MAX3266 must be
evaluated
Math Stuff
•Resistors given
values by specs
of chip
•Rpd = 50W
•Using the eq: Ipd = 0.02*ITIA*(Rin + 1500) and
assuming ITIA is 10mAp-p (for conservation
matters) and Rin = 200ohm…….
Ipd= 340mAp-p
•This is unacceptable
Math stuff (cont.)
• We need to make
some board changes
• R1, R2, and R3 are
removed and
replaced with new R1
•Using improved Eq. Ipd = 0.04*ITIA*Rin and using the
values of ITIA + Rin as before we get 80mAp-p
•This is acceptable with R1 now being 66.7W
Max3264 – Limiting Amplifier
MAX3264 Stage 1
• The chip provides 55dB
of gain. This large gain
makes the amplifier
susceptible to small DC
offsets in the input signal.
DC offsets as low as
1mV will reduce
accuracy and may cause
deterministic jitter
• The input then passes through the offset correction
and low pass filtering portion of the chip. The capacitor
connected between CAZ1 and CAZ2 will determine the
time constant of the offset-correction circuit. This portion
of the circuit is here to reduce input offset
MAX3264 – Stage 2
• The power detector here looks at the signal from
the input buffer and compares it to a threshold
set by the TH resistor. The Resistor value will
depend on the Loss Of Signal (LOS) desired.
• The signal-detect information is provided to the
LOS outputs, which are internally terminated with
a 16kW pull up resistors (RLOS).
MAX3264 Stage 3
• The signal is
outputted to an
output buffer also
has a control module
with two pins for
Level and Squelch
• Level – Allows user to amplify current from 16mA to
20mA by connecting pin to GND
•Squelch (when connected to VCC) holds out+ and
out- at a static voltage whenever the input signal
power drops below the LOS threshold.
MAX3264 Evaluation Kit
•Simply connect your TIA to J4 and J5 and J2 and
J3 to your output and your ready to go. LOS
threshold programming also done here.
The Extras
• Power Supplies producing +3V - +5.5V
needed for Eval Kits.
• SMA Cable and Connectors needed to
link Ethernet Card to OE Mod. Cables
also needed for: photodiode -> TIA ->
limiting amp -> output
Happy Valentines Day!!